CVS commit: src/sys/arch/landisk/landisk

[NONAKA Kimihiro]

Module Name:    src
Committed By:   nonaka
Date:           Sun Mar 21 14:49:29 UTC 2010

Modified Files:
        src/sys/arch/landisk/landisk: bus_dma.c

Log Message:
sync with OpenBSD:r1.3
> bus_dmamap_sync fixes to cope with real life.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/landisk/landisk/bus_dma.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/landisk/landisk/bus_dma.c
diff -u src/sys/arch/landisk/landisk/bus_dma.c:1.10 src/sys/arch/landisk/landisk/bus_dma.c:1.11
--- src/sys/arch/landisk/landisk/bus_dma.c:1.10	Sun Mar 21 13:34:19 2010
+++ src/sys/arch/landisk/landisk/bus_dma.c	Sun Mar 21 14:49:28 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: bus_dma.c,v 1.10 2010/03/21 13:34:19 nonaka Exp $	*/
+/*	$NetBSD: bus_dma.c,v 1.11 2010/03/21 14:49:28 nonaka Exp $	*/
 
 /*
  * Copyright (c) 2005 NONAKA Kimihiro
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.10 2010/03/21 13:34:19 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.11 2010/03/21 14:49:28 nonaka Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -527,21 +527,28 @@
 
 		switch (ops) {
 		case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE:
-			sh_dcache_wbinv_range(naddr, minlen);
+			if (SH_HAS_WRITEBACK_CACHE)
+				sh_dcache_wbinv_range(naddr, minlen);
+			else
+				sh_dcache_inv_range(naddr, minlen);
 			break;
 
 		case BUS_DMASYNC_PREREAD:
-			if (((naddr | minlen) & (~(sh_cache_line_size - 1))) == 0) {
-				sh_dcache_inv_range(naddr, minlen);
-			} else {
+			if (SH_HAS_WRITEBACK_CACHE &&
+			    ((naddr | minlen) & (sh_cache_line_size - 1)) != 0)
 				sh_dcache_wbinv_range(naddr, minlen);
-			}
+			else
+				sh_dcache_inv_range(naddr, minlen);
 			break;
 
 		case BUS_DMASYNC_PREWRITE:
-			if (SH_HAS_WRITEBACK_CACHE) {
+			if (SH_HAS_WRITEBACK_CACHE)
 				sh_dcache_wb_range(naddr, minlen);
-			}
+			break;
+
+		case BUS_DMASYNC_POSTREAD:
+		case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE:
+			sh_dcache_inv_range(naddr, minlen);
 			break;
 		}
 		offset = 0;