Module Name: xsrc
Committed By: mrg
Date: Sat Nov 20 10:02:15 UTC 2010
Modified Files:
xsrc/external/mit/xf86-video-ati/dist/src: r6xx_accel.c radeon_cursor.c
radeon_exa_funcs.c
xsrc/external/mit/xf86-video-ati/dist/src/AtomBios: CD_Operations.c
Removed Files:
xsrc/external/mit/xf86-video-ati/dist/src: local_xf86Rename.h
xsrc/external/mit/xf86-video-ati/dist/src/modes: xf86Crtc.c xf86Crtc.h
xf86Cursors.c xf86DiDGA.c xf86EdidModes.c xf86Modes.c xf86Modes.h
xf86RandR12.c xf86RandR12.h xf86Rename.h xf86Rotate.c xf86cvt.c
xsrc/external/mit/xf86-video-ati/dist/src/parser: xf86Optrec.h
xf86Parser.h
Log Message:
merge xf86-video-ati 6.12.2.
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.1 -r0 \
xsrc/external/mit/xf86-video-ati/dist/src/local_xf86Rename.h
cvs rdiff -u -r1.2 -r1.3 \
xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c
cvs rdiff -u -r1.4 -r1.5 \
xsrc/external/mit/xf86-video-ati/dist/src/radeon_cursor.c \
xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c
cvs rdiff -u -r1.2 -r1.3 \
xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/CD_Operations.c
cvs rdiff -u -r1.1.1.5 -r0 \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86Crtc.c \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86Cursors.c \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86EdidModes.c \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86Modes.c \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86RandR12.c \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86Rotate.c
cvs rdiff -u -r1.1.1.4 -r0 \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86Crtc.h \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86Modes.h
cvs rdiff -u -r1.1.1.3 -r0 \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86DiDGA.c \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86RandR12.h
cvs rdiff -u -r1.1.1.2 -r0 \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86Rename.h \
xsrc/external/mit/xf86-video-ati/dist/src/modes/xf86cvt.c
cvs rdiff -u -r1.1.1.3 -r0 \
xsrc/external/mit/xf86-video-ati/dist/src/parser/xf86Optrec.h
cvs rdiff -u -r1.1.1.4 -r0 \
xsrc/external/mit/xf86-video-ati/dist/src/parser/xf86Parser.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c:1.2 xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c:1.3
--- xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c:1.2 Sat Jul 17 07:55:34 2010
+++ xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c Sat Nov 20 10:02:14 2010
@@ -39,6 +39,7 @@
#include "radeon_drm.h"
#include "radeon_vbo.h"
+#include "radeon_exa_shared.h"
/* we try and batch operations together under KMS -
but it doesn't work yet without misrendering */
@@ -85,34 +86,9 @@
void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib)
{
#if defined(XF86DRM_MODE)
- int ret;
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->cs) {
- if (info->accel_state->ib_reset_op) {
- /* if we have data just reset the CS and ignore the operation */
- info->cs->cdw = info->accel_state->ib_reset_op;
- info->accel_state->ib_reset_op = 0;
- return;
- }
- if (info->accel_state->vb_ptr) {
- info->accel_state->vb_ptr = NULL;
- }
-
- info->accel_state->vb_offset = 0;
- info->accel_state->vb_start_op = -1;
-
- if (CS_FULL(info->cs)) {
- radeon_cs_flush_indirect(pScrn);
- return;
- }
- radeon_cs_erase(info->cs);
- ret = radeon_cs_space_check(info->cs);
- if (ret)
- ErrorF("space check failed in flush\n");
- if (info->dri2.enabled) {
- info->accel_state->XInited3D = FALSE;
- info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
- }
+ radeon_ib_discard(pScrn);
}
#endif
if (!ib) return;
@@ -282,19 +258,24 @@
EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256
RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
- BEGIN_BATCH(12);
+ BEGIN_BATCH(9);
// pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) |
(slice << SLICE_TILE_MAX_shift)));
EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) |
(0 << SLICE_MAX_shift)));
- EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) |
(0 << FMASK_TILE_MAX_shift)));
END_BATCH();
+
+ BEGIN_BATCH(3 + 2);
+ EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
+ END_BATCH();
+
}
-void
+static void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain)
{
@@ -437,6 +418,11 @@
if (vs_conf->uncached_first_inst)
sq_pgm_resources |= UNCACHED_FIRST_INST_bit;
+ /* flush SQ cache */
+ cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
+ vs_conf->shader_size, vs_conf->shader_addr,
+ vs_conf->bo, domain, 0);
+
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
RELOC_BATCH(vs_conf->bo, domain, 0);
@@ -466,6 +452,11 @@
if (ps_conf->clamp_consts)
sq_pgm_resources |= CLAMP_CONSTS_bit;
+ /* flush SQ cache */
+ cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
+ ps_conf->shader_size, ps_conf->shader_addr,
+ ps_conf->bo, domain, 0);
+
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
RELOC_BATCH(ps_conf->bo, domain, 0);
@@ -504,10 +495,11 @@
END_BATCH();
}
-void
+static void
set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
uint32_t sq_vtx_constant_word2;
sq_vtx_constant_word2 = ((((res->vb_addr) >> 32) & BASE_ADDRESS_HI_mask) |
@@ -524,6 +516,22 @@
if (res->srf_mode_all)
sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit;
+ /* flush vertex cache */
+ if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
+ (info->ChipFamily == CHIP_FAMILY_RV620) ||
+ (info->ChipFamily == CHIP_FAMILY_RS780) ||
+ (info->ChipFamily == CHIP_FAMILY_RS880) ||
+ (info->ChipFamily == CHIP_FAMILY_RV710))
+ cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
+ accel_state->vb_offset, accel_state->vb_mc_addr,
+ res->bo,
+ domain, 0);
+ else
+ cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit,
+ accel_state->vb_offset, accel_state->vb_mc_addr,
+ res->bo,
+ domain, 0);
+
BEGIN_BATCH(9 + 2);
PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7);
E32(ib, res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS
@@ -590,6 +598,11 @@
if (tex_res->interlaced)
sq_tex_resource_word6 |= INTERLACED_bit;
+ /* flush texture cache */
+ cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
+ tex_res->size, tex_res->base,
+ tex_res->bo, domain, 0);
+
BEGIN_BATCH(9 + 4);
PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7);
E32(ib, sq_tex_resource_word0);
@@ -877,10 +890,16 @@
sq_setup(pScrn, ib, &sq_conf);
- BEGIN_BATCH(83);
+ /* set fake reloc for unused depth */
+ BEGIN_BATCH(3 + 2);
+ EREG(ib, DB_DEPTH_INFO, 0);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ END_BATCH();
+
+ BEGIN_BATCH(80);
if (info->ChipFamily < CHIP_FAMILY_RV770) {
EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
- - (28 << TD_FIFO_CREDIT_shift)));
+ (28 << TD_FIFO_CREDIT_shift)));
EREG(ib, VC_ENHANCE, 0);
EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
EREG(ib, DB_DEBUG, 0x82000000); /* ? */
@@ -892,7 +911,7 @@
0));
} else {
EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) |
- - (28 << TD_FIFO_CREDIT_shift)));
+ (28 << TD_FIFO_CREDIT_shift)));
EREG(ib, VC_ENHANCE, 0);
EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
EREG(ib, DB_DEBUG, 0);
@@ -920,7 +939,6 @@
E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
// DB
- EREG(ib, DB_DEPTH_INFO, 0);
EREG(ib, DB_DEPTH_CONTROL, 0);
PACK0(ib, DB_RENDER_CONTROL, 2);
E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
@@ -1038,7 +1056,7 @@
// VGT
BEGIN_BATCH(43);
PACK0(ib, VGT_MAX_VTX_INDX, 4);
- E32(ib, 2048); /* XXX set to a reasonably large number of indices */ // VGT_MAX_VTX_INDX
+ E32(ib, 0xffffff); // VGT_MAX_VTX_INDX
E32(ib, 0); // VGT_MIN_VTX_INDX
E32(ib, 0); // VGT_INDX_OFFSET
E32(ib, 0); // VGT_MULTI_PRIM_IB_RESET_INDX
@@ -1138,57 +1156,6 @@
END_BATCH();
}
-Bool
-r600_vb_get(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- accel_state->vb_mc_addr = info->gartLocation + info->dri->bufStart +
- (accel_state->ib->idx*accel_state->ib->total)+
- (accel_state->ib->total / 2);
- accel_state->vb_total = (accel_state->ib->total / 2);
- accel_state->vb_ptr = (pointer)((char*)accel_state->ib->address +
- (accel_state->ib->total / 2));
- accel_state->vb_offset = 0;
- return TRUE;
-}
-
-void
-r600_vb_discard(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- info->accel_state->vb_start_op = -1;
-}
-
-
-
-int
-r600_cp_start(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
-#if defined(XF86DRM_MODE)
- if (info->cs) {
- if (CS_FULL(info->cs)) {
- radeon_cs_flush_indirect(pScrn);
- }
- accel_state->ib_reset_op = info->cs->cdw;
- accel_state->vb_start_op = accel_state->vb_offset;
- } else
-#endif
- {
- accel_state->ib = RADEONCPGetBuffer(pScrn);
- if (!r600_vb_get(pScrn)) {
- return -1;
- }
- accel_state->vb_start_op = accel_state->vb_offset;
- }
- return 0;
-}
-
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -1204,26 +1171,10 @@
if (accel_state->vb_offset == accel_state->vb_start_op) {
R600IBDiscard(pScrn, accel_state->ib);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return;
}
- /* flush vertex cache */
- if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
- (info->ChipFamily == CHIP_FAMILY_RV620) ||
- (info->ChipFamily == CHIP_FAMILY_RS780) ||
- (info->ChipFamily == CHIP_FAMILY_RS880) ||
- (info->ChipFamily == CHIP_FAMILY_RV710))
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
- accel_state->vb_bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- else
- cp_set_surface_sync(pScrn, accel_state->ib, VC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
- accel_state->vb_bo,
- RADEON_GEM_DOMAIN_GTT, 0);
-
/* Vertex buffer setup */
accel_state->vb_size = accel_state->vb_offset - accel_state->vb_start_op;
vtx_res.id = SQ_VTX_RESOURCE_vs;
@@ -1260,31 +1211,3 @@
R600CPFlushIndirect(pScrn, accel_state->ib);
}
-void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
-#ifdef XF86DRM_MODE
- if (info->cs) {
- if (accel_state->vb_bo) {
- if (accel_state->vb_start_op != accel_state->vb_offset) {
- r600_finish_op(pScrn, vert_size);
- accel_state->ib_reset_op = info->cs->cdw;
- }
-
- /* release the current VBO */
- radeon_vbo_put(pScrn);
- }
-
- /* get a new one */
- radeon_vbo_get(pScrn);
- return;
- }
-#endif
-
- if (accel_state->vb_start_op != -1) {
- r600_finish_op(pScrn, vert_size);
- r600_cp_start(pScrn);
- }
-}
Index: xsrc/external/mit/xf86-video-ati/dist/src/radeon_cursor.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/radeon_cursor.c:1.4 xsrc/external/mit/xf86-video-ati/dist/src/radeon_cursor.c:1.5
--- xsrc/external/mit/xf86-video-ati/dist/src/radeon_cursor.c:1.4 Sat Jul 17 06:34:13 2010
+++ xsrc/external/mit/xf86-video-ati/dist/src/radeon_cursor.c Sat Nov 20 10:02:14 2010
@@ -225,7 +225,7 @@
if (IS_DCE4_VARIANT) {
evergreen_lock_cursor(crtc, TRUE);
evergreen_setup_cursor(crtc, FALSE);
- evergreen_lock_cursor(crtc, TRUE);
+ evergreen_lock_cursor(crtc, FALSE);
} else if (IS_AVIVO_VARIANT) {
avivo_lock_cursor(crtc, TRUE);
avivo_setup_cursor(crtc, FALSE);
@@ -265,7 +265,12 @@
if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
if (IS_DCE4_VARIANT) {
- /* XXX - does evergreen need a similar hack as below? */
+ /* avivo cursor spans the full fb width */
+ if (crtc->rotatedData == NULL) {
+ x += crtc->x;
+ y += crtc->y;
+ }
+
evergreen_lock_cursor(crtc, TRUE);
OUTREG(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y));
Index: xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c:1.4 xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c:1.5
--- xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c:1.4 Sat Jul 17 06:34:13 2010
+++ xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c Sat Nov 20 10:02:14 2010
@@ -459,7 +459,8 @@
ScreenPtr pScreen = pDst->drawable.pScreen;
RINFO_FROM_SCREEN(pScreen);
struct radeon_exa_pixmap_priv *driver_priv;
- struct radeon_bo *scratch;
+ struct radeon_bo *scratch = NULL;
+ struct radeon_bo *copy_dst;
unsigned char *dst;
unsigned size;
uint32_t datatype = 0;
@@ -467,7 +468,10 @@
uint32_t dst_pitch_offset;
unsigned bpp = pDst->drawable.bitsPerPixel;
uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64);
+ uint32_t copy_pitch;
uint32_t swap = RADEON_HOST_DATA_SWAP_NONE;
+ int ret;
+ Bool flush = TRUE;
Bool r;
int i;
@@ -489,55 +493,52 @@
}
#endif
- /* If we know the BO won't be busy, don't bother */
- if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs) &&
- !radeon_bo_is_busy(driver_priv->bo, &dst_domain)) {
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* Can't return FALSE here if we need to swap bytes */
- if (swap != RADEON_HOST_DATA_SWAP_NONE &&
- driver_priv->bo != info->front_bo) {
- scratch = driver_priv->bo;
- scratch_pitch = pDst->devKind;
+ /* If we know the BO won't be busy, don't bother with a scratch */
+ copy_dst = driver_priv->bo;
+ copy_pitch = pDst->devKind;
+ if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+ flush = FALSE;
+ if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
goto copy;
- }
-#endif
- return FALSE;
}
size = scratch_pitch * h;
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
if (scratch == NULL) {
- return FALSE;
+ goto copy;
}
radeon_cs_space_reset_bos(info->cs);
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
radeon_cs_space_add_persistent_bo(info->cs, scratch, RADEON_GEM_DOMAIN_GTT, 0);
- r = radeon_cs_space_check(info->cs);
- if (r) {
- r = FALSE;
- goto out;
- }
+ ret = radeon_cs_space_check(info->cs);
+ if (ret) {
+ goto copy;
+ }
+ copy_dst = scratch;
+ copy_pitch = scratch_pitch;
+ flush = FALSE;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
copy:
-#endif
- r = radeon_bo_map(scratch, 0);
- if (r) {
+ if (flush)
+ radeon_cs_flush_indirect(pScrn);
+
+ ret = radeon_bo_map(copy_dst, 0);
+ if (ret) {
r = FALSE;
goto out;
}
r = TRUE;
size = w * bpp / 8;
- dst = scratch->ptr;
- if (scratch == driver_priv->bo)
- dst += y * scratch_pitch + x * bpp / 8;
+ dst = copy_dst->ptr;
+ if (copy_dst == driver_priv->bo)
+ dst += y * copy_pitch + x * bpp / 8;
for (i = 0; i < h; i++) {
- RADEONCopySwap(dst + i * scratch_pitch, (uint8_t*)src, size, swap);
+ RADEONCopySwap(dst + i * copy_pitch, (uint8_t*)src, size, swap);
src += src_pitch;
}
- radeon_bo_unmap(scratch);
+ radeon_bo_unmap(copy_dst);
- if (scratch != driver_priv->bo) {
+ if (copy_dst == scratch) {
RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype);
RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset);
ACCEL_PREAMBLE();
@@ -548,7 +549,7 @@
}
out:
- if (scratch != driver_priv->bo)
+ if (scratch)
radeon_bo_unref(scratch);
return r;
}
@@ -559,14 +560,18 @@
{
RINFO_FROM_SCREEN(pSrc->drawable.pScreen);
struct radeon_exa_pixmap_priv *driver_priv;
- struct radeon_bo *scratch;
+ struct radeon_bo *scratch = NULL;
+ struct radeon_bo *copy_src;
unsigned size;
uint32_t datatype = 0;
uint32_t src_domain = 0;
uint32_t src_pitch_offset;
unsigned bpp = pSrc->drawable.bitsPerPixel;
uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64);
+ uint32_t copy_pitch;
uint32_t swap = RADEON_HOST_DATA_SWAP_NONE;
+ int ret;
+ Bool flush = FALSE;
Bool r;
if (bpp < 8)
@@ -587,41 +592,36 @@
}
#endif
- /* If we know the BO won't end up in VRAM anyway, don't bother */
+ /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
+ copy_src = driver_priv->bo;
+ copy_pitch = pSrc->devKind;
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
src_domain = 0;
+ else /* A write may be scheduled */
+ flush = TRUE;
}
if (!src_domain)
radeon_bo_is_busy(driver_priv->bo, &src_domain);
- if (src_domain != RADEON_GEM_DOMAIN_VRAM) {
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* Can't return FALSE here if we need to swap bytes */
- if (swap != RADEON_HOST_DATA_SWAP_NONE) {
- scratch = driver_priv->bo;
- scratch_pitch = pSrc->devKind;
- goto copy;
- }
-#endif
- return FALSE;
+ if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) {
+ goto copy;
}
size = scratch_pitch * h;
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
if (scratch == NULL) {
- return FALSE;
+ goto copy;
}
radeon_cs_space_reset_bos(info->cs);
radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, RADEON_GEM_DOMAIN_GTT);
- r = radeon_cs_space_check(info->cs);
- if (r) {
- r = FALSE;
- goto out;
+ ret = radeon_cs_space_check(info->cs);
+ if (ret) {
+ goto copy;
}
RADEONGetDatatypeBpp(pSrc->drawable.bitsPerPixel, &datatype);
RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset);
@@ -631,30 +631,34 @@
scratch_pitch << 16, x, y, 0, 0, w, h,
RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT,
RADEON_GEM_DOMAIN_GTT);
- FLUSH_RING();
+ copy_src = scratch;
+ copy_pitch = scratch_pitch;
+ flush = TRUE;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
copy:
-#endif
- r = radeon_bo_map(scratch, 0);
- if (r) {
+ if (flush)
+ FLUSH_RING();
+
+ ret = radeon_bo_map(copy_src, 0);
+ if (ret) {
+ ErrorF("failed to map pixmap: %d\n", ret);
r = FALSE;
goto out;
}
r = TRUE;
w *= bpp / 8;
- if (scratch == driver_priv->bo)
- size = y * scratch_pitch + x * bpp / 8;
+ if (copy_src == driver_priv->bo)
+ size = y * copy_pitch + x * bpp / 8;
else
size = 0;
while (h--) {
- RADEONCopySwap((uint8_t*)dst, scratch->ptr + size, w, swap);
- size += scratch_pitch;
+ RADEONCopySwap((uint8_t*)dst, copy_src->ptr + size, w, swap);
+ size += copy_pitch;
dst += dst_pitch;
}
- radeon_bo_unmap(scratch);
+ radeon_bo_unmap(copy_src);
out:
- if (scratch != driver_priv->bo)
+ if (scratch)
radeon_bo_unref(scratch);
return r;
}
Index: xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/CD_Operations.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/CD_Operations.c:1.2 xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/CD_Operations.c:1.3
--- xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/CD_Operations.c:1.2 Tue Aug 10 02:57:44 2010
+++ xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/CD_Operations.c Sat Nov 20 10:02:14 2010
@@ -367,7 +367,7 @@
UINT32 data;
pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- data = UINT32LE_TO_CPU(*(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index));
+ data = UINT32LE_TO_CPU(ldl_u(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index));
return data;
}
@@ -430,7 +430,7 @@
pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
- ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock));
+ ret = UINT32LE_TO_CPU(ldl_u((UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock)));
return ret;
}
@@ -453,7 +453,7 @@
UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentDword;
- pParserTempData->Index=UINT32LE_TO_CPU(*(UINT32*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT32LE_TO_CPU(ldl_u((UINT32*)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT32);
return pParserTempData->Index;
}
