Module Name: src
Committed By: matt
Date: Wed Dec 29 01:44:21 UTC 2010
Modified Files:
src/sys/arch/arc/arc [matt-nb5-mips64]: autoconf.c c_magnum.c
c_nec_eisa.c c_nec_pci.c interrupt.c p_dti_arcstation.c
p_dti_tyne.c p_sni_rm200pci.c
src/sys/arch/arc/include [matt-nb5-mips64]: intr.h
Log Message:
Adapt to the new interrupt structure.
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.32.36.1 src/sys/arch/arc/arc/autoconf.c
cvs rdiff -u -r1.19 -r1.19.22.1 src/sys/arch/arc/arc/c_magnum.c
cvs rdiff -u -r1.15 -r1.15.16.1 src/sys/arch/arc/arc/c_nec_eisa.c
cvs rdiff -u -r1.17 -r1.17.36.1 src/sys/arch/arc/arc/c_nec_pci.c
cvs rdiff -u -r1.4.22.1 -r1.4.22.2 src/sys/arch/arc/arc/interrupt.c
cvs rdiff -u -r1.13 -r1.13.36.1 src/sys/arch/arc/arc/p_dti_arcstation.c
cvs rdiff -u -r1.16 -r1.16.36.1 src/sys/arch/arc/arc/p_dti_tyne.c
cvs rdiff -u -r1.12 -r1.12.36.1 src/sys/arch/arc/arc/p_sni_rm200pci.c
cvs rdiff -u -r1.22.18.1 -r1.22.18.2 src/sys/arch/arc/include/intr.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arc/arc/autoconf.c
diff -u src/sys/arch/arc/arc/autoconf.c:1.32 src/sys/arch/arc/arc/autoconf.c:1.32.36.1
--- src/sys/arch/arc/arc/autoconf.c:1.32 Mon Dec 3 15:33:12 2007
+++ src/sys/arch/arc/arc/autoconf.c Wed Dec 29 01:44:20 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.32 2007/12/03 15:33:12 ad Exp $ */
+/* $NetBSD: autoconf.c,v 1.32.36.1 2010/12/29 01:44:20 matt Exp $ */
/* $OpenBSD: autoconf.c,v 1.9 1997/05/18 13:45:20 pefo Exp $ */
/*
@@ -88,7 +88,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.32 2007/12/03 15:33:12 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.32.36.1 2010/12/29 01:44:20 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -148,9 +148,10 @@
* to disable it other than setting status register by spl(9).
*/
_spllower(MIPS_INT_MASK_5);
+#error need fix
#else
/* enable all source forcing SOFT_INTs cleared */
- _splnone();
+ spl0();
#endif
}
Index: src/sys/arch/arc/arc/c_magnum.c
diff -u src/sys/arch/arc/arc/c_magnum.c:1.19 src/sys/arch/arc/arc/c_magnum.c:1.19.22.1
--- src/sys/arch/arc/arc/c_magnum.c:1.19 Fri Mar 14 16:43:27 2008
+++ src/sys/arch/arc/arc/c_magnum.c Wed Dec 29 01:44:20 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: c_magnum.c,v 1.19 2008/03/14 16:43:27 tsutsui Exp $ */
+/* $NetBSD: c_magnum.c,v 1.19.22.1 2010/12/29 01:44:20 matt Exp $ */
/* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
/*
@@ -80,11 +80,14 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: c_magnum.c,v 1.19 2008/03/14 16:43:27 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: c_magnum.c,v 1.19.22.1 2010/12/29 01:44:20 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
+#include <sys/intr.h>
#include <sys/device.h>
+
#include <uvm/uvm_extern.h>
#include <machine/autoconf.h>
@@ -120,26 +123,20 @@
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
-static const uint32_t magnum_ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+static const struct ipl_sr_map magnum_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_1
+ | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_3,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
uint32_t
@@ -230,7 +227,7 @@
/*
* Initialize interrupt priority
*/
- ipl_sr_bits = magnum_ipl_sr_bits;
+ ipl_sr_map = magnum_ipl_sr_map;
/*
* Initialize I/O address offset
Index: src/sys/arch/arc/arc/c_nec_eisa.c
diff -u src/sys/arch/arc/arc/c_nec_eisa.c:1.15 src/sys/arch/arc/arc/c_nec_eisa.c:1.15.16.1
--- src/sys/arch/arc/arc/c_nec_eisa.c:1.15 Wed May 14 13:29:27 2008
+++ src/sys/arch/arc/arc/c_nec_eisa.c Wed Dec 29 01:44:20 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: c_nec_eisa.c,v 1.15 2008/05/14 13:29:27 tsutsui Exp $ */
+/* $NetBSD: c_nec_eisa.c,v 1.15.16.1 2010/12/29 01:44:20 matt Exp $ */
/*-
* Copyright (c) 2003 Izumi Tsutsui. All rights reserved.
@@ -55,12 +55,15 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: c_nec_eisa.c,v 1.15 2008/05/14 13:29:27 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: c_nec_eisa.c,v 1.15.16.1 2010/12/29 01:44:20 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kcore.h>
#include <sys/device.h>
+#include <sys/intr.h>
+
#include <uvm/uvm_extern.h>
#include <machine/autoconf.h>
@@ -103,25 +106,19 @@
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
-static const uint32_t nec_eisa_ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+static const struct ipl_sr_map nec_eisa_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_1
+ | MIPS_INT_MASK_2,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
int
@@ -161,7 +158,7 @@
/*
* Initialize interrupt priority
*/
- ipl_sr_bits = nec_eisa_ipl_sr_bits;
+ ipl_sr_map = nec_eisa_ipl_sr_map;
/*
* Initialize I/O address offset
Index: src/sys/arch/arc/arc/c_nec_pci.c
diff -u src/sys/arch/arc/arc/c_nec_pci.c:1.17 src/sys/arch/arc/arc/c_nec_pci.c:1.17.36.1
--- src/sys/arch/arc/arc/c_nec_pci.c:1.17 Mon Dec 3 15:33:13 2007
+++ src/sys/arch/arc/arc/c_nec_pci.c Wed Dec 29 01:44:20 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: c_nec_pci.c,v 1.17 2007/12/03 15:33:13 ad Exp $ */
+/* $NetBSD: c_nec_pci.c,v 1.17.36.1 2010/12/29 01:44:20 matt Exp $ */
/*-
* Copyright (C) 2000 Shuichiro URATA. All rights reserved.
@@ -31,12 +31,15 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: c_nec_pci.c,v 1.17 2007/12/03 15:33:13 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: c_nec_pci.c,v 1.17.36.1 2010/12/29 01:44:20 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kcore.h>
#include <sys/device.h>
+#include <sys/intr.h>
+
#include <uvm/uvm_extern.h>
#include <machine/autoconf.h>
@@ -110,25 +113,19 @@
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
-static const uint32_t nec_pci_ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+static const struct ipl_sr_map nec_pci_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_1
+ | MIPS_INT_MASK_2,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
static u_int
@@ -186,7 +183,7 @@
/*
* Initialize interrupt priority
*/
- ipl_sr_bits = nec_pci_ipl_sr_bits;
+ ipl_sr_map = nec_pci_ipl_sr_map;
/*
* Initialize I/O address offset
Index: src/sys/arch/arc/arc/interrupt.c
diff -u src/sys/arch/arc/arc/interrupt.c:1.4.22.1 src/sys/arch/arc/arc/interrupt.c:1.4.22.2
--- src/sys/arch/arc/arc/interrupt.c:1.4.22.1 Fri Feb 5 07:39:52 2010
+++ src/sys/arch/arc/arc/interrupt.c Wed Dec 29 01:44:20 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.4.22.1 2010/02/05 07:39:52 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.4.22.2 2010/12/29 01:44:20 matt Exp $ */
/* $OpenBSD: trap.c,v 1.22 1999/05/24 23:08:59 jason Exp $ */
/*
@@ -78,7 +78,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.4.22.1 2010/02/05 07:39:52 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.4.22.2 2010/12/29 01:44:20 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -135,73 +135,58 @@
/*
* Handle an interrupt.
- * N.B., curlwp might be NULL.
*/
void
-cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- struct clockframe cf;
struct cpu_inttab *inttab;
- struct cpu_info *ci;
- uint32_t handled;
+ struct clockframe cf;
+ uint32_t ipending;
u_int i;
+ int ipl;
- handled = 0;
- ci = curcpu();
uvmexp.intrs++;
- ci->ci_idepth++;
cf.pc = pc;
cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 1);
- /* check MIPS3 internal clock interrupt */
- if (ipending & MIPS_INT_MASK_5) {
+ while (ppl < (ipl = splintr(&ipending))) {
+ /* check MIPS3 internal clock interrupt */
+ if (ipending & MIPS_INT_MASK_5) {
#ifdef ENABLE_INT5_STATCLOCK
- /* call statclock(9) handler */
- statclockintr(&cf);
- statclock_ev.ev_count++;
+ /* call statclock(9) handler */
+ statclockintr(&cf);
+ statclock_ev.ev_count++;
#else
- /*
- * Writing a value to the Compare register,
- * as a side effect, clears the timer interrupt request.
- */
- mips3_cp0_compare_write(0);
+ /*
+ * Writing a value to the Compare register, as a side
+ * effect, clears the timer interrupt request.
+ */
+ mips3_cp0_compare_write(0);
+ }
#endif
- handled |= MIPS_INT_MASK_5;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
-
- /*
- * If there is an independent timer interrupt handler, call it first.
- * Called interrupt routine returns mask of interrupts to be reenabled.
- */
- inttab = &cpu_int_tab[ARC_INTPRI_TIMER_INT];
- if (inttab->int_mask & ipending) {
- handled |= (*inttab->int_hand)(ipending, &cf);
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
- inttab++;
-
- /*
- * Check off all other enabled interrupts.
- * Called handlers return mask of interrupts to be reenabled.
- */
- for (i = ARC_INTPRI_TIMER_INT + 1; i < ARC_NINTPRI; i++) {
+ /*
+ * If there is an independent timer interrupt handler,
+ * call it first.
+ */
+ inttab = &cpu_int_tab[ARC_INTPRI_TIMER_INT];
if (inttab->int_mask & ipending) {
- handled |= (*inttab->int_hand)(ipending, &cf);
+ (*inttab->int_hand)(ipending, &cf);
+ }
+
+ /*
+ * Check off all other enabled interrupts.
+ * Called handlers return mask of interrupts to be reenabled.
+ */
+ for (inttab++, i = ARC_INTPRI_TIMER_INT + 1;
+ i < ARC_NINTPRI;
+ inttab++, i++) {
+ if (inttab->int_mask & ipending) {
+ (*inttab->int_hand)(ipending, &cf);
+ }
}
- inttab++;
+ (void)splhigh();
}
- cause &= ~handled;
- _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
- ci->ci_idepth--;
-
-#ifdef __HAVE_FAST_SOFTINTS
- /* software interrupts */
- ipending &= MIPS_SOFT_INT_MASK;
- if (ipending == 0)
- return;
- softint_process(ipending);
-#endif
}
Index: src/sys/arch/arc/arc/p_dti_arcstation.c
diff -u src/sys/arch/arc/arc/p_dti_arcstation.c:1.13 src/sys/arch/arc/arc/p_dti_arcstation.c:1.13.36.1
--- src/sys/arch/arc/arc/p_dti_arcstation.c:1.13 Mon Dec 3 15:33:14 2007
+++ src/sys/arch/arc/arc/p_dti_arcstation.c Wed Dec 29 01:44:20 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: p_dti_arcstation.c,v 1.13 2007/12/03 15:33:14 ad Exp $ */
+/* $NetBSD: p_dti_arcstation.c,v 1.13.36.1 2010/12/29 01:44:20 matt Exp $ */
/* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
/*
@@ -76,11 +76,14 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: p_dti_arcstation.c,v 1.13 2007/12/03 15:33:14 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: p_dti_arcstation.c,v 1.13.36.1 2010/12/29 01:44:20 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
+#include <sys/intr.h>
+
#include <uvm/uvm_extern.h>
#include <machine/autoconf.h>
@@ -137,28 +140,16 @@
* given interrupt priority level.
*/
/* XXX see comments in p_dti_arcstation_init() */
-static const uint32_t dti_arcstation_ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] = /* XXX */
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_3|
- MIPS_INT_MASK_4|
- MIPS_INT_MASK_5,
- [IPL_SCHED] = /* XXX */
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_3|
- MIPS_INT_MASK_4|
- MIPS_INT_MASK_5,
+static const struct ipl_sr_map dti_arcstation_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_INT_MASK, /* XXX */
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
#if NPC_ISA > 0 || NOPMS_ISA > 0
@@ -248,7 +239,7 @@
* or
* - use MIP3_INTERNAL_TIMER_INTERRUPT for clock
*/
- ipl_sr_bits = dti_arcstation_ipl_sr_bits;
+ ipl_sr_map = dti_arcstation_ipl_sr_map;
/*
* XXX - should be enabled, if tested.
Index: src/sys/arch/arc/arc/p_dti_tyne.c
diff -u src/sys/arch/arc/arc/p_dti_tyne.c:1.16 src/sys/arch/arc/arc/p_dti_tyne.c:1.16.36.1
--- src/sys/arch/arc/arc/p_dti_tyne.c:1.16 Mon Dec 3 15:33:14 2007
+++ src/sys/arch/arc/arc/p_dti_tyne.c Wed Dec 29 01:44:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: p_dti_tyne.c,v 1.16 2007/12/03 15:33:14 ad Exp $ */
+/* $NetBSD: p_dti_tyne.c,v 1.16.36.1 2010/12/29 01:44:21 matt Exp $ */
/* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
/*
@@ -75,8 +75,9 @@
* from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
*/
+#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: p_dti_tyne.c,v 1.16 2007/12/03 15:33:14 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: p_dti_tyne.c,v 1.16.36.1 2010/12/29 01:44:21 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -138,28 +139,18 @@
* given interrupt priority level.
*/
/* XXX see comments in p_dti_tyne_init() */
-static const uint32_t dti_tyne_ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] =0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] = /* XXX */
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_3|
- MIPS_INT_MASK_4|
- MIPS_INT_MASK_5,
- [IPL_SCHED] = /* XXX */
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_3|
- MIPS_INT_MASK_4|
- MIPS_INT_MASK_5,
+static const struct ipl_sr_map dti_tyne_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_INT_MASK, /* XXX */
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
#if NPC_ISA > 0 || NOPMS_ISA > 0
@@ -241,7 +232,7 @@
* or
* - use MIP3_INTERNAL_TIMER_INTERRUPT for clock
*/
- ipl_sr_bits = dti_tyne_ipl_sr_bits;
+ ipl_sr_map = dti_tyne_ipl_sr_map;
/*
* XXX - should be enabled, if tested.
Index: src/sys/arch/arc/arc/p_sni_rm200pci.c
diff -u src/sys/arch/arc/arc/p_sni_rm200pci.c:1.12 src/sys/arch/arc/arc/p_sni_rm200pci.c:1.12.36.1
--- src/sys/arch/arc/arc/p_sni_rm200pci.c:1.12 Mon Dec 3 15:33:14 2007
+++ src/sys/arch/arc/arc/p_sni_rm200pci.c Wed Dec 29 01:44:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: p_sni_rm200pci.c,v 1.12 2007/12/03 15:33:14 ad Exp $ */
+/* $NetBSD: p_sni_rm200pci.c,v 1.12.36.1 2010/12/29 01:44:21 matt Exp $ */
/* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
/*
@@ -75,12 +75,15 @@
* from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
*/
+#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: p_sni_rm200pci.c,v 1.12 2007/12/03 15:33:14 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: p_sni_rm200pci.c,v 1.12.36.1 2010/12/29 01:44:21 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
+#include <sys/intr.h>
+
#include <uvm/uvm_extern.h>
#include <machine/autoconf.h>
@@ -121,28 +124,16 @@
* given interrupt priority level.
*/
/* XXX lack of hardware info for sni_rm200pci */
-static const uint32_t sni_rm200pci_ipl_sr_bits[_IPL_N] = {
+static const struct ipl_sr_map sni_rm200pci_ipl_sr_map = {
+ .sr_bits = {
[IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] = /* XXX */
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
- [IPL_SCHED] = /* XXX */
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_INT_MASK, /* XXX */
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
/*
@@ -159,7 +150,7 @@
/*
* Initialize interrupt priority
*/
- ipl_sr_bits = sni_rm200pci_ipl_sr_bits;
+ ipl_sr_map = sni_rm200pci_ipl_sr_map;
/*
* XXX - should be enabled, if tested.
Index: src/sys/arch/arc/include/intr.h
diff -u src/sys/arch/arc/include/intr.h:1.22.18.1 src/sys/arch/arc/include/intr.h:1.22.18.2
--- src/sys/arch/arc/include/intr.h:1.22.18.1 Sat Feb 6 02:57:43 2010
+++ src/sys/arch/arc/include/intr.h Wed Dec 29 01:44:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.22.18.1 2010/02/06 02:57:43 matt Exp $ */
+/* $NetBSD: intr.h,v 1.22.18.2 2010/12/29 01:44:21 matt Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -32,61 +32,11 @@
#ifndef _ARC_INTR_H_
#define _ARC_INTR_H_
-#define IPL_NONE 0 /* disable only this interrupt */
-#define IPL_SOFTCLOCK 1 /* generic software interrupts (SI 0) */
-#define IPL_SOFTBIO 1 /* clock software interrupts (SI 0) */
-#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
-#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
-#define IPL_VM 3
-#define IPL_SCHED 4
-#define IPL_HIGH 4
-
-#define _IPL_N 5
-
-#define _IPL_SI0_FIRST IPL_SOFTCLOCK
-#define _IPL_SI0_LAST IPL_SOFTBIO
-
-#define _IPL_SI1_FIRST IPL_SOFTNET
-#define _IPL_SI1_LAST IPL_SOFTSERIAL
-
-/* Interrupt sharing types. */
-#define IST_NONE 0 /* none */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
+#include <mips/intr.h>
#ifdef _KERNEL
#ifndef _LOCORE
-#include <mips/locore.h>
-
-extern const uint32_t *ipl_sr_bits;
-
-#define spl0() (void)_spllower(0)
-#define splx(s) (void)_splset(s)
-
-typedef int ipl_t;
-typedef struct {
- ipl_t _sr;
-} ipl_cookie_t;
-
-static inline ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
-}
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._sr);
-}
-
-#include <sys/spl.h>
-
-struct clockframe;
void arc_set_intr(uint32_t, uint32_t (*)(uint32_t, struct clockframe *), int);
extern uint32_t cpu_int_mask;
