Module Name: src
Committed By: matt
Date: Wed Dec 29 08:16:23 UTC 2010
Modified Files:
src/sys/arch/ews4800mips/ews4800mips [matt-nb5-mips64]: autoconf.c
interrupt.c mainbus.c tr2.c tr2_intr.c tr2a.c tr2a_intr.c
src/sys/arch/ews4800mips/include [matt-nb5-mips64]: intr.h sbdvar.h
src/sys/arch/hpcmips/hpcmips [matt-nb5-mips64]: autoconf.c
hpcapm_machdep.c interrupt.c machdep.c
src/sys/arch/hpcmips/include [matt-nb5-mips64]: intr.h sysconf.h
src/sys/arch/hpcmips/tx [matt-nb5-mips64]: tx39.c
src/sys/arch/hpcmips/vr [matt-nb5-mips64]: vr.c
src/sys/arch/mipsco/include [matt-nb5-mips64]: intr.h sysconf.h
src/sys/arch/mipsco/mipsco [matt-nb5-mips64]: autoconf.c interrupt.c
machdep.c mips_3x30.c
Log Message:
Adapt to the new interrupt framework.
(XXX hpcmips still has calls to _spllower which are not supported.)
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.7.18.1 src/sys/arch/ews4800mips/ews4800mips/autoconf.c
cvs rdiff -u -r1.4.18.1 -r1.4.18.2 \
src/sys/arch/ews4800mips/ews4800mips/interrupt.c
cvs rdiff -u -r1.4 -r1.4.18.1 src/sys/arch/ews4800mips/ews4800mips/mainbus.c
cvs rdiff -u -r1.3.18.1 -r1.3.18.2 src/sys/arch/ews4800mips/ews4800mips/tr2.c \
src/sys/arch/ews4800mips/ews4800mips/tr2a.c
cvs rdiff -u -r1.10 -r1.10.18.1 \
src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c
cvs rdiff -u -r1.12 -r1.12.18.1 \
src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
cvs rdiff -u -r1.10 -r1.10.18.1 src/sys/arch/ews4800mips/include/intr.h
cvs rdiff -u -r1.4 -r1.4.18.1 src/sys/arch/ews4800mips/include/sbdvar.h
cvs rdiff -u -r1.21 -r1.21.28.1 src/sys/arch/hpcmips/hpcmips/autoconf.c
cvs rdiff -u -r1.2 -r1.2.96.1 src/sys/arch/hpcmips/hpcmips/hpcapm_machdep.c
cvs rdiff -u -r1.13 -r1.13.18.1 src/sys/arch/hpcmips/hpcmips/interrupt.c
cvs rdiff -u -r1.96.10.5 -r1.96.10.6 src/sys/arch/hpcmips/hpcmips/machdep.c
cvs rdiff -u -r1.22 -r1.22.28.1 src/sys/arch/hpcmips/include/intr.h
cvs rdiff -u -r1.13 -r1.13.62.1 src/sys/arch/hpcmips/include/sysconf.h
cvs rdiff -u -r1.39.18.1 -r1.39.18.2 src/sys/arch/hpcmips/tx/tx39.c
cvs rdiff -u -r1.51.22.1 -r1.51.22.2 src/sys/arch/hpcmips/vr/vr.c
cvs rdiff -u -r1.16.36.1 -r1.16.36.2 src/sys/arch/mipsco/include/intr.h
cvs rdiff -u -r1.4 -r1.4.62.1 src/sys/arch/mipsco/include/sysconf.h
cvs rdiff -u -r1.18 -r1.18.36.1 src/sys/arch/mipsco/mipsco/autoconf.c
cvs rdiff -u -r1.6.18.1 -r1.6.18.2 src/sys/arch/mipsco/mipsco/interrupt.c
cvs rdiff -u -r1.58.10.3 -r1.58.10.4 src/sys/arch/mipsco/mipsco/machdep.c
cvs rdiff -u -r1.10.18.1 -r1.10.18.2 src/sys/arch/mipsco/mipsco/mips_3x30.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/ews4800mips/ews4800mips/autoconf.c
diff -u src/sys/arch/ews4800mips/ews4800mips/autoconf.c:1.7 src/sys/arch/ews4800mips/ews4800mips/autoconf.c:1.7.18.1
--- src/sys/arch/ews4800mips/ews4800mips/autoconf.c:1.7 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/autoconf.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.7 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: autoconf.c,v 1.7.18.1 2010/12/29 08:16:21 matt Exp $ */
/*-
* Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.7 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.7.18.1 2010/12/29 08:16:21 matt Exp $");
#include "opt_sbd.h"
@@ -35,6 +35,7 @@
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
+#include <sys/intr.h>
#include <machine/sbdvar.h>
#include <machine/disklabel.h>
@@ -50,7 +51,7 @@
splhigh();
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
- _splnone();
+ spl0();
}
void
Index: src/sys/arch/ews4800mips/ews4800mips/interrupt.c
diff -u src/sys/arch/ews4800mips/ews4800mips/interrupt.c:1.4.18.1 src/sys/arch/ews4800mips/ews4800mips/interrupt.c:1.4.18.2
--- src/sys/arch/ews4800mips/ews4800mips/interrupt.c:1.4.18.1 Fri Feb 5 07:39:53 2010
+++ src/sys/arch/ews4800mips/ews4800mips/interrupt.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.4.18.1 2010/02/05 07:39:53 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.4.18.2 2010/12/29 08:16:21 matt Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.4.18.1 2010/02/05 07:39:53 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.4.18.2 2010/12/29 08:16:21 matt Exp $");
#include <sys/param.h>
#include <sys/intr.h>
@@ -39,8 +39,7 @@
#include <machine/sbdvar.h>
-const uint32_t *ipl_sr_bits;
-static void (*platform_intr)(uint32_t, uint32_t, uint32_t, uint32_t);
+static void (*platform_intr)(int, vaddr_t, uint32_t);
void
intr_init(void)
@@ -65,21 +64,9 @@
}
void
-cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- struct cpu_info *ci;
-
- ci = curcpu();
uvmexp.intrs++;
- ci->ci_idepth++;
- (*platform_intr)(status, cause, pc, ipending);
- ci->ci_idepth--;
-
-#ifdef __HAVE_FAST_SOFTINTS
- ipending &= MIPS_SOFT_INT_MASK;
- if (ipending == 0)
- return;
- softint_process(ipending);
-#endif
+ (*platform_intr)(ppl, pc, status);
}
Index: src/sys/arch/ews4800mips/ews4800mips/mainbus.c
diff -u src/sys/arch/ews4800mips/ews4800mips/mainbus.c:1.4 src/sys/arch/ews4800mips/ews4800mips/mainbus.c:1.4.18.1
--- src/sys/arch/ews4800mips/ews4800mips/mainbus.c:1.4 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/mainbus.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.4 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: mainbus.c,v 1.4.18.1 2010/12/29 08:16:21 matt Exp $ */
/*-
* Copyright (c) 2001, 2004, 2005 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.4 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.4.18.1 2010/12/29 08:16:21 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -59,7 +59,7 @@
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
- const char **p;
+ const char * const *p;
mainbus_found = 1;
aprint_normal("\n");
Index: src/sys/arch/ews4800mips/ews4800mips/tr2.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2.c:1.3.18.1 src/sys/arch/ews4800mips/ews4800mips/tr2.c:1.3.18.2
--- src/sys/arch/ews4800mips/ews4800mips/tr2.c:1.3.18.1 Wed Jan 20 09:04:33 2010
+++ src/sys/arch/ews4800mips/ews4800mips/tr2.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2.c,v 1.3.18.1 2010/01/20 09:04:33 matt Exp $ */
+/* $NetBSD: tr2.c,v 1.3.18.2 2010/12/29 08:16:21 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,8 +30,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2.c,v 1.3.18.1 2010/01/20 09:04:33 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2.c,v 1.3.18.2 2010/12/29 08:16:21 matt Exp $");
+#define __INTR_PRIVATE
#include "fb_sbdio.h"
#include "kbms_sbdio.h"
#include "zsc_sbdio.h"
@@ -59,7 +60,7 @@
SBD_DECL(tr2);
/* EWS4800/350 mainbus device list */
-static const char *tr2_mainbusdevs[] =
+static const char * const tr2_mainbusdevs[] =
{
"sbdio",
#ifdef notyet
@@ -102,7 +103,7 @@
platform.mainbusdevs = tr2_mainbusdevs;
platform.sbdiodevs = tr2_sbdiodevs;
- ipl_sr_bits = tr2_sr_bits;
+ ipl_sr_map = tr2_ipl_sr_map;
kseg2iobufsize = 0x02000000; /* 32MB for VME and framebuffer */
Index: src/sys/arch/ews4800mips/ews4800mips/tr2a.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2a.c:1.3.18.1 src/sys/arch/ews4800mips/ews4800mips/tr2a.c:1.3.18.2
--- src/sys/arch/ews4800mips/ews4800mips/tr2a.c:1.3.18.1 Wed Jan 20 09:04:33 2010
+++ src/sys/arch/ews4800mips/ews4800mips/tr2a.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2a.c,v 1.3.18.1 2010/01/20 09:04:33 matt Exp $ */
+/* $NetBSD: tr2a.c,v 1.3.18.2 2010/12/29 08:16:21 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,8 +30,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.3.18.1 2010/01/20 09:04:33 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.3.18.2 2010/12/29 08:16:21 matt Exp $");
+#define __INTR_PRIVATE
#include "fb_sbdio.h"
#include "kbms_sbdio.h"
#include "zsc_sbdio.h"
@@ -59,7 +60,7 @@
SBD_DECL(tr2a);
/* EWS4800/360 bus list */
-static const char *tr2a_mainbusdevs[] = {
+static const char * const tr2a_mainbusdevs[] = {
"sbdio",
#ifdef notyet
"apbus",
@@ -151,7 +152,7 @@
if (have_fb_sbdio)
platform.sbdiodevs = tr2a_sbdiodevs;
- ipl_sr_bits = tr2a_sr_bits;
+ ipl_sr_map = tr2a_ipl_sr_map;
kseg2iobufsize = 0x02000000; /* 32MB for APbus and framebuffer */
Index: src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c:1.10 src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c:1.10.18.1
--- src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c:1.10 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2_intr.c,v 1.10 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: tr2_intr.c,v 1.10.18.1 2010/12/29 08:16:21 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,12 +30,15 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.10 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.10.18.1 2010/12/29 08:16:21 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
-#include <sys/device.h>
+#include <sys/evcnt.h>
+#include <sys/cpu.h>
+#include <sys/lwp.h>
#include <sys/intr.h>
#include <machine/locore.h> /* mips3_cp0* */
@@ -47,23 +50,24 @@
SBD_DECL(tr2);
-const uint32_t tr2_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_4,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+const struct ipl_sr_map tr2_ipl_sr_map = {
+ {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_4,
+ [IPL_SCHED] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_4
+ | MIPS_INT_MASK_5,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
/* !!! TEST !!! VME INTERRUPT IS NOT MASKED */
+ },
};
#define NIRQ 8
@@ -139,121 +143,116 @@
}
void
-tr2_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+tr2_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct tr2_intr_handler *ih;
struct clockframe cf;
- uint32_t r, handled;
+ uint32_t r, ipending;
+ int ipl;
- handled = 0;
+ while (ppl < (ipl = splintr(&ipending))) {
+ if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 0);
- if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
- cf.pc = pc;
- cf.sr = status;
+ *PICNIC_INT5_STATUS_REG = 0;
+ r = *PICNIC_INT5_STATUS_REG;
- *PICNIC_INT5_STATUS_REG = 0;
- r = *PICNIC_INT5_STATUS_REG;
-
- hardclock(&cf);
- timer_tr2_ev.ev_count++;
- handled |= MIPS_INT_MASK_5;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ hardclock(&cf);
+ timer_tr2_ev.ev_count++;
+ }
- if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
- r = *PICNIC_INT4_STATUS_REG;
+ if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
+ r = *PICNIC_INT4_STATUS_REG;
- if (r & PICNIC_INT_KBMS) {
- ih = &tr2_intr_handler[0];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if (r & PICNIC_INT_KBMS) {
+ ih = &tr2_intr_handler[0];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_KBMS;
}
- r &= ~PICNIC_INT_KBMS;
- }
- if (r & PICNIC_INT_SERIAL) {
+ if (r & PICNIC_INT_SERIAL) {
#if 0
- printf("SIO interrupt\n");
+ printf("SIO interrupt\n");
#endif
- ih = &tr2_intr_handler[2];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ ih = &tr2_intr_handler[2];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_SERIAL;
}
- r &= ~PICNIC_INT_SERIAL;
}
- handled |= MIPS_INT_MASK_4;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ if (ipending & MIPS_INT_MASK_3) { /* VME */
+ printf("VME interrupt\n");
- if (ipending & MIPS_INT_MASK_3) { /* VME */
- printf("VME interrupt\n");
-
- r = *(volatile uint32_t *)0xbfb00018; /* NABI? */
- if ((r & 0x10) != 0) {
- /* vme high interrupt */
- } else if ((r & 0x4) != 0) {
- /* vme lo interrupt */
- } else {
- /* error */
+ r = *(volatile uint32_t *)0xbfb00018; /* NABI? */
+ if ((r & 0x10) != 0) {
+ /* vme high interrupt */
+ } else if ((r & 0x4) != 0) {
+ /* vme lo interrupt */
+ } else {
+ /* error */
+ }
}
- }
- if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
- r = *PICNIC_INT2_STATUS_REG;
+ if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
+ r = *PICNIC_INT2_STATUS_REG;
- if (r & PICNIC_INT_ETHER) {
- ih = &tr2_intr_handler[6];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if (r & PICNIC_INT_ETHER) {
+ ih = &tr2_intr_handler[6];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_ETHER;
}
- r &= ~PICNIC_INT_ETHER;
- }
- if (r & PICNIC_INT_SCSI) {
- ih = &tr2_intr_handler[5];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if (r & PICNIC_INT_SCSI) {
+ ih = &tr2_intr_handler[5];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_SCSI;
}
- r &= ~PICNIC_INT_SCSI;
- }
- if ((r & PICNIC_INT_FDDLPT) &&
- ((cause & status) & MIPS_INT_MASK_5)) {
+ if ((r & PICNIC_INT_FDDLPT) &&
+ (ipending & MIPS_INT_MASK_5)) {
#ifdef DEBUG
- printf("FDD LPT interrupt\n");
+ printf("FDD LPT interrupt\n");
#endif
- ih = &tr2_intr_handler[7];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ ih = &tr2_intr_handler[7];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_FDDLPT;
}
- r &= ~PICNIC_INT_FDDLPT;
}
- handled |= MIPS_INT_MASK_2;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
-
- if (ipending & MIPS_INT_MASK_1)
- panic("unknown interrupt INT1\n");
+ if (ipending & MIPS_INT_MASK_1)
+ panic("unknown interrupt INT1\n");
- if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
- printf("printer, printer interrupt\n");
- r = *PICNIC_INT0_STATUS_REG;
- if (r & PICNIC_INT_FDDLPT) {
- printf("FDD, Printer interrupt.\n");
- } else {
- printf("unknown interrupt INT0\n");
+ if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
+#ifdef DEBUG
+ printf("printer, printer interrupt\n");
+#endif
+ r = *PICNIC_INT0_STATUS_REG;
+ if (r & PICNIC_INT_FDDLPT) {
+#ifdef DEBUG
+ printf("FDD, Printer interrupt.\n");
+#endif
+ } else {
+ printf("unknown interrupt INT0\n");
+ }
}
- handled |= MIPS_INT_MASK_0;
}
- cause &= ~handled;
- _splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
}
void
Index: src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c:1.12 src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c:1.12.18.1
--- src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c:1.12 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2a_intr.c,v 1.12 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: tr2a_intr.c,v 1.12.18.1 2010/12/29 08:16:21 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,12 +30,15 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.12 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.12.18.1 2010/12/29 08:16:21 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/evcnt.h>
+#include <sys/lwp.h>
+#include <sys/cpu.h>
#include <sys/intr.h>
#include <machine/locore.h> /* mips3_cp0* */
@@ -45,27 +48,16 @@
SBD_DECL(tr2a);
-const uint32_t tr2a_sr_bits[_IPL_N] = {
+const struct ipl_sr_map tr2a_ipl_sr_map = {
+ .sr_bits = {
[IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_INT_MASK & ~MIPS_INT_MASK_5,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
#define NIRQ 16
@@ -178,134 +170,124 @@
}
void
-tr2a_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+tr2a_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct tr2a_intr_handler *ih;
struct clockframe cf;
- uint32_t r, intc_cause, handled;
+ uint32_t r, intc_cause, ipending;
+ int ipl;
- handled = 0;
intc_cause = *INTC_STATUS_REG & *INTC_MASK_REG;
- if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
- cf.pc = pc;
- cf.sr = status;
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x7c;
- *INTC_STATUS_REG;
-
- hardclock(&cf);
- timer_tr2a_ev.ev_count++;
- handled |= MIPS_INT_MASK_5;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
-
+ while (ppl < (ipl = splintr(&ipending))) {
+ if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 0);
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x7c;
+ *INTC_STATUS_REG;
- if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
- /* KBD, MOUSE, SERIAL */
- r = *ASO_INT_STATUS_REG;
- if (r & 0x300010) {
- ih = &tr2a_intr_handler[4];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r & 0x40) {
- /* kbms */
- ih = &tr2a_intr_handler[9];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r & 0x20) {
- printf("INT4 (1)\n");
- } else if (r & 0x00800000) {
- printf("INT4 (2)\n");
- } else if (r & 0x00400000) {
- printf("INT4 (3)\n");
- } else if (r != 0) {
- printf("not for INT4 %x\n", r);
+ hardclock(&cf);
+ timer_tr2a_ev.ev_count++;
}
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x68;
- *INTC_STATUS_REG;
+ if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
+ /* KBD, MOUSE, SERIAL */
+ r = *ASO_INT_STATUS_REG;
+ if (r & 0x300010) {
+ ih = &tr2a_intr_handler[4];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x40) {
+ /* kbms */
+ ih = &tr2a_intr_handler[9];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x20) {
+ printf("INT4 (1)\n");
+ } else if (r & 0x00800000) {
+ printf("INT4 (2)\n");
+ } else if (r & 0x00400000) {
+ printf("INT4 (3)\n");
+ } else if (r != 0) {
+ printf("not for INT4 %x\n", r);
+ }
- handled |= MIPS_INT_MASK_4;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x68;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {
- /* APbus HI */
- printf("APbus HI\n");
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x54;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_3;
- }
+ if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {
+ /* APbus HI */
+ printf("APbus HI\n");
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x54;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
- /* SCSI, ETHER */
- r = *ASO_INT_STATUS_REG;
- if (r & 0x100) { /* SCSI-A */
- ih = &tr2a_intr_handler[6];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
+ /* SCSI, ETHER */
+ r = *ASO_INT_STATUS_REG;
+ if (r & 0x100) { /* SCSI-A */
+ ih = &tr2a_intr_handler[6];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x200) { /* SCSI-B */
+ ih = &tr2a_intr_handler[10];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x1) { /* LANCE */
+ ih = &tr2a_intr_handler[0];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r != 0) {
+ printf("not for INT2 %x %x\n", r,
+ *ASO_DMAINT_STATUS_REG);
}
- } else if (r & 0x200) { /* SCSI-B */
- ih = &tr2a_intr_handler[10];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r & 0x1) { /* LANCE */
- ih = &tr2a_intr_handler[0];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r != 0) {
- printf("not for INT2 %x %x\n", r,
- *ASO_DMAINT_STATUS_REG);
- }
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x40;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_2;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x40;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
- /* APbus LO */
- printf("APbus LO\n");
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x2c;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_1;
- }
+ if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
+ /* APbus LO */
+ printf("APbus LO\n");
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x2c;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_0) && (intc_cause & INTC_INT0)) {
- /* NMI etc. */
- r = *ASO_INT_STATUS_REG;
- printf("INT0 %08x\n", r);
- if (r & 0x8000) {
- printf("INT0(1) NMI\n");
- } else if (r & 0x8) {
- printf("INT0(2)\n");
- } else if (r & 0x4) {
- printf("INT0(3)\n");
- } else if (r != 0) {
- printf("not for INT0 %x\n", r);
+ if ((ipending & MIPS_INT_MASK_0) && (intc_cause & INTC_INT0)) {
+ /* NMI etc. */
+ r = *ASO_INT_STATUS_REG;
+ printf("INT0 %08x\n", r);
+ if (r & 0x8000) {
+ printf("INT0(1) NMI\n");
+ } else if (r & 0x8) {
+ printf("INT0(2)\n");
+ } else if (r & 0x4) {
+ printf("INT0(3)\n");
+ } else if (r != 0) {
+ printf("not for INT0 %x\n", r);
+ }
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x14;
+ *INTC_STATUS_REG;
}
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x14;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_0;
}
- cause &= ~handled;
- _splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
}
void
Index: src/sys/arch/ews4800mips/include/intr.h
diff -u src/sys/arch/ews4800mips/include/intr.h:1.10 src/sys/arch/ews4800mips/include/intr.h:1.10.18.1
--- src/sys/arch/ews4800mips/include/intr.h:1.10 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/include/intr.h Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.10 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: intr.h,v 1.10.18.1 2010/12/29 08:16:22 matt Exp $ */
/*-
* Copyright (c) 2000, 2001, 2004 The NetBSD Foundation, Inc.
@@ -32,59 +32,18 @@
#ifndef _EWS4800MIPS_INTR_H_
#define _EWS4800MIPS_INTR_H_
-#define IPL_NONE 0 /* disable only this interrupt */
-#define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */
-#define IPL_SOFTBIO 1 /* bio software interrupts (SI 0) */
-#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
-#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
-#define IPL_VM 3
-#define IPL_SCHED 4 /* disable clock interrupts */
-#define IPL_HIGH 4 /* disable all interrupts */
-
-#define _IPL_N 5
-
-#define _IPL_SI0_FIRST IPL_SOFTCLOCK
-#define _IPL_SI0_LAST IPL_SOFTBIO
-
-#define _IPL_SI1_FIRST IPL_SOFTNET
-#define _IPL_SI1_LAST IPL_SOFTSERIAL
-
-#define IST_UNUSABLE -1 /* interrupt cannot be used */
-#define IST_NONE 0 /* none (dummy) */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
-
-#include <mips/locore.h>
-
-extern const uint32_t *ipl_sr_bits;
-
-#define spl0() (void) _spllower(0)
-#define splx(s) (void) _splset(s)
-
-typedef int ipl_t;
-typedef struct {
- ipl_t _sr;
-} ipl_cookie_t;
-
-static inline ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
-}
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._sr);
-}
-
-#include <sys/spl.h>
+#include <mips/intr.h>
+#ifdef _KERNEL
void intr_init(void);
void intr_establish(int, int (*)(void *), void *);
void intr_disestablish(void *);
+#ifdef __INTR_PRIVATE
+extern const struct ipl_sr_map tr2_ipl_sr_map;
+extern const struct ipl_sr_map tr2a_ipl_sr_map;
+#endif
+
+#endif
+
#endif /* !_EWS4800MIPS_INTR_H_ */
Index: src/sys/arch/ews4800mips/include/sbdvar.h
diff -u src/sys/arch/ews4800mips/include/sbdvar.h:1.4 src/sys/arch/ews4800mips/include/sbdvar.h:1.4.18.1
--- src/sys/arch/ews4800mips/include/sbdvar.h:1.4 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/include/sbdvar.h Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: sbdvar.h,v 1.4 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: sbdvar.h,v 1.4.18.1 2010/12/29 08:16:22 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -47,7 +47,7 @@
int cpu_clock;
/* mainbus node table */
- const char **mainbusdevs;
+ const char * const *mainbusdevs;
/* System Board I/O device table */
const struct sbdiodevdesc *sbdiodevs;
@@ -68,7 +68,7 @@
void (*intr_init)(void);
void *(*intr_establish)(int, int (*)(void *), void *);
void (*intr_disestablish)(void *);
- void (*intr)(uint32_t, uint32_t, uint32_t, uint32_t);
+ void (*intr)(int, vaddr_t, uint32_t);
/* Interval timer helper routines */
void (*initclocks)(void);
@@ -88,14 +88,13 @@
void x ## _intr_init(void); \
void *x ## _intr_establish(int, int (*)(void *), void *); \
void x ## _intr_disestablish(void *); \
-void x ## _intr(uint32_t, uint32_t, uint32_t, uint32_t); \
+void x ## _intr(int, vaddr_t, uint32_t); \
void x ## _initclocks(void); \
void x ## _consinit(void); \
int x ## _ipl_bootdev(void); \
void x ## _reboot(void); \
void x ## _poweroff(void); \
void x ## _ether_addr(uint8_t *); \
-extern const uint32_t x ## _sr_bits[]
#define _SBD_OPS_SET(m, x) platform . x = m ## _ ## x
Index: src/sys/arch/hpcmips/hpcmips/autoconf.c
diff -u src/sys/arch/hpcmips/hpcmips/autoconf.c:1.21 src/sys/arch/hpcmips/hpcmips/autoconf.c:1.21.28.1
--- src/sys/arch/hpcmips/hpcmips/autoconf.c:1.21 Tue Feb 12 17:30:57 2008
+++ src/sys/arch/hpcmips/hpcmips/autoconf.c Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.21 2008/02/12 17:30:57 joerg Exp $ */
+/* $NetBSD: autoconf.c,v 1.21.28.1 2010/12/29 08:16:22 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -77,7 +77,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.21 2008/02/12 17:30:57 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.21.28.1 2010/12/29 08:16:22 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -114,7 +114,7 @@
panic("no mainbus found");
/* Configuration is finished, turn on interrupts. */
- _splnone(); /* enable all source forcing SOFT_INTs cleared */
+ spl0(); /* enable all source forcing SOFT_INTs cleared */
}
void
Index: src/sys/arch/hpcmips/hpcmips/hpcapm_machdep.c
diff -u src/sys/arch/hpcmips/hpcmips/hpcapm_machdep.c:1.2 src/sys/arch/hpcmips/hpcmips/hpcapm_machdep.c:1.2.96.1
--- src/sys/arch/hpcmips/hpcmips/hpcapm_machdep.c:1.2 Sun Dec 11 12:17:33 2005
+++ src/sys/arch/hpcmips/hpcmips/hpcapm_machdep.c Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: hpcapm_machdep.c,v 1.2 2005/12/11 12:17:33 christos Exp $ */
+/* $NetBSD: hpcapm_machdep.c,v 1.2.96.1 2010/12/29 08:16:22 matt Exp $ */
/*
* Copyright (c) 2000 Takemura Shin
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: hpcapm_machdep.c,v 1.2 2005/12/11 12:17:33 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: hpcapm_machdep.c,v 1.2.96.1 2010/12/29 08:16:22 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -91,35 +91,35 @@
machine_sleep()
{
#if NVRIP_COMMON > 0
- if (platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) {
- /*
- * disable all interrupts except PIU interrupt
- */
- vrip_intr_suspend();
- _spllower(~MIPS_INT_MASK_0);
-
- /*
- * SUSPEND instruction puts the CPU into power saveing
- * state until some interrupt occuer.
- * It sleeps until you push the power button.
- */
- __asm(".set noreorder");
- __asm(".word " ___STRING(VR_OPCODE_SUSPEND));
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm(".set reorder");
-
- splhigh();
- vrip_intr_resume();
- delay(1000); /* 1msec */
- }
+ if (platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) {
+ /*
+ * disable all interrupts except PIU interrupt
+ */
+ vrip_intr_suspend();
+ _spllower(~MIPS_INT_MASK_0);
+
+ /*
+ * SUSPEND instruction puts the CPU into power saveing
+ * state until some interrupt occuer.
+ * It sleeps until you push the power button.
+ */
+ __asm(".set noreorder");
+ __asm(".word " ___STRING(VR_OPCODE_SUSPEND));
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm(".set reorder");
+
+ splhigh();
+ vrip_intr_resume();
+ delay(1000); /* 1msec */
+ }
#endif /* NVRIP_COMMON > 0 */
#ifdef TX39XX
- if (platid_match(&platid, &platid_mask_CPU_MIPS_TX)) {
- tx39power_suspend_cpu();
- }
+ if (platid_match(&platid, &platid_mask_CPU_MIPS_TX)) {
+ tx39power_suspend_cpu();
+ }
#endif
}
Index: src/sys/arch/hpcmips/hpcmips/interrupt.c
diff -u src/sys/arch/hpcmips/hpcmips/interrupt.c:1.13 src/sys/arch/hpcmips/hpcmips/interrupt.c:1.13.18.1
--- src/sys/arch/hpcmips/hpcmips/interrupt.c:1.13 Mon Apr 28 20:23:21 2008
+++ src/sys/arch/hpcmips/hpcmips/interrupt.c Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.13 2008/04/28 20:23:21 martin Exp $ */
+/* $NetBSD: interrupt.c,v 1.13.18.1 2010/12/29 08:16:22 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,28 +30,26 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.13 2008/04/28 20:23:21 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.13.18.1 2010/12/29 08:16:22 matt Exp $");
#include "opt_vr41xx.h"
#include "opt_tx39xx.h"
+#define __INTR_PRIVATE
+
#include <sys/param.h>
#include <sys/malloc.h>
+#include <sys/intr.h>
#include <uvm/uvm_extern.h>
#include <machine/sysconf.h>
-extern const u_int32_t __ipl_sr_bits_vr[];
-extern const u_int32_t __ipl_sr_bits_tx[];
-
-const u_int32_t *ipl_sr_bits;
-
void
-intr_init()
+intr_init(void)
{
- ipl_sr_bits = CPUISMIPS3 ? __ipl_sr_bits_vr : __ipl_sr_bits_tx;
+ ipl_sr_map = CPUISMIPS3 ? __ipl_sr_map_vr : __ipl_sr_map_tx;
}
#if defined(VR41XX) && defined(TX39XX)
@@ -64,9 +62,9 @@
*
*/
void
-cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- (*platform.cpu_intr)(status, cause, pc, ipending);
+ (*platform.cpu_intr)(ppl, pc, status);
}
#endif /* VR41XX && TX39XX */
Index: src/sys/arch/hpcmips/hpcmips/machdep.c
diff -u src/sys/arch/hpcmips/hpcmips/machdep.c:1.96.10.5 src/sys/arch/hpcmips/hpcmips/machdep.c:1.96.10.6
--- src/sys/arch/hpcmips/hpcmips/machdep.c:1.96.10.5 Sun Mar 21 17:38:34 2010
+++ src/sys/arch/hpcmips/hpcmips/machdep.c Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.96.10.5 2010/03/21 17:38:34 cliff Exp $ */
+/* $NetBSD: machdep.c,v 1.96.10.6 2010/12/29 08:16:22 matt Exp $ */
/*-
* Copyright (c) 1999 Shin Takemura, All rights reserved.
@@ -108,7 +108,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.96.10.5 2010/03/21 17:38:34 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.96.10.6 2010/12/29 08:16:22 matt Exp $");
#include "opt_vr41xx.h"
#include "opt_tx39xx.h"
@@ -142,6 +142,7 @@
#include <ufs/mfs/mfs_extern.h> /* mfs_initminiroot() */
#include <dev/cons.h> /* cntab access (cpu_reboot) */
+#include <machine/locore.h>
#include <machine/psl.h>
#include <machine/sysconf.h>
#include <machine/platid.h>
Index: src/sys/arch/hpcmips/include/intr.h
diff -u src/sys/arch/hpcmips/include/intr.h:1.22 src/sys/arch/hpcmips/include/intr.h:1.22.28.1
--- src/sys/arch/hpcmips/include/intr.h:1.22 Fri Jan 4 22:03:25 2008
+++ src/sys/arch/hpcmips/include/intr.h Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.22 2008/01/04 22:03:25 ad Exp $ */
+/* $NetBSD: intr.h,v 1.22.28.1 2010/12/29 08:16:22 matt Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -33,62 +33,17 @@
#ifndef _HPCMIPS_INTR_H_
#define _HPCMIPS_INTR_H_
-#define IPL_NONE 0 /* disable only this interrupt */
-#define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */
-#define IPL_SOFTBIO 1 /* bio software interrupts (SI 0) */
-#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
-#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
-#define IPL_VM 3
-#define IPL_SCHED 4
-#define IPL_HIGH 4 /* disable all interrupts */
-
-#define _IPL_N 5
-
-#define _IPL_SI0_FIRST IPL_SOFTCLOCK
-#define _IPL_SI0_LAST IPL_SOFTBIO
-
-#define _IPL_SI1_FIRST IPL_SOFTNET
-#define _IPL_SI1_LAST IPL_SOFTSERIAL
-
-/* Interrupt sharing types. */
-#define IST_UNUSABLE -1 /* interrupt cannot be used */
-#define IST_NONE 0 /* none */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
+#include <mips/intr.h>
#ifdef _KERNEL
#ifndef _LOCORE
-#include <mips/cpuregs.h>
-#include <mips/locore.h>
-
-extern const u_int32_t *ipl_sr_bits;
void intr_init(void);
-#define spl0() (void) _spllower(0)
-#define splx(s) (void) _splset(s)
-
-typedef int ipl_t;
-typedef struct {
- ipl_t _sr;
-} ipl_cookie_t;
-
-static inline ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
-}
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._sr);
-}
-
-#include <sys/spl.h>
+#ifdef __INTR_PRIVATE
+extern const struct ipl_sr_map __ipl_sr_map_vr;
+extern const struct ipl_sr_map __ipl_sr_map_tx;
+#endif
#endif /* !_LOCORE */
#endif /* _KERNEL */
Index: src/sys/arch/hpcmips/include/sysconf.h
diff -u src/sys/arch/hpcmips/include/sysconf.h:1.13 src/sys/arch/hpcmips/include/sysconf.h:1.13.62.1
--- src/sys/arch/hpcmips/include/sysconf.h:1.13 Sun Mar 4 05:59:53 2007
+++ src/sys/arch/hpcmips/include/sysconf.h Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: sysconf.h,v 1.13 2007/03/04 05:59:53 christos Exp $ */
+/* $NetBSD: sysconf.h,v 1.13.62.1 2010/12/29 08:16:22 matt Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -62,7 +62,7 @@
* reboot - reboot or powerdown
* clock -
*/
- void (*cpu_intr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+ void (*cpu_intr)(int, vaddr_t, u_int32_t);
void (*cpu_idle)(void);
void (*cons_init)(void);
void (*fb_init)(void **);
Index: src/sys/arch/hpcmips/tx/tx39.c
diff -u src/sys/arch/hpcmips/tx/tx39.c:1.39.18.1 src/sys/arch/hpcmips/tx/tx39.c:1.39.18.2
--- src/sys/arch/hpcmips/tx/tx39.c:1.39.18.1 Mon Feb 1 04:18:31 2010
+++ src/sys/arch/hpcmips/tx/tx39.c Wed Dec 29 08:16:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: tx39.c,v 1.39.18.1 2010/02/01 04:18:31 matt Exp $ */
+/* $NetBSD: tx39.c,v 1.39.18.2 2010/12/29 08:16:22 matt Exp $ */
/*-
* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tx39.c,v 1.39.18.1 2010/02/01 04:18:31 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tx39.c,v 1.39.18.2 2010/12/29 08:16:22 matt Exp $");
#include "opt_vr41xx.h"
#include "opt_tx39xx.h"
@@ -39,6 +39,7 @@
#include <sys/param.h>
#include <sys/systm.h>
+#include <sys/intr.h>
#include <uvm/uvm_extern.h>
@@ -83,7 +84,7 @@
#define TX_INTR cpu_intr /* locore_mips3 directly call this */
#endif
-extern void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+extern void TX_INTR(int, vaddr_t, uint32_t);
void tx39clock_cpuspeed(int *, int *);
@@ -179,9 +180,9 @@
tx_find_dram(paddr_t start, paddr_t end)
{
char *page, *startaddr, *endaddr;
- u_int32_t magic0, magic1;
-#define MAGIC0 (*(volatile u_int32_t *)(page + 0))
-#define MAGIC1 (*(volatile u_int32_t *)(page + 4))
+ uint32_t magic0, magic1;
+#define MAGIC0 (*(volatile uint32_t *)(page + 0))
+#define MAGIC1 (*(volatile uint32_t *)(page + 4))
startaddr = (char *)MIPS_PHYS_TO_KSEG1(start);
endaddr = (char *)MIPS_PHYS_TO_KSEG1(end);
@@ -236,7 +237,7 @@
tx_reboot(int howto, char *bootstr)
{
- goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
+ goto *(uint32_t *)MIPS_RESET_EXC_VEC;
}
void
Index: src/sys/arch/hpcmips/vr/vr.c
diff -u src/sys/arch/hpcmips/vr/vr.c:1.51.22.1 src/sys/arch/hpcmips/vr/vr.c:1.51.22.2
--- src/sys/arch/hpcmips/vr/vr.c:1.51.22.1 Fri Feb 5 07:39:53 2010
+++ src/sys/arch/hpcmips/vr/vr.c Wed Dec 29 08:16:23 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: vr.c,v 1.51.22.1 2010/02/05 07:39:53 matt Exp $ */
+/* $NetBSD: vr.c,v 1.51.22.2 2010/12/29 08:16:23 matt Exp $ */
/*-
* Copyright (c) 1999-2002
@@ -35,12 +35,14 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vr.c,v 1.51.22.1 2010/02/05 07:39:53 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vr.c,v 1.51.22.2 2010/12/29 08:16:23 matt Exp $");
#include "opt_vr41xx.h"
#include "opt_tx39xx.h"
#include "opt_kgdb.h"
+#define __INTR_PRIVATE
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/reboot.h>
@@ -126,22 +128,19 @@
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
-const u_int32_t __ipl_sr_bits_vr[_IPL_N] = {
- 0, /* IPL_NONE */
-
- MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0, /* IPL_VM */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1, /* IPL_SCHED */
+const struct ipl_sr_map __ipl_sr_map_vr = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0,
+ [IPL_SCHED] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_1,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_VM] = MIPS_INT_MASK,
+ },
};
#if defined(VR41XX) && defined(TX39XX)
@@ -151,7 +150,7 @@
#endif
void vr_init(void);
-void VR_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+void VR_INTR(int, vaddr_t, uint32_t);
extern void vr_idle(void);
STATIC void vr_cons_init(void);
STATIC void vr_fb_init(void **);
@@ -162,8 +161,8 @@
/*
* CPU interrupt dispatch table (HwInt[0:3])
*/
-STATIC int vr_null_handler(void *, u_int32_t, u_int32_t);
-STATIC int (*vr_intr_handler[4])(void *, u_int32_t, u_int32_t) =
+STATIC int vr_null_handler(void *, uint32_t, uint32_t);
+STATIC int (*vr_intr_handler[4])(void *, uint32_t, uint32_t) =
{
vr_null_handler,
vr_null_handler,
@@ -428,6 +427,7 @@
printf("%s(%d): can't init kgdb's serial port",
__FILE__, __LINE__);
}
+ }
#else /* KGDB */
if (com_info->attach != NULL && (bootinfo->bi_cnuse&BI_CNUSE_SERIAL)) {
/* Serial console */
@@ -530,45 +530,32 @@
* Handle interrupts.
*/
void
-VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
+VR_INTR(int ppl, vaddr_t pc, uint32_t status)
{
- struct cpu_info *ci;
+ uint32_t ipending;
+ int ipl;
- ci = curcpu();
- ci->ci_idepth++;
uvmexp.intrs++;
- /* Deal with unneded compare interrupts occasionally so that we can
- * keep spllowersoftclock. */
- if (ipending & MIPS_INT_MASK_5) {
- mips3_cp0_compare_write(0);
- }
+ while (ppl < (ipl = splintr(&ipending))) {
+ /* Deal with unneded compare interrupts occasionally so that
+ * we can keep spllowersoftclock. */
+ if (ipending & MIPS_INT_MASK_5) {
+ mips3_cp0_compare_write(0);
+ }
- if (ipending & MIPS_INT_MASK_1) {
- _splset(MIPS_SR_INT_IE); /* for spllowersoftclock */
- /* Remove the lower priority pending bits from status so that
- * spllowersoftclock will not happen if other interrupts are
- * pending. */
- (*vr_intr_handler[1])(vr_intr_arg[1], pc, status & ~(ipending
- & (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)));
- }
+ if (ipending & MIPS_INT_MASK_1) {
+ (*vr_intr_handler[1])(vr_intr_arg[1], pc, ipending);
+ }
- if (ipending & MIPS_INT_MASK_0) {
- _splset(MIPS_INT_MASK_1|MIPS_SR_INT_IE);
- (*vr_intr_handler[0])(vr_intr_arg[0], pc, status);
+ if (ipending & MIPS_INT_MASK_0) {
+ (*vr_intr_handler[0])(vr_intr_arg[0], pc, status);
+ }
}
- ci->ci_idepth--;
-
-#ifdef __HAVE_FAST_SOFTINTS
- ipending &= MIPS_SOFT_INT_MASK;
- if (ipending == 0)
- return;
- softint_process(ipending);
-#endif
}
void *
-vr_intr_establish(int line, int (*ih_fun)(void *, u_int32_t, u_int32_t),
+vr_intr_establish(int line, int (*ih_fun)(void *, uint32_t, uint32_t),
void *ih_arg)
{
@@ -590,7 +577,7 @@
}
int
-vr_null_handler(void *arg, u_int32_t pc, u_int32_t status)
+vr_null_handler(void *arg, uint32_t pc, uint32_t status)
{
printf("vr_null_handler\n");
Index: src/sys/arch/mipsco/include/intr.h
diff -u src/sys/arch/mipsco/include/intr.h:1.16.36.1 src/sys/arch/mipsco/include/intr.h:1.16.36.2
--- src/sys/arch/mipsco/include/intr.h:1.16.36.1 Fri Feb 5 07:39:54 2010
+++ src/sys/arch/mipsco/include/intr.h Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.16.36.1 2010/02/05 07:39:54 matt Exp $ */
+/* $NetBSD: intr.h,v 1.16.36.2 2010/12/29 08:16:21 matt Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -33,29 +33,12 @@
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
-#define IPL_NONE 0 /* disable only this interrupt */
-#define IPL_SOFTCLOCK 1 /* generic software interrupts */
-#define IPL_SOFTBIO 1 /* clock software interrupts */
-#define IPL_SOFTNET 2 /* network software interrupts */
-#define IPL_SOFTSERIAL 2 /* serial software interrupts */
-#define IPL_VM 3
-#define IPL_SCHED 4
-#define IPL_HIGH 4 /* disable all interrupts */
-
-#define IPL_N 5
-
-/* Interrupt sharing types. */
-#define IST_NONE 0 /* none */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
+#include <mips/intr.h>
#ifdef _KERNEL
-#ifndef _LOCORE
-#include <sys/types.h>
-#include <sys/device.h>
-#include <sys/queue.h>
-#include <mips/locore.h>
+#ifdef __INTR_PRIVATE
+#include <sys/evcnt.h>
+#include <mips/cpuregs.h>
/*
* nesting interrupt masks.
@@ -69,49 +52,27 @@
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
-#define spl0() (void)_spllower(0)
-#define splx(s) (void)_splset(s)
-#define splvm() _splraise(MIPS_INT_MASK_SPL2)
-#define splsched() _splraise(MIPS_INT_MASK_SPL2)
-#define splhigh() _splraise(MIPS_INT_MASK_SPL2)
-
-#define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0)
-#define splsoftbio() _splraise(MIPS_INT_MASK_SPL_SOFT0)
-#define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1)
-#define splsoftserial() _splraise(MIPS_INT_MASK_SPL_SOFT1)
-
-typedef int ipl_t;
-typedef struct {
- int _sr;
-} ipl_cookie_t;
-
-ipl_cookie_t makeiplcookie(ipl_t ipl);
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._sr);
-}
-
struct mipsco_intrhand {
- LIST_ENTRY(mipsco_intrhand)
- ih_q;
- int (*ih_fun) __P((void *));
+ LIST_ENTRY(mipsco_intrhand) ih_q;
+ int (*ih_fun)(void *);
void *ih_arg;
struct mipsco_intr *ih_intrhead;
int ih_pending;
};
struct mipsco_intr {
- LIST_HEAD(,mipsco_intrhand)
- intr_q;
+ LIST_HEAD(,mipsco_intrhand) intr_q;
struct evcnt ih_evcnt;
unsigned long intr_siq;
};
-
+extern const struct ipl_sr_map mipsco_ipl_sr_map;
extern struct mipsco_intrhand intrtab[];
+#define CALL_INTR(lev) ((*intrtab[lev].ih_fun)(intrtab[lev].ih_arg))
+
+#define MAX_INTR_COOKIES 16
+
+#endif /* __INTR_PRIVATE */
#define SYS_INTR_LEVEL0 0
#define SYS_INTR_LEVEL1 1
@@ -126,10 +87,5 @@
#define SYS_INTR_FDC 10
#define SYS_INTR_ATBUS 11
-#define MAX_INTR_COOKIES 16
-
-#define CALL_INTR(lev) ((*intrtab[lev].ih_fun)(intrtab[lev].ih_arg))
-
-#endif /* !_LOCORE */
#endif /* _KERNEL */
#endif /* _MACHINE_INTR_H_ */
Index: src/sys/arch/mipsco/include/sysconf.h
diff -u src/sys/arch/mipsco/include/sysconf.h:1.4 src/sys/arch/mipsco/include/sysconf.h:1.4.62.1
--- src/sys/arch/mipsco/include/sysconf.h:1.4 Sun Mar 4 06:00:13 2007
+++ src/sys/arch/mipsco/include/sysconf.h Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: sysconf.h,v 1.4 2007/03/04 06:00:13 christos Exp $ */
+/* $NetBSD: sysconf.h,v 1.4.62.1 2010/12/29 08:16:21 matt Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -53,11 +53,11 @@
* write_todr - Write TOD registers
* clkinit - Initialize clocks
*/
- void (*cons_init) __P((void));
- void (*iointr) __P((unsigned, unsigned, unsigned, unsigned));
- int (*memsize) __P((void *));
- void (*intr_establish) __P((int, int (*)__P((void *)), void *));
- void (*clkinit) __P((void));
+ void (*cons_init)(void);
+ void (*iointr)(uint32_t, vaddr_t, uint32_t);
+ int (*memsize)(void *);
+ void (*intr_establish)(int, int (*)(void *), void *);
+ void (*clkinit)(void);
};
extern struct platform platform;
Index: src/sys/arch/mipsco/mipsco/autoconf.c
diff -u src/sys/arch/mipsco/mipsco/autoconf.c:1.18 src/sys/arch/mipsco/mipsco/autoconf.c:1.18.36.1
--- src/sys/arch/mipsco/mipsco/autoconf.c:1.18 Mon Dec 3 15:33:57 2007
+++ src/sys/arch/mipsco/mipsco/autoconf.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.18 2007/12/03 15:33:57 ad Exp $ */
+/* $NetBSD: autoconf.c,v 1.18.36.1 2010/12/29 08:16:21 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -84,8 +84,9 @@
* and the drivers are initialized.
*/
+#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.18 2007/12/03 15:33:57 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.18.36.1 2010/12/29 08:16:21 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
Index: src/sys/arch/mipsco/mipsco/interrupt.c
diff -u src/sys/arch/mipsco/mipsco/interrupt.c:1.6.18.1 src/sys/arch/mipsco/mipsco/interrupt.c:1.6.18.2
--- src/sys/arch/mipsco/mipsco/interrupt.c:1.6.18.1 Fri Feb 5 07:39:54 2010
+++ src/sys/arch/mipsco/mipsco/interrupt.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.6.18.1 2010/02/05 07:39:54 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.6.18.2 2010/12/29 08:16:21 matt Exp $ */
/*
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -29,55 +29,40 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.6.18.1 2010/02/05 07:39:54 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.6.18.2 2010/12/29 08:16:21 matt Exp $");
#include <sys/param.h>
#include <sys/malloc.h>
#include <sys/intr.h>
-#include <sys/cpu.h>
#include <uvm/uvm_extern.h>
#include <machine/sysconf.h>
void
-cpu_intr(status, cause, pc, ipending)
- u_int32_t status;
- u_int32_t cause;
- u_int32_t pc;
- u_int32_t ipending;
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- struct cpu_info *ci;
+ uint32_t ipending;
+ int ipl;
- ci = curcpu();
uvmexp.intrs++;
- /* device interrupts */
- ci->ci_idepth++;
- (*platform.iointr)(status, cause, pc, ipending);
- ci->ci_idepth--;
-
-#ifdef __HAVE_FAST_SOFTINTS
- /* software simulated interrupt */
- ipending &= MIPS_SOFT_INT_MASK;
- if (ipending == 0)
- return;
- softint_process(ipending);
-#endif
+ while (ppl < (ipl = splintr(&ipending))) {
+ /* device interrupts */
+ (*platform.iointr)(status, pc, ipending);
+ }
+
}
-static const int ipl_sr_bits[] = {
+const struct ipl_sr_map mipsco_ipl_sr_map = {
+ .sr_bits = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] = MIPS_INT_MASK_SPL_SOFT0,
[IPL_SOFTNET] = MIPS_INT_MASK_SPL_SOFT1,
[IPL_VM] = MIPS_INT_MASK_SPL2,
[IPL_SCHED] = MIPS_INT_MASK_SPL2,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
-
-ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
-}
Index: src/sys/arch/mipsco/mipsco/machdep.c
diff -u src/sys/arch/mipsco/mipsco/machdep.c:1.58.10.3 src/sys/arch/mipsco/mipsco/machdep.c:1.58.10.4
--- src/sys/arch/mipsco/mipsco/machdep.c:1.58.10.3 Sun Mar 21 17:38:34 2010
+++ src/sys/arch/mipsco/mipsco/machdep.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.58.10.3 2010/03/21 17:38:34 cliff Exp $ */
+/* $NetBSD: machdep.c,v 1.58.10.4 2010/12/29 08:16:21 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -76,7 +76,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.58.10.3 2010/03/21 17:38:34 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.58.10.4 2010/12/29 08:16:21 matt Exp $");
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
@@ -150,26 +150,26 @@
phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
int mem_cluster_cnt;
-void to_monitor __P((int)) __attribute__((__noreturn__));
-void prom_halt __P((int)) __attribute__((__noreturn__));
+void to_monitor(int) __dead;
+void prom_halt(int) __dead;
#ifdef KGDB
-void zs_kgdb_init __P((void));
-void kgdb_connect __P((int));
+void zs_kgdb_init(void);
+void kgdb_connect(int);
#endif
/*
* Local functions.
*/
-int initcpu __P((void));
-void configure __P((void));
+int initcpu(void);
+void configure(void);
-void mach_init __P((int, char *[], char*[], u_int, char *));
-int memsize_scan __P((void *));
+void mach_init(int, char *[], char*[], u_int, char *);
+int memsize_scan(void *);
#ifdef DEBUG
/* stacktrace code violates prototypes to get callee's registers */
-extern void stacktrace __P((void)); /*XXX*/
+extern void stacktrace(void); /*XXX*/
#endif
/*
@@ -182,15 +182,15 @@
extern struct user *proc0paddr;
/* locore callback-vector setup */
-extern void mips_vector_init __P((const struct splsw *));
-extern void prom_init __P((void));
-extern void pizazz_init __P((void));
+extern void mips_vector_init(const struct splsw *);
+extern void prom_init(void);
+extern void pizazz_init(void);
/* platform-specific initialization vector */
-static void unimpl_cons_init __P((void));
-static void unimpl_iointr __P((unsigned, unsigned, unsigned, unsigned));
-static int unimpl_memsize __P((void *));
-static void unimpl_intr_establish __P((int, int (*)__P((void *)), void *));
+static void unimpl_cons_init(void);
+static void unimpl_iointr(uint32_t, vaddr_t, uint32_t);
+static int unimpl_memsize(void *);
+static void unimpl_intr_establish(int, int (*)(void *), void *);
struct platform platform = {
.iobus = "iobus not set",
@@ -205,11 +205,11 @@
extern struct consdev consdev_prom;
extern struct consdev consdev_zs;
-static void null_cnprobe __P((struct consdev *));
-static void prom_cninit __P((struct consdev *));
-static int prom_cngetc __P((dev_t));
-static void prom_cnputc __P((dev_t, int));
-static void null_cnpollc __P((dev_t, int));
+static void null_cnprobe(struct consdev *);
+static void prom_cninit(struct consdev *);
+static int prom_cngetc(dev_t);
+static void prom_cnputc(dev_t, int);
+static void null_cnpollc(dev_t, int);
struct consdev consdev_prom = {
null_cnprobe,
@@ -246,7 +246,6 @@
struct btinfo_symtab *bi_syms;
#endif
-
/* Check for valid bootinfo passed from bootstrap */
if (bim == BOOTINFO_MAGIC) {
struct btinfo_magic *bi_magic;
@@ -264,6 +263,13 @@
kernend = (void *)mips_round_page(end);
memset(edata, 0, end - edata);
+ /*
+ * Copy exception-dispatch code down to exception vector.
+ * Initialize locore-function vector.
+ * Clear out the I and D caches.
+ */
+ mips_vector_init(NULL);
+
#if NKSYMS || defined(DDB) || defined(LKM)
bi_syms = lookup_bootinfo(BTINFO_SYMTAB);
@@ -298,13 +304,6 @@
mem_clusters[0].size = ctob(physmem);
mem_cluster_cnt = 1;
- /*
- * Copy exception-dispatch code down to exception vector.
- * Initialize locore-function vector.
- * Clear out the I and D caches.
- */
- mips_vector_init();
-
/* Look at argv[0] and compute bootdev */
makebootdev(argv[0]);
@@ -531,50 +530,41 @@
}
int
-initcpu()
+initcpu(void)
{
spl0(); /* safe to turn interrupts on now */
return 0;
}
static void
-unimpl_cons_init()
+unimpl_cons_init(void)
{
panic("sysconf.init didn't set cons_init");
}
static void
-unimpl_iointr(mask, pc, statusreg, causereg)
- u_int mask;
- u_int pc;
- u_int statusreg;
- u_int causereg;
+unimpl_iointr(uint32_t status, vaddr_t pc, uint32_t ipending)
{
panic("sysconf.init didn't set intr");
}
static int
-unimpl_memsize(first)
-void *first;
+unimpl_memsize(void *first)
{
panic("sysconf.init didn't set memsize");
}
void
-unimpl_intr_establish(level, func, arg)
- int level;
- int (*func) __P((void *));
- void *arg;
+unimpl_intr_establish(int level, int (*func)(void *), void *arg)
{
panic("sysconf.init didn't init intr_establish");
}
void
-delay(n)
- int n;
+delay(int n)
{
DELAY(n);
}
Index: src/sys/arch/mipsco/mipsco/mips_3x30.c
diff -u src/sys/arch/mipsco/mipsco/mips_3x30.c:1.10.18.1 src/sys/arch/mipsco/mipsco/mips_3x30.c:1.10.18.2
--- src/sys/arch/mipsco/mipsco/mips_3x30.c:1.10.18.1 Mon Feb 1 04:18:31 2010
+++ src/sys/arch/mipsco/mipsco/mips_3x30.c Wed Dec 29 08:16:21 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_3x30.c,v 1.10.18.1 2010/02/01 04:18:31 matt Exp $ */
+/* $NetBSD: mips_3x30.c,v 1.10.18.2 2010/12/29 08:16:21 matt Exp $ */
/*
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -29,19 +29,20 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_3x30.c,v 1.10.18.1 2010/02/01 04:18:31 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_3x30.c,v 1.10.18.2 2010/12/29 08:16:21 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/kernel.h>
+#include <sys/cpu.h>
+#include <sys/intr.h>
#include <machine/trap.h>
#include <machine/psl.h>
-#include <machine/cpu.h>
-#include <machine/intr.h>
#include <machine/mainboard.h>
#include <machine/sysconf.h>
@@ -49,9 +50,9 @@
/* Local functions */
void pizazz_init (void);
-void pizazz_intr (u_int, u_int, u_int, u_int);
+void pizazz_intr (uint32_t, vaddr_t, uint32_t);
int pizazz_level0_intr (void *);
-void pizazz_level5_intr (int, int, int);
+void pizazz_level5_intr (uint32_t, vaddr_t);
void pizazz_intr_establish (int, int (*)(void *), void *);
#define INT_MASK_FPU MIPS_INT_MASK_3
@@ -64,6 +65,8 @@
platform.iointr = pizazz_intr;
platform.intr_establish = pizazz_intr_establish;
+ ipl_sr_map = mipsco_ipl_sr_map;
+
pizazz_intr_establish(SYS_INTR_LEVEL0, pizazz_level0_intr, NULL);
strcpy(cpu_model, "Mips 3230 Magnum (Pizazz)");
@@ -78,11 +81,7 @@
} while (0)
void
-pizazz_intr(status, cause, pc, ipending)
- u_int status; /* status register at time of the exception */
- u_int cause; /* cause register at time of exception */
- u_int pc; /* program counter where to continue */
- u_int ipending;
+pizazz_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
{
/* handle clock interrupts ASAP */
if (ipending & MIPS_INT_MASK_2) { /* Timer Interrupt */
@@ -91,35 +90,25 @@
cf.pc = pc;
cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 0);
rambo_clkintr(&cf);
-
- /* keep clock interrupts enabled when we return */
- cause &= ~MIPS_INT_MASK_2;
}
- /* If clock interrupts were enabled, re-enable them ASAP. */
- _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_2));
-
if (ipending & MIPS_INT_MASK_5) /* level 5 interrupt */
- pizazz_level5_intr(pc, cause, status);
+ pizazz_level5_intr(status, pc);
HANDLE_INTR(SYS_INTR_FDC, MIPS_INT_MASK_4);
HANDLE_INTR(SYS_INTR_SCSI, MIPS_INT_MASK_1);
HANDLE_INTR(SYS_INTR_LEVEL0, MIPS_INT_MASK_0);
- /* XXX: Keep FDC interrupt masked off */
- cause &= ~(MIPS_INT_MASK_0 | MIPS_INT_MASK_1 | MIPS_INT_MASK_5);
-
- _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
-
#if !defined(NOFPU)
/* FPU nofiticaition */
if (ipending & INT_MASK_FPU) {
if (!USERMODE(status))
- panic("kernel used FPU: PC %x, CR %x, SR %x",
- pc, cause, status);
- MachFPInterrupt(status, cause, pc, curlwp->l_md.md_utf);
+ panic("kernel used FPU: PC %x, SR %x",
+ pc, status);
+ MachFPInterrupt(status, 0, pc, curlwp->l_md.md_utf);
}
#endif
}
@@ -155,16 +144,13 @@
* Motherboard Parity Error
*/
void
-pizazz_level5_intr(pc, cause, status)
- int pc;
- int cause;
- int status;
+pizazz_level5_intr(uint32_t status, vaddr_t pc)
{
u_int32_t ereg;
ereg = *(u_int32_t *)RAMBO_ERREG;
- printf("interrupt: pc=%p cr=%x sr=%x\n", (void *)pc, cause, status);
+ printf("interrupt: pc=%p sr=%x\n", (void *)pc, status);
printf("parity error: %p mask: 0x%x\n", (void *)ereg, ereg & 0xf);
panic("memory fault");
}
