Module Name: src
Committed By: matt
Date: Fri Jan 7 01:59:40 UTC 2011
Modified Files:
src/sys/arch/powerpc/include [matt-nb5-pq3]: cpu.h db_machdep.h psl.h
Log Message:
Add booke support.
To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.65.22.1 src/sys/arch/powerpc/include/cpu.h
cvs rdiff -u -r1.19 -r1.19.88.1 src/sys/arch/powerpc/include/db_machdep.h
cvs rdiff -u -r1.14 -r1.14.86.1 src/sys/arch/powerpc/include/psl.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/include/cpu.h
diff -u src/sys/arch/powerpc/include/cpu.h:1.65 src/sys/arch/powerpc/include/cpu.h:1.65.22.1
--- src/sys/arch/powerpc/include/cpu.h:1.65 Wed Apr 30 23:21:29 2008
+++ src/sys/arch/powerpc/include/cpu.h Fri Jan 7 01:59:40 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.65 2008/04/30 23:21:29 macallan Exp $ */
+/* $NetBSD: cpu.h,v 1.65.22.1 2011/01/07 01:59:40 matt Exp $ */
/*
* Copyright (C) 1999 Wolfgang Solfrank.
@@ -59,6 +59,7 @@
struct cpu_info {
struct cpu_data ci_data; /* MI per-cpu data */
struct device *ci_dev; /* device of corresponding cpu */
+ struct cpu_softc *ci_softc; /* private cpu info */
struct lwp *ci_curlwp; /* current owner of the processor */
struct pcb *ci_curpcb;
@@ -69,16 +70,21 @@
volatile int ci_astpending;
int ci_want_resched;
+ volatile uint64_t ci_lastintr;
volatile u_long ci_lasttb;
volatile int ci_tickspending;
volatile int ci_cpl;
volatile int ci_iactive;
volatile int ci_idepth;
+#ifndef PPC_BOOKE
volatile int ci_ipending;
- int ci_intrdepth;
+#endif
int ci_mtx_oldspl;
int ci_mtx_count;
+#ifndef PPC_BOOKE
char *ci_intstk;
+#endif
+#ifndef PPC_BOOKE
#define CPUSAVE_LEN 8
register_t ci_tempsave[CPUSAVE_LEN];
register_t ci_ddbsave[CPUSAVE_LEN];
@@ -87,21 +93,37 @@
#define CPUSAVE_R29 1 /* where r29 gets saved */
#define CPUSAVE_R30 2 /* where r30 gets saved */
#define CPUSAVE_R31 3 /* where r31 gets saved */
+#if defined(PPC_IBM4XX)
+#define CPUSAVE_DEAR 4 /* where SPR_DAR gets saved */
+#define CPUSAVE_ESR 5 /* where SPR_DSISR gets saved */
+ register_t ci_tlbmisssave[CPUSAVE_LEN];
+#else
#define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */
#define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */
-#define CPUSAVE_SRR0 6 /* where SRR0 gets saved */
-#define CPUSAVE_SRR1 7 /* where SRR1 gets saved */
#define DISISAVE_LEN 4
register_t ci_disisave[DISISAVE_LEN];
+#endif
+#define CPUSAVE_SRR0 6 /* where SRR0 gets saved */
+#define CPUSAVE_SRR1 7 /* where SRR1 gets saved */
+#else
+#define CPUSAVE_LEN 128
+ register_t ci_savelifo[CPUSAVE_LEN];
+ struct pmap_segtab *ci_pmap_segtabs[2];
+#define ci_pmap_kern_segtab ci_pmap_segtabs[0]
+#define ci_pmap_user_segtab ci_pmap_segtabs[1]
+ struct pmap_tlb_info *ci_tlb_info;
+#endif
struct cache_info ci_ci;
void *ci_sysmon_cookie;
void (*ci_idlespin)(void);
uint32_t ci_khz;
struct evcnt ci_ev_clock; /* clock intrs */
struct evcnt ci_ev_statclock; /* stat clock */
+#ifndef PPC_BOOKE
struct evcnt ci_ev_softclock; /* softclock intrs */
struct evcnt ci_ev_softnet; /* softnet intrs */
struct evcnt ci_ev_softserial; /* softserial intrs */
+#endif
struct evcnt ci_ev_traps; /* calls to trap() */
struct evcnt ci_ev_kdsi; /* kernel DSI traps */
struct evcnt ci_ev_udsi; /* user DSI traps */
@@ -119,6 +141,9 @@
struct evcnt ci_ev_vecsw; /* Altivec context switches */
struct evcnt ci_ev_umchk; /* user MCHK events */
struct evcnt ci_ev_ipi; /* IPIs received */
+ struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */
+ struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */
+ struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */
};
#ifdef MULTIPROCESSOR
@@ -190,7 +215,8 @@
static __inline void
mtmsr(register_t msr)
{
-
+ //KASSERT(msr & PSL_CE);
+ //KASSERT(msr & PSL_DE);
__asm volatile ("mtmsr %0" : : "r"(msr));
}
@@ -202,6 +228,8 @@
__asm volatile (
#ifdef PPC_IBM403
" mftblo %0 \n"
+#elif defined(PPC_BOOKE)
+" mfspr %0,268 \n"
#else
" mftbl %0 \n"
#endif
@@ -225,6 +253,10 @@
"1: mftbhi %0 \n"
" mftblo %0+1 \n"
" mftbhi %1 \n"
+#elif defined(PPC_BOOKE)
+"1: mfspr %0,269 \n"
+" mfspr %0+1,268 \n"
+" mfspr %1,269 \n"
#else
"1: mftbu %0 \n"
" mftb %0+1 \n"
@@ -297,16 +329,15 @@
})
#endif /* PPC_IBM4XX || PPC_IBM403 */
-#define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
-#define CLKF_PC(frame) ((frame)->srr0)
-#define CLKF_INTR(frame) ((frame)->depth > 0)
+#define CLKF_USERMODE(frame) (((frame)->cf_srr1 & PSL_PR) != 0)
+#define CLKF_PC(frame) ((frame)->cf_srr0)
+#define CLKF_INTR(frame) ((frame)->cf_idepth >= 0)
+#define LWP_PC(l) (trapframe(l)->tf_srr0)
-#define LWP_PC(l) (trapframe(l)->srr0)
#define cpu_swapin(p)
#define cpu_swapout(p)
#define cpu_proc_fork(p1, p2)
-#define cpu_idle() (curcpu()->ci_idlespin())
#define cpu_lwp_free2(l)
extern int powersave;
@@ -314,15 +345,28 @@
extern int cpu_printfataltraps;
extern char cpu_model[];
+void cpu_uarea_remap(struct lwp *);
struct cpu_info *cpu_attach_common(struct device *, int);
void cpu_setup(struct device *, struct cpu_info *);
void cpu_identify(char *, size_t);
void delay (unsigned int);
void cpu_probe_cache(void);
+#ifndef PPC_BOOKE
void dcache_flush_page(vaddr_t);
void icache_flush_page(vaddr_t);
void dcache_flush(vaddr_t, vsize_t);
void icache_flush(vaddr_t, vsize_t);
+#else
+void dcache_wb_page(vaddr_t);
+void dcache_wbinv_page(vaddr_t);
+void dcache_inv_page(vaddr_t);
+void dcache_zero_page(vaddr_t);
+void icache_inv_page(vaddr_t);
+void dcache_wb(vaddr_t, vsize_t);
+void dcache_wbinv(vaddr_t, vsize_t);
+void dcache_inv(vaddr_t, vsize_t);
+void icache_inv(vaddr_t, vsize_t);
+#endif
void *mapiodev(paddr_t, psize_t);
void unmapiodev(vaddr_t, vsize_t);
@@ -344,7 +388,7 @@
#define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1)
#define cpu_signotify(l) (curcpu()->ci_astpending = 1) /* XXXSMP */
-#if !defined(PPC_IBM4XX)
+#if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE)
void oea_init(void (*)(void));
void oea_startup(const char *);
void oea_dumpsys(void);
Index: src/sys/arch/powerpc/include/db_machdep.h
diff -u src/sys/arch/powerpc/include/db_machdep.h:1.19 src/sys/arch/powerpc/include/db_machdep.h:1.19.88.1
--- src/sys/arch/powerpc/include/db_machdep.h:1.19 Sun May 14 21:56:32 2006
+++ src/sys/arch/powerpc/include/db_machdep.h Fri Jan 7 01:59:39 2011
@@ -1,5 +1,5 @@
/* $OpenBSD: db_machdep.h,v 1.2 1997/03/21 00:48:48 niklas Exp $ */
-/* $NetBSD: db_machdep.h,v 1.19 2006/05/14 21:56:32 elad Exp $ */
+/* $NetBSD: db_machdep.h,v 1.19.88.1 2011/01/07 01:59:39 matt Exp $ */
/*
* Mach Operating System
@@ -118,7 +118,7 @@
((ins)&M_BCTR) == I_BCTR )
#define inst_load(ins) 0
#define inst_store(ins) 0
-#ifdef PPC_IBM4XX
+#if defined(PPC_IBM4XX) || defined(PPC_BOOKE)
#define next_instr_address(v, b) ((db_addr_t) ((b) ? (v) : ((v) + 4)))
extern db_addr_t branch_taken(int, db_addr_t, db_regs_t *);
#endif
@@ -150,7 +150,8 @@
void kdb_kintr __P((void *));
int kdb_trap __P((int, void *));
-#ifdef PPC_IBM4XX
+#if defined (PPC_OEA) || defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) \
+ || defined(PPC_IBM4XX) || defined(USERACC) || defined(PPC_BOOKE)
/*
* We have machine-dependent commands.
*/
Index: src/sys/arch/powerpc/include/psl.h
diff -u src/sys/arch/powerpc/include/psl.h:1.14 src/sys/arch/powerpc/include/psl.h:1.14.86.1
--- src/sys/arch/powerpc/include/psl.h:1.14 Sat Aug 5 21:26:49 2006
+++ src/sys/arch/powerpc/include/psl.h Fri Jan 7 01:59:39 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: psl.h,v 1.14 2006/08/05 21:26:49 sanjayl Exp $ */
+/* $NetBSD: psl.h,v 1.14.86.1 2011/01/07 01:59:39 matt Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -42,24 +42,34 @@
*
* [*] Little-endian mode on the 601 is implemented in the HID0 register.
*/
-#define PSL_VEC 0x02000000 /* AltiVec vector unit available */
-#define PSL_POW 0x00040000 /* power management */
-#define PSL_TGPR 0x00020000 /* temp. gpr remapping (mpc603e) */
-#define PSL_ILE 0x00010000 /* interrupt endian mode (1 == le) */
-#define PSL_EE 0x00008000 /* external interrupt enable */
-#define PSL_PR 0x00004000 /* privilege mode (1 == user) */
-#define PSL_FP 0x00002000 /* floating point enable */
-#define PSL_ME 0x00001000 /* machine check enable */
-#define PSL_FE0 0x00000800 /* floating point interrupt mode 0 */
-#define PSL_SE 0x00000400 /* single-step trace enable */
-#define PSL_BE 0x00000200 /* branch trace enable */
-#define PSL_FE1 0x00000100 /* floating point interrupt mode 1 */
-#define PSL_IP 0x00000040 /* interrupt prefix */
-#define PSL_IR 0x00000020 /* instruction address relocation */
-#define PSL_DR 0x00000010 /* data address relocation */
-#define PSL_PM 0x00000008 /* Performance monitor marked mode */
-#define PSL_RI 0x00000002 /* recoverable interrupt */
-#define PSL_LE 0x00000001 /* endian mode (1 == le) */
+#define PSL_VEC 0x02000000 /* ..6. AltiVec vector unit available */
+#define PSL_UCLE 0x00400000 /* B... user-mode cache lock enable */
+#define PSL_SPV 0x00200000 /* B... (e500) SPE enable */
+#define PSL_POW 0x00040000 /* ..6. power management */
+#define PSL_WE PSL_POW /* B4.. wait state enable */
+#define PSL_TGPR 0x00020000 /* ..6. temp. gpr remapping (mpc603e) */
+#define PSL_CE PSL_TGPR /* B4.. critical interrupt enable */
+#define PSL_ILE 0x00010000 /* ..6. interrupt endian mode (1 == le) */
+#define PSL_EE 0x00008000 /* B468 external interrupt enable */
+#define PSL_PR 0x00004000 /* B468 privilege mode (1 == user) */
+#define PSL_FP 0x00002000 /* B.6. floating point enable */
+#define PSL_ME 0x00001000 /* B468 machine check enable */
+#define PSL_FE0 0x00000800 /* B.6. floating point mode 0 */
+#define PSL_SE 0x00000400 /* ..6. single-step trace enable */
+#define PSL_DWE PSL_SE /* .4.. debug wait enable */
+#define PSL_UBLE PSL_SE /* B... user BTB lock enable */
+#define PSL_BE 0x00000200 /* ..6. branch trace enable */
+#define PSL_DE PSL_BE /* B4.. debug interrupt enable */
+#define PSL_FE1 0x00000100 /* B.6. floating point mode 1 */
+#define PSL_IP 0x00000040 /* ..6. interrupt prefix */
+#define PSL_IR 0x00000020 /* .468 instruction address relocation */
+#define PSL_IS PSL_IR /* B... instruction address space */
+#define PSL_DR 0x00000010 /* .468 data address relocation */
+#define PSL_DS PSL_DR /* B... data address space */
+#define PSL_PM 0x00000008 /* ..6. Performance monitor */
+#define PSL_PMM PSL_PM /* B... Performance monitor */
+#define PSL_RI 0x00000002 /* ..6. recoverable interrupt */
+#define PSL_LE 0x00000001 /* ..6. endian mode (1 == le) */
#define PSL_601_MASK ~(PSL_VEC|PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE)
@@ -97,12 +107,18 @@
#define PSL_USERSET cpu_psluserset
#define PSL_USERMOD cpu_pslusermod
+#elif defined(PPC_BOOKE)
+#define PSL_USERSET (PSL_EE | PSL_PR | PSL_ME | PSL_CE | PSL_DE | PSL_IS | PSL_DS)
+#define PSL_USERMOD (0)
+#define PSL_USERSRR1 ((PSL_USERSET|PSL_USERMOD) & (PSL_CE|0xFFFF))
#else /* PPC_IBM4XX */
#define PSL_USERSET (PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR)
#define PSL_USERMOD (0)
#endif /* PPC_OEA */
+#ifndef PSL_USERSRR1
#define PSL_USERSRR1 ((PSL_USERSET|PSL_USERMOD) & 0xFFFF)
+#endif
#define PSL_USEROK_P(psl) (((psl) & ~PSL_USERMOD) == PSL_USERSET)
#endif /* !_LOCORE */
