Module Name: src Committed By: tsutsui Date: Tue Jan 25 12:21:05 UTC 2011
Modified Files: src/sys/arch/sgimips/hpc: haltwo.c hpc.c hpcdma.c hpcdma.h hpcreg.h hpcvar.h if_sq.c pi1ppc.c pi1ppcvar.h sqvar.h Log Message: u_intNN_t -> uintNN_t To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/sgimips/hpc/haltwo.c cvs rdiff -u -r1.63 -r1.64 src/sys/arch/sgimips/hpc/hpc.c cvs rdiff -u -r1.18 -r1.19 src/sys/arch/sgimips/hpc/hpcdma.c cvs rdiff -u -r1.9 -r1.10 src/sys/arch/sgimips/hpc/hpcdma.h \ src/sys/arch/sgimips/hpc/sqvar.h cvs rdiff -u -r1.19 -r1.20 src/sys/arch/sgimips/hpc/hpcreg.h cvs rdiff -u -r1.11 -r1.12 src/sys/arch/sgimips/hpc/hpcvar.h cvs rdiff -u -r1.37 -r1.38 src/sys/arch/sgimips/hpc/if_sq.c cvs rdiff -u -r1.7 -r1.8 src/sys/arch/sgimips/hpc/pi1ppc.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/sgimips/hpc/pi1ppcvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/sgimips/hpc/haltwo.c diff -u src/sys/arch/sgimips/hpc/haltwo.c:1.17 src/sys/arch/sgimips/hpc/haltwo.c:1.18 --- src/sys/arch/sgimips/hpc/haltwo.c:1.17 Thu Sep 24 14:09:18 2009 +++ src/sys/arch/sgimips/hpc/haltwo.c Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: haltwo.c,v 1.17 2009/09/24 14:09:18 tsutsui Exp $ */ +/* $NetBSD: haltwo.c,v 1.18 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2003 Ilpo Ruotsalainen @@ -30,7 +30,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: haltwo.c,v 1.17 2009/09/24 14:09:18 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: haltwo.c,v 1.18 2011/01/25 12:21:04 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -269,12 +269,12 @@ return 0; if ( platform.badaddr((void *)(vaddr_t)(haa->ha_sh + haa->ha_devoff), - sizeof(u_int32_t)) ) + sizeof(uint32_t)) ) return 0; if ( platform.badaddr( (void *)(vaddr_t)(haa->ha_sh + haa->ha_devoff + HAL2_REG_CTL_REV), - sizeof(u_int32_t)) ) + sizeof(uint32_t)) ) return 0; rev = *(uint32_t *)MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_devoff + Index: src/sys/arch/sgimips/hpc/hpc.c diff -u src/sys/arch/sgimips/hpc/hpc.c:1.63 src/sys/arch/sgimips/hpc/hpc.c:1.64 --- src/sys/arch/sgimips/hpc/hpc.c:1.63 Mon Dec 14 00:46:13 2009 +++ src/sys/arch/sgimips/hpc/hpc.c Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: hpc.c,v 1.63 2009/12/14 00:46:13 matt Exp $ */ +/* $NetBSD: hpc.c,v 1.64 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -35,7 +35,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.63 2009/12/14 00:46:13 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.64 2011/01/25 12:21:04 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -382,7 +382,7 @@ mach_type == MACH_SGI_IP22) { /* Make sure it's actually there and readable */ if (!platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), - sizeof(u_int32_t))) + sizeof(uint32_t))) return 1; } @@ -590,7 +590,7 @@ return (0); if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { - u_int32_t reg; + uint32_t reg; if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + HPC1_BIGENDIAN), 4)) { @@ -665,10 +665,10 @@ static int hpc_power_intr(void *arg) { - u_int32_t pwr_reg; + uint32_t pwr_reg; - pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); - *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; + pwr_reg = *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); + *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); @@ -692,7 +692,7 @@ value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + HPC1_AUX_REGS); value ^= HPC1_AUX_CONSLED; - *(volatile u_int8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + + *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + HPC1_AUX_REGS) = value; splx(s); Index: src/sys/arch/sgimips/hpc/hpcdma.c diff -u src/sys/arch/sgimips/hpc/hpcdma.c:1.18 src/sys/arch/sgimips/hpc/hpcdma.c:1.19 --- src/sys/arch/sgimips/hpc/hpcdma.c:1.18 Tue Jan 25 12:11:27 2011 +++ src/sys/arch/sgimips/hpc/hpcdma.c Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: hpcdma.c,v 1.18 2011/01/25 12:11:27 tsutsui Exp $ */ +/* $NetBSD: hpcdma.c,v 1.19 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2001 Wayne Knowles @@ -44,7 +44,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: hpcdma.c,v 1.18 2011/01/25 12:11:27 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: hpcdma.c,v 1.19 2011/01/25 12:21:04 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -196,7 +196,7 @@ void hpcdma_flush(struct hpc_dma_softc *sc) { - u_int32_t mode; + uint32_t mode; mode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl); bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl, Index: src/sys/arch/sgimips/hpc/hpcdma.h diff -u src/sys/arch/sgimips/hpc/hpcdma.h:1.9 src/sys/arch/sgimips/hpc/hpcdma.h:1.10 --- src/sys/arch/sgimips/hpc/hpcdma.h:1.9 Tue Jan 25 12:11:27 2011 +++ src/sys/arch/sgimips/hpc/hpcdma.h Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: hpcdma.h,v 1.9 2011/01/25 12:11:27 tsutsui Exp $ */ +/* $NetBSD: hpcdma.h,v 1.10 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2001 Wayne Knowles @@ -46,11 +46,11 @@ bus_space_handle_t sc_bsh; bus_dma_tag_t sc_dmat; - u_int32_t sc_flags; + uint32_t sc_flags; #define HPCDMA_READ 0x20 /* direction of transfer */ #define HPCDMA_LOADED 0x40 /* bus_dmamap loaded */ #define HPCDMA_ACTIVE 0x80 /* DMA engine is busy */ - u_int32_t sc_dmacmd; + uint32_t sc_dmacmd; int sc_ndesc; bus_dmamap_t sc_dmamap; struct hpc_dma_desc *sc_desc_kva; /* Virtual address */ @@ -62,7 +62,7 @@ void hpcdma_init(struct hpc_attach_args *, struct hpc_dma_softc *, int); void hpcdma_sglist_create(struct hpc_dma_softc *, bus_dmamap_t); -void hpcdma_cntl(struct hpc_dma_softc *, u_int32_t); +void hpcdma_cntl(struct hpc_dma_softc *, uint32_t); void hpcdma_reset(struct hpc_dma_softc *); void hpcdma_flush(struct hpc_dma_softc *); Index: src/sys/arch/sgimips/hpc/sqvar.h diff -u src/sys/arch/sgimips/hpc/sqvar.h:1.9 src/sys/arch/sgimips/hpc/sqvar.h:1.10 --- src/sys/arch/sgimips/hpc/sqvar.h:1.9 Sun Dec 11 12:18:53 2005 +++ src/sys/arch/sgimips/hpc/sqvar.h Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: sqvar.h,v 1.9 2005/12/11 12:18:53 christos Exp $ */ +/* $NetBSD: sqvar.h,v 1.10 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2001 Rafal K. Boni @@ -152,7 +152,7 @@ bus_dmamap_t sc_txmap[SQ_NTXDESC]; struct mbuf* sc_txmbuf[SQ_NTXDESC]; - u_int8_t sc_rxcmd; /* prototype rxcmd */ + uint8_t sc_rxcmd; /* prototype rxcmd */ struct evcnt sq_intrcnt; /* count interrupts */ Index: src/sys/arch/sgimips/hpc/hpcreg.h diff -u src/sys/arch/sgimips/hpc/hpcreg.h:1.19 src/sys/arch/sgimips/hpc/hpcreg.h:1.20 --- src/sys/arch/sgimips/hpc/hpcreg.h:1.19 Mon Feb 19 20:14:30 2007 +++ src/sys/arch/sgimips/hpc/hpcreg.h Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: hpcreg.h,v 1.19 2007/02/19 20:14:30 rumble Exp $ */ +/* $NetBSD: hpcreg.h,v 1.20 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2001 Rafal K. Boni @@ -43,10 +43,10 @@ * HPC3 descriptor layout. */ struct hpc_dma_desc { - u_int32_t hdd_bufptr; /* Physical address of buffer */ - u_int32_t hdd_ctl; /* Control flags and byte count */ - u_int32_t hdd_descptr; /* Physical address of next descr. */ - u_int32_t hdd_pad; /* Pad out to quadword alignment */ + uint32_t hdd_bufptr; /* Physical address of buffer */ + uint32_t hdd_ctl; /* Control flags and byte count */ + uint32_t hdd_descptr; /* Physical address of next descr. */ + uint32_t hdd_pad; /* Pad out to quadword alignment */ }; /* Index: src/sys/arch/sgimips/hpc/hpcvar.h diff -u src/sys/arch/sgimips/hpc/hpcvar.h:1.11 src/sys/arch/sgimips/hpc/hpcvar.h:1.12 --- src/sys/arch/sgimips/hpc/hpcvar.h:1.11 Fri Dec 22 23:36:42 2006 +++ src/sys/arch/sgimips/hpc/hpcvar.h Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: hpcvar.h,v 1.11 2006/12/22 23:36:42 rumble Exp $ */ +/* $NetBSD: hpcvar.h,v 1.12 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2001 Rafal K. Boni @@ -39,63 +39,63 @@ struct hpc_values { int revision; - u_int32_t scsi0_regs; - u_int32_t scsi0_regs_size; - u_int32_t scsi0_cbp; - u_int32_t scsi0_ndbp; - u_int32_t scsi0_bc; - u_int32_t scsi0_ctl; - u_int32_t scsi0_gio; - u_int32_t scsi0_dev; - u_int32_t scsi0_dmacfg; - u_int32_t scsi0_piocfg; - u_int32_t scsi1_regs; - u_int32_t scsi1_regs_size; - u_int32_t scsi1_cbp; - u_int32_t scsi1_ndbp; - u_int32_t scsi1_bc; - u_int32_t scsi1_ctl; - u_int32_t scsi1_gio; - u_int32_t scsi1_dev; - u_int32_t scsi1_dmacfg; - u_int32_t scsi1_piocfg; - u_int32_t enet_regs; - u_int32_t enet_regs_size; - u_int32_t enet_intdelay; - u_int32_t enet_intdelayval; - u_int32_t enetr_cbp; - u_int32_t enetr_ndbp; - u_int32_t enetr_bc; - u_int32_t enetr_ctl; - u_int32_t enetr_ctl_active; - u_int32_t enetr_reset; - u_int32_t enetr_dmacfg; - u_int32_t enetr_piocfg; - u_int32_t enetx_cbp; - u_int32_t enetx_ndbp; - u_int32_t enetx_bc; - u_int32_t enetx_ctl; - u_int32_t enetx_ctl_active; - u_int32_t enetx_dev; - u_int32_t enetr_fifo; - u_int32_t enetr_fifo_size; - u_int32_t enetx_fifo; - u_int32_t enetx_fifo_size; - u_int32_t scsi0_devregs_size; - u_int32_t scsi1_devregs_size; - u_int32_t enet_devregs; - u_int32_t enet_devregs_size; - u_int32_t pbus_fifo; - u_int32_t pbus_fifo_size; - u_int32_t pbus_bbram; - u_int32_t scsi_max_xfer; - u_int32_t scsi_dma_segs; - u_int32_t scsi_dma_segs_size; - u_int32_t scsi_dma_datain_cmd; - u_int32_t scsi_dma_dataout_cmd; - u_int32_t scsi_dmactl_flush; - u_int32_t scsi_dmactl_active; - u_int32_t scsi_dmactl_reset; + uint32_t scsi0_regs; + uint32_t scsi0_regs_size; + uint32_t scsi0_cbp; + uint32_t scsi0_ndbp; + uint32_t scsi0_bc; + uint32_t scsi0_ctl; + uint32_t scsi0_gio; + uint32_t scsi0_dev; + uint32_t scsi0_dmacfg; + uint32_t scsi0_piocfg; + uint32_t scsi1_regs; + uint32_t scsi1_regs_size; + uint32_t scsi1_cbp; + uint32_t scsi1_ndbp; + uint32_t scsi1_bc; + uint32_t scsi1_ctl; + uint32_t scsi1_gio; + uint32_t scsi1_dev; + uint32_t scsi1_dmacfg; + uint32_t scsi1_piocfg; + uint32_t enet_regs; + uint32_t enet_regs_size; + uint32_t enet_intdelay; + uint32_t enet_intdelayval; + uint32_t enetr_cbp; + uint32_t enetr_ndbp; + uint32_t enetr_bc; + uint32_t enetr_ctl; + uint32_t enetr_ctl_active; + uint32_t enetr_reset; + uint32_t enetr_dmacfg; + uint32_t enetr_piocfg; + uint32_t enetx_cbp; + uint32_t enetx_ndbp; + uint32_t enetx_bc; + uint32_t enetx_ctl; + uint32_t enetx_ctl_active; + uint32_t enetx_dev; + uint32_t enetr_fifo; + uint32_t enetr_fifo_size; + uint32_t enetx_fifo; + uint32_t enetx_fifo_size; + uint32_t scsi0_devregs_size; + uint32_t scsi1_devregs_size; + uint32_t enet_devregs; + uint32_t enet_devregs_size; + uint32_t pbus_fifo; + uint32_t pbus_fifo_size; + uint32_t pbus_bbram; + uint32_t scsi_max_xfer; + uint32_t scsi_dma_segs; + uint32_t scsi_dma_segs_size; + uint32_t scsi_dma_datain_cmd; + uint32_t scsi_dma_dataout_cmd; + uint32_t scsi_dmactl_flush; + uint32_t scsi_dmactl_active; + uint32_t scsi_dmactl_reset; }; struct hpc_attach_args { Index: src/sys/arch/sgimips/hpc/if_sq.c diff -u src/sys/arch/sgimips/hpc/if_sq.c:1.37 src/sys/arch/sgimips/hpc/if_sq.c:1.38 --- src/sys/arch/sgimips/hpc/if_sq.c:1.37 Mon Jan 10 13:29:29 2011 +++ src/sys/arch/sgimips/hpc/if_sq.c Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: if_sq.c,v 1.37 2011/01/10 13:29:29 tsutsui Exp $ */ +/* $NetBSD: if_sq.c,v 1.38 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2001 Rafal K. Boni @@ -33,7 +33,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.37 2011/01/10 13:29:29 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.38 2011/01/25 12:21:04 tsutsui Exp $"); #include <sys/param.h> @@ -419,7 +419,7 @@ * chip is configured and assume that it's correct for both. */ if (sc->hpc_regs->revision == 3) { - u_int32_t dmareg, pioreg; + uint32_t dmareg, pioreg; pioreg = HPC3_ENETR_PIOCFG_P1(1) | HPC3_ENETR_PIOCFG_P2(6) | @@ -526,7 +526,7 @@ sq_start(struct ifnet *ifp) { struct sq_softc *sc = ifp->if_softc; - u_int32_t status; + uint32_t status; struct mbuf *m0, *m; bus_dmamap_t dmamap; int err, totlen, nexttx, firsttx, lasttx = -1, ofree, seg; @@ -842,7 +842,7 @@ void sq_watchdog(struct ifnet *ifp) { - u_int32_t status; + uint32_t status; struct sq_softc *sc = ifp->if_softc; status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl); @@ -894,7 +894,7 @@ struct sq_softc *sc = arg; struct ifnet *ifp = &sc->sc_ethercom.ec_if; int handled = 0; - u_int32_t stat; + uint32_t stat; stat = sq_hpc_read(sc, sc->hpc_regs->enetr_reset); @@ -936,9 +936,9 @@ int count = 0; struct mbuf* m; int i, framelen; - u_int8_t pktstat; - u_int32_t status; - u_int32_t ctl_reg; + uint8_t pktstat; + uint32_t status; + uint32_t ctl_reg; int new_end, orig_end; struct ifnet *ifp = &sc->sc_ethercom.ec_if; @@ -958,7 +958,7 @@ if (ctl_reg) { #if defined(SQ_DEBUG) - u_int32_t reg; + uint32_t reg; reg = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl); SQ_DPRINTF(("%s: rxintr: done at %d (ctl %08x)\n", @@ -982,7 +982,7 @@ bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0, sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); - pktstat = *((u_int8_t*)m->m_data + framelen + 2); + pktstat = *((uint8_t*)m->m_data + framelen + 2); if ((pktstat & RXSTAT_GOOD) == 0) { ifp->if_ierrors++; @@ -1066,7 +1066,7 @@ sq_txintr(struct sq_softc *sc) { int shift = 0; - u_int32_t status, tmp; + uint32_t status, tmp; struct ifnet *ifp = &sc->sc_ethercom.ec_if; if (sc->hpc_regs->revision != 3) @@ -1132,7 +1132,7 @@ * For now, we'll only reclaim on inactive DMA and assume * that a sufficiently large ring keeps us out of trouble. */ - u_int32_t reclaimto, status; + uint32_t reclaimto, status; int reclaimall, i = sc->sc_prevtx; struct ifnet *ifp = &sc->sc_ethercom.ec_if; @@ -1206,7 +1206,7 @@ * descriptors are left over. */ int i; - u_int32_t status = 0; + uint32_t status = 0; struct ifnet *ifp = &sc->sc_ethercom.ec_if; i = sc->sc_prevtx; Index: src/sys/arch/sgimips/hpc/pi1ppc.c diff -u src/sys/arch/sgimips/hpc/pi1ppc.c:1.7 src/sys/arch/sgimips/hpc/pi1ppc.c:1.8 --- src/sys/arch/sgimips/hpc/pi1ppc.c:1.7 Tue Dec 16 22:35:25 2008 +++ src/sys/arch/sgimips/hpc/pi1ppc.c Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: pi1ppc.c,v 1.7 2008/12/16 22:35:25 christos Exp $ */ +/* $NetBSD: pi1ppc.c,v 1.8 2011/01/25 12:21:04 tsutsui Exp $ */ /* * Copyright (c) 2001 Alcove - Nicolas Souchu @@ -33,7 +33,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: pi1ppc.c,v 1.7 2008/12/16 22:35:25 christos Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pi1ppc.c,v 1.8 2011/01/25 12:21:04 tsutsui Exp $"); #include "opt_pi1ppc.h" @@ -78,8 +78,8 @@ /* Prototypes for functions. */ /* PC-style register emulation */ -static u_int8_t r_reg(int reg, struct pi1ppc_softc *pi1ppc); -static void w_reg(int reg, struct pi1ppc_softc *pi1ppc, u_int8_t byte); +static uint8_t r_reg(int reg, struct pi1ppc_softc *pi1ppc); +static void w_reg(int reg, struct pi1ppc_softc *pi1ppc, uint8_t byte); #define AT_DATA_REG 0 #define AT_STAT_REG 1 @@ -110,7 +110,7 @@ static int pi1ppc_setmode(device_t, int); static int pi1ppc_getmode(device_t); static int pi1ppc_exec_microseq(device_t, struct ppbus_microseq * *); -static u_int8_t pi1ppc_io(device_t, int, u_char *, int, u_char); +static uint8_t pi1ppc_io(device_t, int, u_char *, int, u_char); static int pi1ppc_read_ivar(device_t, int, unsigned int *); static int pi1ppc_write_ivar(device_t, int, unsigned int *); static int pi1ppc_add_handler(device_t, void (*)(void *), void *); @@ -130,20 +130,20 @@ static void pi1ppc_std_write(struct pi1ppc_softc * const); /* Miscellaneous */ -static void pi1ppc_set_intr_mask(struct pi1ppc_softc * const, u_int8_t); -static u_int8_t pi1ppc_get_intr_stat(struct pi1ppc_softc * const); +static void pi1ppc_set_intr_mask(struct pi1ppc_softc * const, uint8_t); +static uint8_t pi1ppc_get_intr_stat(struct pi1ppc_softc * const); #ifdef USE_INDY_ACK_HACK -static u_int8_t pi1ppc_get_intr_mask(struct pi1ppc_softc * const); +static uint8_t pi1ppc_get_intr_mask(struct pi1ppc_softc * const); #endif -static int pi1ppc_poll_str(struct pi1ppc_softc * const, const u_int8_t, - const u_int8_t); +static int pi1ppc_poll_str(struct pi1ppc_softc * const, const uint8_t, + const uint8_t); static int pi1ppc_wait_interrupt(struct pi1ppc_softc * const, const void *, - const u_int8_t); + const uint8_t); static int pi1ppc_poll_interrupt_stat(struct pi1ppc_softc * const, - const u_int8_t); + const uint8_t); static int pi1ppc_match(device_t parent, cfdata_t match, void *aux); static void pi1ppc_attach(device_t parent, device_t self, void *aux); @@ -589,8 +589,8 @@ pi1ppc_setmode(device_t dev, int mode) { struct pi1ppc_softc *pi1ppc = device_private(dev); - u_int8_t ecr; - u_int8_t chipset_mode; + uint8_t ecr; + uint8_t chipset_mode; int s; int rval = 0; @@ -694,9 +694,9 @@ /* Bit 4 of ctl_reg_int_en is used to emulate the PC's int enable bit. Without it, lpt doesn't like the port. */ -static u_int8_t ctl_reg_int_en = 0; +static uint8_t ctl_reg_int_en = 0; -static u_int8_t +static uint8_t r_reg(int reg, struct pi1ppc_softc *pi1ppc) { int val = 0; @@ -746,7 +746,7 @@ } static void -w_reg(int reg, struct pi1ppc_softc *pi1ppc, u_int8_t byte) +w_reg(int reg, struct pi1ppc_softc *pi1ppc, uint8_t byte) { /* don't try to write to the status reg */ @@ -1015,11 +1015,11 @@ } /* General I/O routine */ -static u_int8_t +static uint8_t pi1ppc_io(device_t dev, int iop, u_char *addr, int cnt, u_char byte) { struct pi1ppc_softc *pi1ppc = device_private(dev); - u_int8_t val = 0; + uint8_t val = 0; int s; s = splpi1ppc(); @@ -1216,9 +1216,9 @@ pi1ppc_nibble_read(struct pi1ppc_softc *pi1ppc) { int i; - u_int8_t nibble[2]; - u_int8_t ctr; - u_int8_t str; + uint8_t nibble[2]; + uint8_t ctr; + uint8_t str; /* Enable interrupts if needed */ if (pi1ppc->sc_use & PI1PPC_USE_INTR) { @@ -1290,8 +1290,8 @@ static void pi1ppc_byte_read(struct pi1ppc_softc * const pi1ppc) { - u_int8_t ctr; - u_int8_t str; + uint8_t ctr; + uint8_t str; /* Check direction bit */ ctr = pi1ppc_r_ctr(pi1ppc); @@ -1372,7 +1372,7 @@ */ static void -pi1ppc_set_intr_mask(struct pi1ppc_softc * const pi1ppc, u_int8_t mask) +pi1ppc_set_intr_mask(struct pi1ppc_softc * const pi1ppc, uint8_t mask) { /* invert valid bits (0 = enabled) */ mask = ~mask; @@ -1384,7 +1384,7 @@ #ifdef USE_INDY_ACK_HACK -static u_int8_t +static uint8_t pi1ppc_get_intr_mask(struct pi1ppc_softc * const pi1ppc) { int val; @@ -1398,7 +1398,7 @@ } #endif -static u_int8_t +static uint8_t pi1ppc_get_intr_stat(struct pi1ppc_softc * const pi1ppc) { int val; @@ -1491,11 +1491,11 @@ * Returns 0 if device ready, error value otherwise. */ static int -pi1ppc_poll_str(struct pi1ppc_softc * const pi1ppc, const u_int8_t status, - const u_int8_t mask) +pi1ppc_poll_str(struct pi1ppc_softc * const pi1ppc, const uint8_t status, + const uint8_t mask) { unsigned int timecount; - u_int8_t str; + uint8_t str; int error = EIO; /* Wait for str to have status for MAXBUSYWAIT */ @@ -1517,7 +1517,7 @@ /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ static int pi1ppc_wait_interrupt(struct pi1ppc_softc * const pi1ppc, const void *where, - const u_int8_t irqstat) + const uint8_t irqstat) { int error = EIO; @@ -1575,10 +1575,10 @@ static int pi1ppc_poll_interrupt_stat(struct pi1ppc_softc * const pi1ppc, - const u_int8_t match) + const uint8_t match) { unsigned int timecount; - u_int8_t cur; + uint8_t cur; int error = EIO; #ifdef USE_INDY_ACK_HACK Index: src/sys/arch/sgimips/hpc/pi1ppcvar.h diff -u src/sys/arch/sgimips/hpc/pi1ppcvar.h:1.3 src/sys/arch/sgimips/hpc/pi1ppcvar.h:1.4 --- src/sys/arch/sgimips/hpc/pi1ppcvar.h:1.3 Wed Apr 16 06:25:23 2008 +++ src/sys/arch/sgimips/hpc/pi1ppcvar.h Tue Jan 25 12:21:04 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: pi1ppcvar.h,v 1.3 2008/04/16 06:25:23 cegger Exp $ */ +/* $NetBSD: pi1ppcvar.h,v 1.4 2011/01/25 12:21:04 tsutsui Exp $ */ /*- * Copyright (c) 2001 Alcove - Nicolas Souchu @@ -129,17 +129,17 @@ /* Input buffer: working pointers, and size in bytes. */ char * sc_inb; char * sc_inbstart; - u_int32_t sc_inb_nbytes; + uint32_t sc_inb_nbytes; int sc_inerr; /* Output buffer pointer, working pointer, and size in bytes. */ char * sc_outb; char * sc_outbstart; - u_int32_t sc_outb_nbytes; + uint32_t sc_outb_nbytes; int sc_outerr; /* DMA functions: setup by bus specific attach code */ - int (*sc_dma_start)(struct pi1ppc_softc *, void *, u_int, u_int8_t); + int (*sc_dma_start)(struct pi1ppc_softc *, void *, u_int, uint8_t); int (*sc_dma_finish)(struct pi1ppc_softc *); int (*sc_dma_abort)(struct pi1ppc_softc *); int (*sc_dma_malloc)(device_t, void **, bus_addr_t *, @@ -154,7 +154,7 @@ /* Device attachment state */ #define PI1PPC_ATTACHED 1 #define PI1PPC_NOATTACH 0 - u_int8_t sc_dev_ok; + uint8_t sc_dev_ok; /* * Hardware capabilities flags: standard mode and nibble mode are @@ -165,59 +165,59 @@ #define PI1PPC_HAS_DMA 0x02 /* DMA available */ #define PI1PPC_HAS_FIFO 0x04 /* FIFO available */ #define PI1PPC_HAS_PS2 0x08 /* PS2 mode capable */ - u_int8_t sc_has; /* Chipset detected capabilities */ + uint8_t sc_has; /* Chipset detected capabilities */ /* Flags specifying mode of chipset operation . */ #define PI1PPC_MODE_STD 0x01 /* Use centronics-compatible mode */ #define PI1PPC_MODE_PS2 0x02 /* Use PS2 mode */ #define PI1PPC_MODE_NIBBLE 0x10 /* Use nibble mode */ - u_int8_t sc_mode; /* Current operational mode */ + uint8_t sc_mode; /* Current operational mode */ /* Flags which further define chipset operation */ #define PI1PPC_USE_INTR 0x01 /* Use interrupts */ #define PI1PPC_USE_DMA 0x02 /* Use DMA */ - u_int8_t sc_use; /* Capabilities to use */ + uint8_t sc_use; /* Capabilities to use */ /* Parallel Port Chipset model. */ #define GENERIC 6 - u_int8_t sc_model; /* chipset model */ + uint8_t sc_model; /* chipset model */ /* EPP mode - UNUSED */ - u_int8_t sc_epp; + uint8_t sc_epp; /* Parallel Port Chipset Type. Only Indy-style needed? */ #define PI1PPC_TYPE_INDY 0 - u_int8_t sc_type; + uint8_t sc_type; /* Stored register values after an interrupt occurs */ - u_int8_t sc_ecr_intr; - u_int8_t sc_ctr_intr; - u_int8_t sc_str_intr; + uint8_t sc_ecr_intr; + uint8_t sc_ctr_intr; + uint8_t sc_str_intr; #define PI1PPC_IRQ_NONE 0x0 #define PI1PPC_IRQ_nACK 0x1 #define PI1PPC_IRQ_DMA 0x2 #define PI1PPC_IRQ_FIFO 0x4 #define PI1PPC_IRQ_nFAULT 0x8 - u_int8_t sc_irqstat; /* Record irq settings */ + uint8_t sc_irqstat; /* Record irq settings */ #define PI1PPC_DMA_INIT 0x01 #define PI1PPC_DMA_STARTED 0x02 #define PI1PPC_DMA_COMPLETE 0x03 #define PI1PPC_DMA_INTERRUPTED 0x04 #define PI1PPC_DMA_ERROR 0x05 - u_int8_t sc_dmastat; /* Record dma state */ + uint8_t sc_dmastat; /* Record dma state */ #define PI1PPC_PWORD_MASK 0x30 #define PI1PPC_PWORD_16 0x00 #define PI1PPC_PWORD_8 0x10 #define PI1PPC_PWORD_32 0x20 - u_int8_t sc_pword; /* PWord size: used for FIFO DMA transfers */ - u_int8_t sc_fifo; /* FIFO size */ + uint8_t sc_pword; /* PWord size: used for FIFO DMA transfers */ + uint8_t sc_fifo; /* FIFO size */ /* Indicates number of PWords in FIFO queues that generate interrupt */ - u_int8_t sc_wthr; /* writeIntrThresold */ - u_int8_t sc_rthr; /* readIntrThresold */ + uint8_t sc_wthr; /* writeIntrThresold */ + uint8_t sc_rthr; /* readIntrThresold */ };