Module Name: src
Committed By: cliff
Date: Sat Feb 5 06:17:41 UTC 2011
Added Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cpuset.h
Log Message:
add cpuset.h to allow abstracting bit-per-cpu run state variables (cpus_running
et. al.)
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/include/cpuset.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/mips/include/cpuset.h
diff -u /dev/null src/sys/arch/mips/include/cpuset.h:1.1.2.1
--- /dev/null Sat Feb 5 06:17:41 2011
+++ src/sys/arch/mips/include/cpuset.h Sat Feb 5 06:17:41 2011
@@ -0,0 +1,54 @@
+/* $NetBSD: cpuset.h,v 1.1.2.1 2011/02/05 06:17:41 cliff Exp $ */
+/* $NetBSD: cpuset.h,v 1.1.2.1 2011/02/05 06:17:41 cliff Exp $ */
+
+/*-
+ * Copyright (c) 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MIPS_CPUSET_H_
+#define _MIPS_CPUSET_H_
+
+#include <sys/atomic.h>
+
+#define CPUSET_MAXNUMCPU 64
+typedef uint64_t mips_cpuset_t;
+
+#define CPUSET_SINGLE(cpu) ((mips_cpuset_t)1 << (cpu))
+
+#define CPUSET_ADD(set, cpu) atomic_or_64((volatile uint64_t *)&(set), CPUSET_SINGLE(cpu))
+#define CPUSET_DEL(set, cpu) atomic_and_64((volatile uint64_t *)&(set), ~CPUSET_SINGLE(cpu))
+#define CPUSET_SUB(set1, set2) atomic_and_64((volatile uint64_t *)&(set1), ~(set2))
+
+#define CPUSET_EXCEPT(set, cpu) ((set) & ~CPUSET_SINGLE(cpu))
+
+#define CPUSET_HAS(set, cpu) ((set) & CPUSET_SINGLE(cpu))
+#define CPUSET_NEXT(set) (ffs(set) - 1)
+
+#define CPUSET_EMPTY(set) ((set) == (mips_cpuset_t)0)
+#define CPUSET_EQUAL(set1, set2) ((set1) == (set2))
+#define CPUSET_CLEAR(set) ((set) = (mips_cpuset_t)0)
+#define CPUSET_ASSIGN(set1, set2) ((set1) = (set2))
+
+#endif /* _MIPS_CPUSET_H_ */
