Module Name: src
Committed By: matt
Date: Tue Feb 8 06:16:59 UTC 2011
Modified Files:
src/sys/arch/powerpc/include/booke: e500reg.h
Log Message:
Add some P2020 / MPC856x definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/powerpc/include/booke/e500reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/include/booke/e500reg.h
diff -u src/sys/arch/powerpc/include/booke/e500reg.h:1.2 src/sys/arch/powerpc/include/booke/e500reg.h:1.3
--- src/sys/arch/powerpc/include/booke/e500reg.h:1.2 Tue Jan 18 01:02:54 2011
+++ src/sys/arch/powerpc/include/booke/e500reg.h Tue Feb 8 06:16:59 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: e500reg.h,v 1.2 2011/01/18 01:02:54 matt Exp $ */
+/* $NetBSD: e500reg.h,v 1.3 2011/02/08 06:16:59 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -77,8 +77,8 @@
#endif /* GPIO_PRIVATE */
#define PCIE1_BASE 0x0a000
-#define PCIE2_MPC8572_BASE 0x09000
-#define PCIE3_MPC8572_BASE 0x08000
+#define PCIE2_MPC8572_BASE 0x09000 /* P2020 too */
+#define PCIE3_MPC8572_BASE 0x08000 /* P2020 too */
#define PCIX1_MPC8548_BASE 0x08000
#define PCIX2_MPC8548_BASE 0x09000
#define PCIE2_MPC8544_BASE 0x09000 /* MPC8536 too */
@@ -292,6 +292,8 @@
/* Power-On Reset Configuration Values */
#define PORPLLSR 0x000 /* POR PLL ratio status register */
+#define E500_RATIO2 __PPCBITS(2,7)
+#define E500_RATIO2_GET(n) __SHIFTOUT(n, E500_RATIO2)
#define E500_RATIO __PPCBITS(10,15)
#define E500_RATIO_GET(n) __SHIFTOUT(n, E500_RATIO)
#define PCI1_CLK_SEL __PPCBIT(16)
@@ -299,6 +301,7 @@
#define PLAT_RATIO __PPCBITS(26,30)
#define PLAT_RATIO_GET(n) __SHIFTOUT(n, PLAT_RATIO)
#define PORBMSR 0x004 /* POR boot mode status register */
+#define PORBMSR_BCFG __PPCBITS(0,1)
#define PORBMSR_HA __PPCBITS(13,15)
#define PORBMSR_HA_GET(n) __SHIFTOUT(m, PORBMSR_HA)
#define PORBMSR_HA_PEXSRIO_AGENT 0 /* PCI Express & SRIO agent mode */
@@ -349,6 +352,13 @@
#define IOSEL_MPC8572_SRIO3125 13
#define IOSEL_MPC8572_SRIO1250 14
#define IOSEL_MPC8572_PCIE1_X8 15
+#define IOSEL_P20x0_PCIE1_X1 0
+#define IOSEL_P20x0_PCIE12_X1_3_X2 2
+#define IOSEL_P20x0_PCIE13_X2 4
+#define IOSEL_P20x0_PCIE1_X4 6
+#define IOSEL_P20x0_PCIE1_X1_SRIO12500_1X 13
+#define IOSEL_P20x0_PCIE12_X1_SGMII23 14
+#define IOSEL_P20x0_PCIE1_X2_SGMII23 15
#define PORDEVSR_PCI2_ARB __PPCBIT(13)
#define PORDEVSR_PCI1_ARB __PPCBIT(14)
#define PORDEVSR_PCI32 __PPCBIT(15)
@@ -411,16 +421,18 @@
#define DEVDISR_TLU1 __PPCBIT(9)
#define DEVDISR_USB2 __PPCBIT(9) /* MPC8536 */
#define DEVDISR_TLU2 __PPCBIT(10)
+#define DEVDISR_ESDHC_10 __PPCBIT(10)
#define DEVDISR_USB3 __PPCBIT(10) /* MPC8536 */
#define DEVDISR_L2 __PPCBIT(11) /* MPC8536 */
#define DEVDISR_SRIO __PPCBIT(12)
-#define DEVDISR_ESDHC __PPCBIT(12) /* MPC8536 */
+#define DEVDISR_ESDHC_12 __PPCBIT(12) /* MPC8536 */
#define DEVDISR_RMSG __PPCBIT(13)
#define DEVDISR_SATA1 __PPCBIT(13) /* MPC8536 */
-#define DEVDISR_DDR2 __PPCBIT(14)
-#define DEVDISR_DDR __PPCBIT(15)
-#define DEVDISR_SPI __PPCBIT(15) /* MPC8536 */
+#define DEVDISR_DDR2_14 __PPCBIT(14)
+#define DEVDISR_DDR_15 __PPCBIT(15)
+#define DEVDISR_SPI_15 __PPCBIT(15) /* MPC8536 */
#define DEVDISR_E500 __PPCBIT(16)
+#define DEVDISR_DDR_16 __PPCBIT(16) /* MPC8536 */
#define DEVDISR_TB __PPCBIT(17)
#define DEVDISR_E500_1 __PPCBIT(18)
#define DEVDISR_TB_1 __PPCBIT(19)
@@ -433,6 +445,7 @@
#define DEVDISR_TSEC3 __PPCBIT(26)
#define DEVDISR_TSEC4 __PPCBIT(27)
#define DEVDISR_FEC __PPCBIT(28)
+#define DEVDISR_SPI_28 __PPCBIT(28) /* P2020 */
#define DEVDISR_I2C __PPCBIT(29)
#define DEVDISR_DUART __PPCBIT(30)
#define DEVDISR_SRDS1 __PPCBIT(31) /* MPC8536 */
