Module Name: src
Committed By: kiyohara
Date: Sun Aug 7 15:04:46 UTC 2011
Modified Files:
src/sys/arch/bebox/bebox: machdep.c
Added Files:
src/sys/arch/bebox/include: bebox.h
Log Message:
Use BEBOX_REG for mapped to BAT instead of bebox_mb_reg.
To generate a diff of this commit:
cvs rdiff -u -r1.101 -r1.102 src/sys/arch/bebox/bebox/machdep.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/bebox/include/bebox.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/bebox/bebox/machdep.c
diff -u src/sys/arch/bebox/bebox/machdep.c:1.101 src/sys/arch/bebox/bebox/machdep.c:1.102
--- src/sys/arch/bebox/bebox/machdep.c:1.101 Thu Jun 30 00:52:55 2011
+++ src/sys/arch/bebox/bebox/machdep.c Sun Aug 7 15:04:46 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.101 2011/06/30 00:52:55 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.102 2011/08/07 15:04:46 kiyohara Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.101 2011/06/30 00:52:55 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.102 2011/08/07 15:04:46 kiyohara Exp $");
#include "opt_compat_netbsd.h"
#include "opt_ddb.h"
@@ -104,7 +104,6 @@
* Global variables used here and there
*/
char bootinfo[BOOTINFO_MAXSIZE];
-paddr_t bebox_mb_reg; /* BeBox MotherBoard register */
#define OFMEMREGIONS 32
struct mem_region physmemr[OFMEMREGIONS], availmemr[OFMEMREGIONS];
char bootpath[256];
@@ -167,12 +166,6 @@
void
cpu_startup(void)
{
- /*
- * BeBox Mother Board's Register Mapping
- */
- bebox_mb_reg = (vaddr_t) mapiodev(BEBOX_INTR_REG, PAGE_SIZE, false);
- if (!bebox_mb_reg)
- panic("cpu_startup: no room for interrupt register");
/*
* Do common VM initialization
Added files:
Index: src/sys/arch/bebox/include/bebox.h
diff -u /dev/null src/sys/arch/bebox/include/bebox.h:1.1
--- /dev/null Sun Aug 7 15:04:46 2011
+++ src/sys/arch/bebox/include/bebox.h Sun Aug 7 15:04:45 2011
@@ -0,0 +1,66 @@
+/* $NetBSD: bebox.h,v 1.1 2011/08/07 15:04:45 kiyohara Exp $ */
+/*
+ * Copyright (c) 2011 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BEBOX_H
+#define _BEBOX_H
+
+/*
+ * BeBox mainboard's Register
+ */
+#define BEBOX_REG 0x7ffff000
+
+#define BEBOX_SET_MASK 0x80000000
+#define BEBOX_CLEAR_MASK 0x00000000
+
+#define READ_BEBOX_REG(reg) *(uint32_t *)(BEBOX_REG + (reg))
+#define SET_BEBOX_REG(reg, v) \
+ *(uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_SET_MASK)
+#define CLEAR_BEBOX_REG(reg, v) \
+ *(uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_CLEAR_MASK)
+
+#define CPU0_INT_MASK 0x0f0 /* Interrupt Mask for CPU0 */
+#define CPU1_INT_MASK 0x1f0 /* Interrupt Mask for CPU1 */
+#define INT_SOURCE 0x2f0 /* Interrupt Source */
+#define CPU_CONTROL 0x3f0 /* Inter-CPU Interrupt */
+#define CPU_RESET 0x4f0 /* Reset Control */
+#define INTR_VECTOR_REG 0xff0
+
+/* Control */
+#define CPU0_SMI (1 << 30) /* SMI to CPU0 */
+#define CPU1_SMI (1 << 29) /* SMI to CPU1 */
+#define CPU1_INT (1 << 28) /* Interrupt to CPU1 (rev.1 only) */
+#define CPU0_TLBISYNC (1 << 27) /* tlbsync to CPU0 */
+#define CPU1_TLBISYNC (1 << 26) /* tlbsync to CPU1 */
+#define WHO_AM_I (1 << 25)
+
+#define TLBISYNC_FROM(n) (1 << (CPU1_TLBISYNC + (n)))
+
+/* Reset */
+#define CPU1_SRESET (1 << 30) /* Software Reset to CPU1 */
+#define CPU1_HRESET (1 << 29) /* Hardware Reset to CPU1 */
+
+#endif /* _BEBOX_H */
