Module Name: src
Committed By: jdc
Date: Sun Oct 23 06:06:24 UTC 2011
Modified Files:
src/sys/arch/sparc64/dev: ffb.c ffbreg.h
Log Message:
Correct the VSYNC-related register definitions and rework how they are used
(only when the monitor supports composite sync). OK macallan@.
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/sparc64/dev/ffb.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/sparc64/dev/ffbreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/dev/ffb.c
diff -u src/sys/arch/sparc64/dev/ffb.c:1.46 src/sys/arch/sparc64/dev/ffb.c:1.47
--- src/sys/arch/sparc64/dev/ffb.c:1.46 Thu Aug 18 12:53:25 2011
+++ src/sys/arch/sparc64/dev/ffb.c Sun Oct 23 06:06:24 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: ffb.c,v 1.46 2011/08/18 12:53:25 macallan Exp $ */
+/* $NetBSD: ffb.c,v 1.47 2011/10/23 06:06:24 jdc Exp $ */
/* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */
/*
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.46 2011/08/18 12:53:25 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.47 2011/10/23 06:06:24 jdc Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -1355,32 +1355,21 @@ ffb_set_vmode(struct ffb_softc *sc, stru
}
/* DAC Control and Timing Generator Control */
- if (mode->flags & VID_PVSYNC) {
- dcl = FFB_DAC_DAC_CTRL_POS_SYNC;
- if (mode->flags & VID_NHSYNC) {
-#if 0
-/* XXX */
- dcl |= FFB_DAC_DAC_CTRL_VSYNC_REV;
-#endif
- tgc = 0;
- } else {
- tgc = FFB_DAC_TGC_EQUAL_DISABLE;
- }
- } else {
+ if (mode->flags & VID_PVSYNC)
+ dcl = FFB_DAC_DAC_CTRL_POS_VSYNC;
+ else
dcl = 0;
- if (mode->flags & VID_PVSYNC) {
- dcl |= FFB_DAC_DAC_CTRL_VSYNC_REV;
- tgc = 0;
- } else {
- tgc = FFB_DAC_TGC_EQUAL_DISABLE;
- }
- }
+ tgc = 0;
#define EDID_VID_INP sc->sc_edid_info.edid_video_input
-
- if (!(EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) {
+ if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) {
+ dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS;
+ tgc = FFB_DAC_TGC_EQUAL_DISABLE;
+ } else {
dcl |= FFB_DAC_DAC_CTRL_SYNC_G;
if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS)
tgc |= FFB_DAC_TGC_VSYNC_DISABLE;
+ else
+ tgc = FFB_DAC_TGC_EQUAL_DISABLE;
}
if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK)
dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE;
Index: src/sys/arch/sparc64/dev/ffbreg.h
diff -u src/sys/arch/sparc64/dev/ffbreg.h:1.8 src/sys/arch/sparc64/dev/ffbreg.h:1.9
--- src/sys/arch/sparc64/dev/ffbreg.h:1.8 Mon May 9 08:44:22 2011
+++ src/sys/arch/sparc64/dev/ffbreg.h Sun Oct 23 06:06:24 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: ffbreg.h,v 1.8 2011/05/09 08:44:22 jdc Exp $ */
+/* $NetBSD: ffbreg.h,v 1.9 2011/10/23 06:06:24 jdc Exp $ */
/* $OpenBSD: creatorreg.h,v 1.5 2002/07/29 06:21:45 jason Exp $ */
/*
@@ -103,8 +103,8 @@
/* 0x5001 DAC control */
#define FFB_DAC_DAC_CTRL_SYNC_G 0x0020 /* enable sync on green */
#define FFB_DAC_DAC_CTRL_PED_ENABLE 0x0040 /* enable pedestal */
-#define FFB_DAC_DAC_CTRL_VSYNC_REV 0x0080 /* reverse vsync (BT497A) */
-#define FFB_DAC_DAC_CTRL_POS_SYNC 0x0100 /* enable pos. sync (BT497A) */
+#define FFB_DAC_DAC_CTRL_VSYNC_DIS 0x0080 /* disable vsync pin */
+#define FFB_DAC_DAC_CTRL_POS_VSYNC 0x0100 /* enable pos. vsync */
/* 0x6000 timing generator control */
#define FFB_DAC_TGC_VIDEO_ENABLE 0x01 /* enable DAC outputs */
