Module Name: src
Committed By: matt
Date: Wed Oct 17 18:55:43 UTC 2012
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_armv7.S
Log Message:
Add a few more DSBs before flushing cache lines.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.8
--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.7 Sun Oct 7 18:47:07 2012
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Wed Oct 17 18:55:43 2012
@@ -139,6 +139,7 @@ ENTRY(armv7_dcache_wb_range)
and r3, r0, ip @ get offset into cache line
add r1, r1, r3 @ add to length
bic r0, r0, ip @ clear offset from start.
+ dsb
1:
mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache to PoC
add r0, r0, r2
@@ -158,6 +159,7 @@ ENTRY(armv7_dcache_wbinv_range)
and r3, r0, ip @ get offset into cache line
add r1, r1, r3 @ add to length
bic r0, r0, ip @ clear offset from start.
+ dsb
1:
mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line
add r0, r0, r2
@@ -198,6 +200,7 @@ ENTRY(armv7_idcache_wbinv_range)
and r3, r0, ip @ get offset into cache line
add r1, r1, r3 @ add to length
bic r0, r0, ip @ clear offset from start.
+ dsb
1:
mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line
mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line
