Module Name: src
Committed By: nakayama
Date: Thu Nov 8 16:30:12 UTC 2012
Modified Files:
src/sys/arch/sparc64/include: ctlreg.h psl.h
Log Message:
Move ASRs macro to more appropriate header.
While there remove useless macro.
To generate a diff of this commit:
cvs rdiff -u -r1.57 -r1.58 src/sys/arch/sparc64/include/ctlreg.h
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/sparc64/include/psl.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/include/ctlreg.h
diff -u src/sys/arch/sparc64/include/ctlreg.h:1.57 src/sys/arch/sparc64/include/ctlreg.h:1.58
--- src/sys/arch/sparc64/include/ctlreg.h:1.57 Thu Nov 8 00:34:37 2012
+++ src/sys/arch/sparc64/include/ctlreg.h Thu Nov 8 16:30:12 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.57 2012/11/08 00:34:37 macallan Exp $ */
+/* $NetBSD: ctlreg.h,v 1.58 2012/11/08 16:30:12 nakayama Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -410,32 +410,6 @@
#define IRDR_3H 0x70 /* unimplemented */
#define IRDR_3L 0x78 /* unimplemented */
-/* SOFTINT ASRs */
-#define SET_SOFTINT %asr20 /* Sets these bits */
-#define CLEAR_SOFTINT %asr21 /* Clears these bits */
-#define SOFTINT %asr22 /* Reads the register */
-#define TICK_CMPR %asr23
-#define STICK %asr24
-#define STICK_CMPR %asr25
-
-#define TICK_INT 0x01 /* level-14 clock tick */
-#define SOFTINT1 (0x1<<1)
-#define SOFTINT2 (0x1<<2)
-#define SOFTINT3 (0x1<<3)
-#define SOFTINT4 (0x1<<4)
-#define SOFTINT5 (0x1<<5)
-#define SOFTINT6 (0x1<<6)
-#define SOFTINT7 (0x1<<7)
-#define SOFTINT8 (0x1<<8)
-#define SOFTINT9 (0x1<<9)
-#define SOFTINT10 (0x1<<10)
-#define SOFTINT11 (0x1<<11)
-#define SOFTINT12 (0x1<<12)
-#define SOFTINT13 (0x1<<13)
-#define SOFTINT14 (0x1<<14)
-#define SOFTINT15 (0x1<<15)
-#define STICK_INTR (0x1<<16) /* system tick */
-
/* Interrupt Dispatch -- usually reserved for cross-calls */
#define ASR_IDSR 0x48 /* Interrupt dispatch status reg */
#define IDSR 0x00
Index: src/sys/arch/sparc64/include/psl.h
diff -u src/sys/arch/sparc64/include/psl.h:1.50 src/sys/arch/sparc64/include/psl.h:1.51
--- src/sys/arch/sparc64/include/psl.h:1.50 Thu Nov 8 00:34:37 2012
+++ src/sys/arch/sparc64/include/psl.h Thu Nov 8 16:30:12 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: psl.h,v 1.50 2012/11/08 00:34:37 macallan Exp $ */
+/* $NetBSD: psl.h,v 1.51 2012/11/08 16:30:12 nakayama Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -264,6 +264,20 @@
#define CWP 0x01f
+/*
+ * UltraSPARC Ancillary State Registers
+ */
+#define SET_SOFTINT %asr20 /* Set Software Interrupt register bits */
+#define CLEAR_SOFTINT %asr21 /* Clear Software Interrupt register bits */
+#define SOFTINT %asr22 /* Software Interrupt register */
+#define TICK_CMPR %asr23 /* TICK Compare register */
+#define STICK %asr24 /* STICK register */
+#define STICK_CMPR %asr25 /* STICK Compare register */
+
+/* SOFTINT bit descriptions */
+#define TICK_INT 0x01 /* CPU clock timer interrupt */
+#define STICK_INT (0x1<<16) /* system clock timer interrupt */
+
/* 64-byte alignment -- this seems the best place to put this. */
#define SPARC64_BLOCK_SIZE 64
#define SPARC64_BLOCK_ALIGN 0x3f
