Module Name:    src
Committed By:   rkujawa
Date:           Mon Nov 19 22:22:56 UTC 2012

Modified Files:
        src/sys/dev/ata: ata_wdc.c
        src/sys/dev/ic: wdc.c wdcvar.h

Log Message:
Introduce WDC_CAPABILITY_NO_AUXCTL flag. For lame controllers that don't
have aux control registers (driver coming soon).


To generate a diff of this commit:
cvs rdiff -u -r1.101 -r1.102 src/sys/dev/ata/ata_wdc.c
cvs rdiff -u -r1.274 -r1.275 src/sys/dev/ic/wdc.c
cvs rdiff -u -r1.95 -r1.96 src/sys/dev/ic/wdcvar.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/dev/ata/ata_wdc.c
diff -u src/sys/dev/ata/ata_wdc.c:1.101 src/sys/dev/ata/ata_wdc.c:1.102
--- src/sys/dev/ata/ata_wdc.c:1.101	Tue Jul 31 15:50:34 2012
+++ src/sys/dev/ata/ata_wdc.c	Mon Nov 19 22:22:56 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: ata_wdc.c,v 1.101 2012/07/31 15:50:34 bouyer Exp $	*/
+/*	$NetBSD: ata_wdc.c,v 1.102 2012/11/19 22:22:56 rkujawa Exp $	*/
 
 /*
  * Copyright (c) 1998, 2001, 2003 Manuel Bouyer.
@@ -54,7 +54,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.101 2012/07/31 15:50:34 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.102 2012/11/19 22:22:56 rkujawa Exp $");
 
 #include "opt_ata.h"
 #include "opt_wdc.h"
@@ -211,8 +211,9 @@ wdc_ata_bio_start(struct ata_channel *ch
 		 * disable interrupts, all commands here should be quick
 		 * enough to be able to poll, and we don't go here that often
 		 */
-		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
-		    WDCTL_4BIT | WDCTL_IDS);
+		if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
+			bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 
+			    wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS);
 		if (wdc->select)
 			wdc->select(chp, xfer->c_drive);
 		bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
@@ -289,8 +290,9 @@ ready:
 		/*
 		 * The drive is usable now
 		 */
-		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
-		    WDCTL_4BIT);
+		if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
+			bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 
+			    wd_aux_ctlr, WDCTL_4BIT);
 		delay(10); /* some drives need a little delay here */
 	}
 
@@ -317,7 +319,10 @@ ctrlerror:
 ctrldone:
 	drvp->state = 0;
 	wdc_ata_bio_done(chp, xfer);
-	bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
+
+	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
+		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 
+		    WDCTL_4BIT);
 	return;
 }
 

Index: src/sys/dev/ic/wdc.c
diff -u src/sys/dev/ic/wdc.c:1.274 src/sys/dev/ic/wdc.c:1.275
--- src/sys/dev/ic/wdc.c:1.274	Tue Jul 31 15:50:34 2012
+++ src/sys/dev/ic/wdc.c	Mon Nov 19 22:22:56 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: wdc.c,v 1.274 2012/07/31 15:50:34 bouyer Exp $ */
+/*	$NetBSD: wdc.c,v 1.275 2012/11/19 22:22:56 rkujawa Exp $ */
 
 /*
  * Copyright (c) 1998, 2001, 2003 Manuel Bouyer.  All rights reserved.
@@ -58,7 +58,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.274 2012/07/31 15:50:34 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.275 2012/11/19 22:22:56 rkujawa Exp $");
 
 #include "opt_ata.h"
 #include "opt_wdc.h"
@@ -156,7 +156,6 @@ static int	__wdcwait(struct ata_channel 
 
 static void	wdc_datain_pio(struct ata_channel *, int, void *, size_t);
 static void	wdc_dataout_pio(struct ata_channel *, int, void *, size_t);
-
 #define DEBUG_INTR   0x01
 #define DEBUG_XFERS  0x02
 #define DEBUG_STATUS 0x04
@@ -698,7 +697,11 @@ wdcprobe1(struct ata_channel *chp, int p
 	wdc->reset(chp, RESET_POLL);
 	DELAY(2000);
 	(void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
-	bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
+
+	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 
+		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 
+		    WDCTL_4BIT);
+
 #ifdef WDC_NO_IDS
 	ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL);
 #else
@@ -1052,7 +1055,10 @@ wdcreset(struct ata_channel *chp, int po
 			aprint_normal(" drive 1");
 		aprint_normal("\n");
 	}
-	bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
+	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 
+		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 
+		    WDCTL_4BIT);
+
 	return  (drv_mask1 != drv_mask2) ? 1 : 0;
 }
 
@@ -1071,12 +1077,15 @@ wdc_do_reset(struct ata_channel *chp, in
 	bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM);
 	delay(10);	/* 400ns delay */
 	/* assert SRST, wait for reset to complete */
-	bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
-	    WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
-	delay(2000);
+	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) {
+		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
+		    WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
+		delay(2000);
+	}
 	(void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
-	bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
-	    WDCTL_4BIT | WDCTL_IDS);
+	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 
+		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
+		    WDCTL_4BIT | WDCTL_IDS);
 	delay(10);	/* 400ns delay */
 	if (poll != RESET_SLEEP) {
 		/* ACK interrupt in case there is one pending left */
@@ -1456,8 +1465,9 @@ __wdccommand_start(struct ata_channel *c
 	}
 	if (ata_c->flags & AT_POLL) {
 		/* polled command, disable interrupts */
-		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
-		    WDCTL_4BIT | WDCTL_IDS);
+		if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 
+			bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 
+			    wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS);
 	}
 	if ((ata_c->flags & AT_LBA48) != 0) {
 		wdccommandext(chp, drive, ata_c->r_command,
@@ -1635,13 +1645,16 @@ __wdccommand_done(struct ata_channel *ch
 		    wdr->cmd_iohs[wd_sdh], 0);
 
 		if ((ata_c->flags & AT_LBA48) != 0) {
-			if ((ata_c->flags & AT_POLL) != 0)
-				bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh,
-				    wd_aux_ctlr,
-				    WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS);
-			else
-				bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh,
-				    wd_aux_ctlr, WDCTL_HOB|WDCTL_4BIT);
+			if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) {
+				if ((ata_c->flags & AT_POLL) != 0)
+					bus_space_write_1(wdr->ctl_iot, 
+					    wdr->ctl_ioh, wd_aux_ctlr,
+					    WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS);
+				else
+					bus_space_write_1(wdr->ctl_iot, 
+					    wdr->ctl_ioh, wd_aux_ctlr, 
+					    WDCTL_HOB|WDCTL_4BIT);
+			}
 			ata_c->r_count |= bus_space_read_1(wdr->cmd_iot,
 			    wdr->cmd_iohs[wd_seccnt], 0) << 8;
 			ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot,
@@ -1650,12 +1663,16 @@ __wdccommand_done(struct ata_channel *ch
 			    wdr->cmd_iohs[wd_cyl_lo], 0) << 32;
 			ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot,
 			    wdr->cmd_iohs[wd_cyl_hi], 0) << 40;
-			if ((ata_c->flags & AT_POLL) != 0)
-				bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh,
-				    wd_aux_ctlr, WDCTL_4BIT|WDCTL_IDS);
-			else
-				bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh,
-				     wd_aux_ctlr, WDCTL_4BIT);
+			if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) {
+				if ((ata_c->flags & AT_POLL) != 0)
+					bus_space_write_1(wdr->ctl_iot, 
+					    wdr->ctl_ioh, wd_aux_ctlr, 
+					    WDCTL_4BIT|WDCTL_IDS);
+				else
+					bus_space_write_1(wdr->ctl_iot, 
+					    wdr->ctl_ioh, wd_aux_ctlr, 
+					    WDCTL_4BIT);
+			}
 		} else {
 			ata_c->r_lba |=
 			    (uint64_t)(ata_c->r_device & 0x0f) << 24;
@@ -1666,8 +1683,9 @@ __wdccommand_done(struct ata_channel *ch
 	chp->ch_queue->active_xfer = NULL;
 	if (ata_c->flags & AT_POLL) {
 		/* enable interrupts */
-		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
-		    WDCTL_4BIT);
+		if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 
+			bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 
+			    wd_aux_ctlr, WDCTL_4BIT);
 		delay(10); /* some drives need a little delay here */
 	}
 	if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) {

Index: src/sys/dev/ic/wdcvar.h
diff -u src/sys/dev/ic/wdcvar.h:1.95 src/sys/dev/ic/wdcvar.h:1.96
--- src/sys/dev/ic/wdcvar.h:1.95	Tue Jul 31 15:50:35 2012
+++ src/sys/dev/ic/wdcvar.h	Mon Nov 19 22:22:56 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: wdcvar.h,v 1.95 2012/07/31 15:50:35 bouyer Exp $	*/
+/*	$NetBSD: wdcvar.h,v 1.96 2012/11/19 22:22:56 rkujawa Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
@@ -81,7 +81,8 @@ struct wdc_softc {
 	int		cap;		/* controller capabilities */
 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
 #define WDC_CAPABILITY_PREATA	0x0200	/* ctrl can be a pre-ata one */
-#define WDC_CAPABILITY_WIDEREGS 0x0400  /* Ctrl has wide (16bit) registers  */
+#define WDC_CAPABILITY_WIDEREGS 0x0400  /* ctrl has wide (16bit) registers  */
+#define WDC_CAPABILITY_NO_AUXCTL 0x0800 /* ctrl has no aux control registers */
 
 #if NATA_DMA || NATA_PIOBM
 	/* if WDC_CAPABILITY_DMA set in 'cap' */

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