Module Name: src
Committed By: jkunz
Date: Sun Dec 16 19:08:45 UTC 2012
Modified Files:
src/sys/arch/evbarm/stand/bootimx23: boot_prep.c bootimx23.bd
clock_prep.c common.c common.h emi_prep.c pinctrl_prep.c
power_prep.c
Log Message:
Contribution from Petri Laakso.
Refactoring of bootimx23:
- Code style clean up.
- Don't do DCDC initialization in bootimx23. This has proven to be
unreliable. DCDC initialization will be done in kernel later.
Use linear regulators while booting to make bootimx23 reliable.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbarm/stand/bootimx23/boot_prep.c \
src/sys/arch/evbarm/stand/bootimx23/clock_prep.c \
src/sys/arch/evbarm/stand/bootimx23/common.c \
src/sys/arch/evbarm/stand/bootimx23/common.h \
src/sys/arch/evbarm/stand/bootimx23/emi_prep.c \
src/sys/arch/evbarm/stand/bootimx23/pinctrl_prep.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbarm/stand/bootimx23/bootimx23.bd \
src/sys/arch/evbarm/stand/bootimx23/power_prep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/stand/bootimx23/boot_prep.c
diff -u src/sys/arch/evbarm/stand/bootimx23/boot_prep.c:1.1 src/sys/arch/evbarm/stand/bootimx23/boot_prep.c:1.2
--- src/sys/arch/evbarm/stand/bootimx23/boot_prep.c:1.1 Tue Nov 20 19:08:46 2012
+++ src/sys/arch/evbarm/stand/bootimx23/boot_prep.c Sun Dec 16 19:08:44 2012
@@ -1,4 +1,4 @@
-/* $Id: boot_prep.c,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */
+/* $Id: boot_prep.c,v 1.2 2012/12/16 19:08:44 jkunz Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -39,15 +39,15 @@
#include "common.h"
/*
- * Initialize i.MX23 power, clock and DRAM.
+ * Initialize i.MX23 power, clocks and DRAM.
*/
int
_start(void)
{
- /* Make sure timer is running */
- REG_WRITE(HW_DIGCTL_BASE + HW_DIGCTL_CTRL_CLR,
- HW_DIGCTL_CTRL_XTAL24M_GATE);
+ /* Make sure timer is running. */
+ REG_WR(HW_DIGCTL_BASE + HW_DIGCTL_CTRL_CLR,
+ HW_DIGCTL_CTRL_XTAL24M_GATE);
printf("\n\rBooting");
@@ -58,7 +58,6 @@ _start(void)
putchar('.');
pinctrl_prep();
- delay_us(1000);
putchar('.');
emi_prep();
Index: src/sys/arch/evbarm/stand/bootimx23/clock_prep.c
diff -u src/sys/arch/evbarm/stand/bootimx23/clock_prep.c:1.1 src/sys/arch/evbarm/stand/bootimx23/clock_prep.c:1.2
--- src/sys/arch/evbarm/stand/bootimx23/clock_prep.c:1.1 Tue Nov 20 19:08:46 2012
+++ src/sys/arch/evbarm/stand/bootimx23/clock_prep.c Sun Dec 16 19:08:44 2012
@@ -1,4 +1,4 @@
-/* $Id: clock_prep.c,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */
+/* $Id: clock_prep.c,v 1.2 2012/12/16 19:08:44 jkunz Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -39,26 +39,28 @@
#include "common.h"
-void enable_pll(void);
-void enable_ref_cpu(int);
-void enable_ref_emi(int);
-void enable_ref_io(int);
-void use_ref_cpu(void);
-void use_ref_emi(void);
-void use_ref_io(void);
-void set_hbus_div(int);
-void set_emi_div(int);
-void set_ssp_div(int);
-
-/* Clock frequences after clock_prep() */
-#define CPU_FRAC 0x13 /* CPUCLK @ 454.74 MHz */
-#define HBUS_DIV 0x3 /* AHBCLK @ 151.58 MHz */
-#define EMI_FRAC 0x21 /* EMICLK @ 130.91 MHz */
-#define EMI_DIV 0x2
-#define IO_FRAC 0x12 /* IOCLK @ 480.00 MHz */
-#define SSP_DIV 0x5 /* SSPCLK @ 96.00 MHz */
+static void enable_pll(void);
+static void enable_ref_cpu(int);
+static void enable_ref_emi(int);
+static void enable_ref_io(int);
+static void use_ref_cpu(void);
+static void use_ref_emi(void);
+static void use_ref_io(void);
+static void set_hbus_div(int);
+static void set_emi_div(int);
+static void set_ssp_div(int);
+
+/*
+ * Clock frequences set by clock_prep()
+ */
+#define CPU_FRAC 0x13 /* CPUCLK @ 454.74 MHz */
+#define HBUS_DIV 0x3 /* AHBCLK @ 151.58 MHz */
+#define EMI_FRAC 0x21 /* EMICLK @ 130.91 MHz */
+#define EMI_DIV 0x2
+#define IO_FRAC 0x12 /* IOCLK @ 480.00 MHz */
+#define SSP_DIV 0x5 /* SSPCLK @ 96.00 MHz */
-/* Offset to frac register for byte store instructions. (strb) */
+/* Offset to frac register for CLKCTRL_WR_BYTE macro. */
#define HW_CLKCTRL_FRAC_CPU (HW_CLKCTRL_FRAC+0)
#define HW_CLKCTRL_FRAC_EMI (HW_CLKCTRL_FRAC+1)
#define HW_CLKCTRL_FRAC_IO (HW_CLKCTRL_FRAC+3)
@@ -86,9 +88,7 @@ clock_prep(void)
enable_ref_io(IO_FRAC);
set_emi_div(EMI_DIV);
set_hbus_div(HBUS_DIV);
- delay_us(1000);
use_ref_cpu();
- //delay_us(1000);
use_ref_emi();
use_ref_io();
set_ssp_div(SSP_DIV);
@@ -99,7 +99,7 @@ clock_prep(void)
/*
* Turn PLL on and wait until it's locked to 480 MHz.
*/
-void
+static void
enable_pll(void)
{
@@ -112,7 +112,7 @@ enable_pll(void)
/*
* Enable fractional divider clock ref_cpu with divide value "frac".
*/
-void
+static void
enable_ref_cpu(int frac)
{
uint32_t reg;
@@ -128,7 +128,7 @@ enable_ref_cpu(int frac)
/*
* Enable fractional divider clock ref_emi with divide value "frac".
*/
-void
+static void
enable_ref_emi(int frac)
{
uint32_t reg;
@@ -144,7 +144,7 @@ enable_ref_emi(int frac)
/*
* Enable fractional divider clock ref_io with divide value "frac".
*/
-void
+static void
enable_ref_io(int frac)
{
uint32_t reg;
@@ -160,7 +160,7 @@ enable_ref_io(int frac)
/*
* Divide CLK_P by "div" to get CLK_H frequency.
*/
-void
+static void
set_hbus_div(int div)
{
uint32_t reg;
@@ -177,7 +177,7 @@ set_hbus_div(int div)
/*
* ref_emi is divied "div" to get CLK_EMI.
*/
-void
+static void
set_emi_div(int div)
{
uint32_t reg;
@@ -193,7 +193,7 @@ set_emi_div(int div)
/*
* ref_io is divied "div" to get CLK_SSP.
*/
-void
+static void
set_ssp_div(int div)
{
uint32_t reg;
@@ -209,7 +209,7 @@ set_ssp_div(int div)
/*
* Transition from ref_xtal to use ref_cpu.
*/
-void
+static void
use_ref_cpu(void)
{
CLKCTRL_WR(HW_CLKCTRL_CLKSEQ_CLR, HW_CLKCTRL_CLKSEQ_BYPASS_CPU);
@@ -219,7 +219,7 @@ use_ref_cpu(void)
/*
* Transition from ref_xtal to use ref_emi and source CLK_EMI from ref_emi.
*/
-void
+static void
use_ref_emi(void)
{
uint32_t reg;
@@ -238,7 +238,7 @@ use_ref_emi(void)
/*
* Transition from ref_xtal to use ref_io and source CLK_SSP from ref_io.
*/
-void
+static void
use_ref_io(void)
{
uint32_t reg;
Index: src/sys/arch/evbarm/stand/bootimx23/common.c
diff -u src/sys/arch/evbarm/stand/bootimx23/common.c:1.1 src/sys/arch/evbarm/stand/bootimx23/common.c:1.2
--- src/sys/arch/evbarm/stand/bootimx23/common.c:1.1 Tue Nov 20 19:08:46 2012
+++ src/sys/arch/evbarm/stand/bootimx23/common.c Sun Dec 16 19:08:44 2012
@@ -1,4 +1,4 @@
-/* $Id: common.c,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */
+/* $Id: common.c,v 1.2 2012/12/16 19:08:44 jkunz Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,6 +30,7 @@
*/
#include <sys/param.h>
+#include <sys/types.h>
#include <sys/cdefs.h>
#include <arm/imx/imx23_digctlreg.h>
@@ -38,16 +39,33 @@
#include "common.h"
/*
- * Delay "delay" microseconds.
+ * Delay us microseconds.
*/
void
-delay_us(unsigned int delay)
+delay(unsigned int us)
{
+ uint32_t start;
+ uint32_t now;
+ uint32_t elapsed;
+ uint32_t total;
+ uint32_t last;
+
+ total = 0;
+ last = 0;
+ start = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
+
+ do {
+ now = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
+
+ if (start <= now)
+ elapsed = now - start;
+ else /* Take care of overflow. */
+ elapsed = (UINT32_MAX - start) + 1 + now;
- /* Set microsecond timer to 0 */
- REG_WRITE(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS_CLR, 0xFFFFFFFF);
+ total += elapsed - last;
+ last = elapsed;
- while (REG_READ(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS) < delay);
+ } while (total < us);
return;
}
@@ -60,10 +78,14 @@ putchar(int ch)
{
/* Wait until transmit FIFO has space for the new character. */
- while (REG_READ(HW_UARTDBG_BASE + HW_UARTDBGFR) & HW_UARTDBGFR_TXFF);
+ while (REG_RD(HW_UARTDBG_BASE + HW_UARTDBGFR) & HW_UARTDBGFR_TXFF);
- REG_WRITE_BYTE(HW_UARTDBG_BASE + HW_UARTDBGDR,
+ REG_WR_BYTE(HW_UARTDBG_BASE + HW_UARTDBGDR,
__SHIFTIN(ch, HW_UARTDBGDR_DATA));
+#ifdef DEBUG
+ /* Flush: Wait until transmit FIFO contents are written to UART. */
+ while (!(REG_RD(HW_UARTDBG_BASE + HW_UARTDBGFR) & HW_UARTDBGFR_TXFE));
+#endif
return;
}
Index: src/sys/arch/evbarm/stand/bootimx23/common.h
diff -u src/sys/arch/evbarm/stand/bootimx23/common.h:1.1 src/sys/arch/evbarm/stand/bootimx23/common.h:1.2
--- src/sys/arch/evbarm/stand/bootimx23/common.h:1.1 Tue Nov 20 19:08:46 2012
+++ src/sys/arch/evbarm/stand/bootimx23/common.h Sun Dec 16 19:08:44 2012
@@ -1,4 +1,4 @@
-/* $Id: common.h,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */
+/* $Id: common.h,v 1.2 2012/12/16 19:08:44 jkunz Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -32,12 +32,12 @@
#ifndef _BOOTIMX23_COMMON_
#define _BOOTIMX23_COMMON_
-#define REG_READ(reg) *(volatile uint32_t *)(reg)
-#define REG_WRITE(reg, val) \
+#define REG_RD(reg) *(volatile uint32_t *)(reg)
+#define REG_WR(reg, val) \
do { \
*(volatile uint32_t *)((reg)) = val; \
} while (0)
-#define REG_WRITE_BYTE(reg, val) \
+#define REG_WR_BYTE(reg, val) \
do { \
*(volatile uint8_t *)((reg)) = val; \
} while (0)
@@ -46,7 +46,7 @@ int clock_prep(void);
int emi_prep(void);
int pinctrl_prep(void);
int power_prep(void);
-void delay_us(unsigned int);
+void delay(unsigned int);
void putchar(int);
#endif /* !_BOOTIMX23_COMMON_ */
Index: src/sys/arch/evbarm/stand/bootimx23/emi_prep.c
diff -u src/sys/arch/evbarm/stand/bootimx23/emi_prep.c:1.1 src/sys/arch/evbarm/stand/bootimx23/emi_prep.c:1.2
--- src/sys/arch/evbarm/stand/bootimx23/emi_prep.c:1.1 Tue Nov 20 19:08:46 2012
+++ src/sys/arch/evbarm/stand/bootimx23/emi_prep.c Sun Dec 16 19:08:44 2012
@@ -1,4 +1,4 @@
-/* $Id: emi_prep.c,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */
+/* $Id: emi_prep.c,v 1.2 2012/12/16 19:08:44 jkunz Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -39,9 +39,9 @@
#include "common.h"
-void init_dram_registers(void);
-void start_dram(void);
-uint32_t get_dram_int_status(void);
+static void init_dram_registers(void);
+static void start_dram(void);
+static uint32_t get_dram_int_status(void);
/*
* Initialize external DRAM memory.
@@ -64,58 +64,58 @@ emi_prep(void)
* settings were to HW_DRAM_CTL19_DQS_OUT_SHIFT which was set to 16 as a result
* from trial and error.
*/
-void
+static void
init_dram_registers(void)
{
uint32_t reg;
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL00, 0x01010001);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL01, 0x00010100);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL02, 0x01000101);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL03, 0x00000001);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL04, 0x00000101);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL05, 0x00000000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL06, 0x00010000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL07, 0x01000001);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL00, 0x01010001);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL01, 0x00010100);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL02, 0x01000101);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL03, 0x00000001);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL04, 0x00000101);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL05, 0x00000000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL06, 0x00010000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL07, 0x01000001);
// HW_DRAM_CTL08 initialized last.
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL09, 0x00000001);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL10, 0x07000200);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL11, 0x00070202);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL12, 0x02020000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL13, 0x04040a01);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL14, 0x00000201);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL15, 0x02040000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL16, 0x02000000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL17, 0x19000f08);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL18, 0x0d0d0000);
-// REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL19, 0x02021313);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL09, 0x00000001);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL10, 0x07000200);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL11, 0x00070202);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL12, 0x02020000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL13, 0x04040a01);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL14, 0x00000201);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL15, 0x02040000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL16, 0x02000000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL17, 0x19000f08);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL18, 0x0d0d0000);
+// REG_WR(HW_DRAM_BASE + HW_DRAM_CTL19, 0x02021313);
reg = __SHIFTIN(2, HW_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS) |
__SHIFTIN(16, HW_DRAM_CTL19_DQS_OUT_SHIFT) |
__SHIFTIN(19, HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1) |
__SHIFTIN(19, HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL19, reg);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL20, 0x02061521);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL21, 0x0000000a);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL22, 0x00080008);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL23, 0x00200020);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL24, 0x00200020);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL25, 0x00200020);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL26, 0x000003f7);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL19, reg);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL20, 0x02061521);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL21, 0x0000000a);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL22, 0x00080008);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL23, 0x00200020);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL24, 0x00200020);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL25, 0x00200020);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL26, 0x000003f7);
// HW_DRAM_CTL27
// HW_DRAM_CTL28
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL29, 0x00000020);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL30, 0x00000020);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL31, 0x00c80000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL32, 0x000a23cd);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL33, 0x000000c8);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL34, 0x00006665);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL29, 0x00000020);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL30, 0x00000020);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL31, 0x00c80000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL32, 0x000a23cd);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL33, 0x000000c8);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL34, 0x00006665);
// HW_DRAM_CTL35 is read only register
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL36, 0x00000101);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL37, 0x00040001);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL38, 0x00000000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL39, 0x00000000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL40, 0x00010000);
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL08, 0x01000000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL36, 0x00000101);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL37, 0x00040001);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL38, 0x00000000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL39, 0x00000000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL40, 0x00010000);
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, 0x01000000);
return;
}
@@ -123,15 +123,15 @@ init_dram_registers(void)
/*
* Start DRAM module. After return DRAM is ready to use.
*/
-void
+static void
start_dram(void)
{
uint32_t reg;
- reg = REG_READ(HW_DRAM_BASE + HW_DRAM_CTL08);
+ reg = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08);
reg |= HW_DRAM_CTL08_START;
- REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL08, reg);
-
+ REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, reg);
+
/* Wait until DRAM initialization is complete. */
while(!(get_dram_int_status() & (1<<2)));
@@ -141,11 +141,11 @@ start_dram(void)
/*
* Return DRAM controller interrupt status register.
*/
-uint32_t
+static uint32_t
get_dram_int_status(void)
{
uint32_t reg;
-
- reg = REG_READ(HW_DRAM_BASE + HW_DRAM_CTL18);
+
+ reg = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL18);
return __SHIFTOUT(reg, HW_DRAM_CTL18_INT_STATUS);
}
Index: src/sys/arch/evbarm/stand/bootimx23/pinctrl_prep.c
diff -u src/sys/arch/evbarm/stand/bootimx23/pinctrl_prep.c:1.1 src/sys/arch/evbarm/stand/bootimx23/pinctrl_prep.c:1.2
--- src/sys/arch/evbarm/stand/bootimx23/pinctrl_prep.c:1.1 Tue Nov 20 19:08:46 2012
+++ src/sys/arch/evbarm/stand/bootimx23/pinctrl_prep.c Sun Dec 16 19:08:44 2012
@@ -1,4 +1,4 @@
-/* $Id: pinctrl_prep.c,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */
+/* $Id: pinctrl_prep.c,v 1.2 2012/12/16 19:08:44 jkunz Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -39,12 +39,12 @@
#include "common.h"
-void configure_emi_mux(void);
-void configure_emi_drive(int);
-void disable_emi_padkeepers(void);
-void configure_ssp_mux();
-void configure_ssp_drive(int);
-void configure_ssp_pullups(void);
+static void configure_emi_mux(void);
+static void configure_emi_drive(int);
+static void disable_emi_padkeepers(void);
+static void configure_ssp_mux();
+static void configure_ssp_drive(int);
+static void configure_ssp_pullups(void);
/* EMI pins output drive strengths */
#define DRIVE_04_MA 0x0 /* 4 mA */
@@ -59,7 +59,7 @@ int
pinctrl_prep(void)
{
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR,
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR,
(HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE));
/* EMI. */
@@ -78,21 +78,21 @@ pinctrl_prep(void)
/*
* Configure external EMI pins to be used for DRAM.
*/
-void
+static void
configure_emi_mux(void)
{
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, (
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, (
HW_PINCTRL_MUXSEL4_BANK2_PIN15 | /* Pin 108, EMI_A06 */
HW_PINCTRL_MUXSEL4_BANK2_PIN14 | /* Pin 107, EMI_A05 */
HW_PINCTRL_MUXSEL4_BANK2_PIN13 | /* Pin 109, EMI_A04 */
HW_PINCTRL_MUXSEL4_BANK2_PIN12 | /* Pin 110, EMI_A03 */
HW_PINCTRL_MUXSEL4_BANK2_PIN11 | /* Pin 111, EMI_A02 */
HW_PINCTRL_MUXSEL4_BANK2_PIN10 | /* Pin 112, EMI_A01 */
- HW_PINCTRL_MUXSEL4_BANK2_PIN09) /* Pin 113, EMI_A00 */
+ HW_PINCTRL_MUXSEL4_BANK2_PIN09) /* Pin 113, EMI_A00 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR, (
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR, (
HW_PINCTRL_MUXSEL5_BANK2_PIN31 | /* Pin 114, EMI_WEN */
HW_PINCTRL_MUXSEL5_BANK2_PIN30 | /* Pin 98, EMI_RASN */
HW_PINCTRL_MUXSEL5_BANK2_PIN29 | /* Pin 115, EMI_CKE */
@@ -109,10 +109,10 @@ configure_emi_mux(void)
HW_PINCTRL_MUXSEL5_BANK2_PIN19 | /* Pin 104, EMI_A10 */
HW_PINCTRL_MUXSEL5_BANK2_PIN18 | /* Pin 103, EMI_A09 */
HW_PINCTRL_MUXSEL5_BANK2_PIN17 | /* Pin 106, EMI_A08 */
- HW_PINCTRL_MUXSEL5_BANK2_PIN16) /* Pin 105, EMI_A07 */
+ HW_PINCTRL_MUXSEL5_BANK2_PIN16) /* Pin 105, EMI_A07 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR, (
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR, (
HW_PINCTRL_MUXSEL6_BANK3_PIN15 | /* Pin 95, EMI_D15 */
HW_PINCTRL_MUXSEL6_BANK3_PIN14 | /* Pin 96, EMI_D14 */
HW_PINCTRL_MUXSEL6_BANK3_PIN13 | /* Pin 94, EMI_D13 */
@@ -128,16 +128,16 @@ configure_emi_mux(void)
HW_PINCTRL_MUXSEL6_BANK3_PIN03 | /* Pin 79, EMI_D03 */
HW_PINCTRL_MUXSEL6_BANK3_PIN02 | /* Pin 77, EMI_D02 */
HW_PINCTRL_MUXSEL6_BANK3_PIN01 | /* Pin 76, EMI_D01 */
- HW_PINCTRL_MUXSEL6_BANK3_PIN00) /* Pin 75, EMI_D00 */
+ HW_PINCTRL_MUXSEL6_BANK3_PIN00) /* Pin 75, EMI_D00 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR, (
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR, (
HW_PINCTRL_MUXSEL7_BANK3_PIN21 | /* Pin 72, EMI_CLKN */
HW_PINCTRL_MUXSEL7_BANK3_PIN20 | /* Pin 70, EMI_CLK */
HW_PINCTRL_MUXSEL7_BANK3_PIN19 | /* Pin 74, EMI_DQS1 */
HW_PINCTRL_MUXSEL7_BANK3_PIN18 | /* Pin 73, EMI_DQS0 */
HW_PINCTRL_MUXSEL7_BANK3_PIN17 | /* Pin 92, EMI_DQM1 */
- HW_PINCTRL_MUXSEL7_BANK3_PIN16) /* Pin 81, EMI_DQM0 */
+ HW_PINCTRL_MUXSEL7_BANK3_PIN16) /* Pin 81, EMI_DQM0 */
);
return;
@@ -147,13 +147,13 @@ configure_emi_mux(void)
* Configure EMI pins voltages to 1.8/2.5V operation and drive strength
* to "ma".
*/
-void
+static void
configure_emi_drive(int ma)
{
uint32_t drive;
/* DRIVE 9 */
- drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9);
+ drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9);
drive &= ~(
HW_PINCTRL_DRIVE9_BANK2_PIN15_V | /* Pin 108, EMI_A06 */
HW_PINCTRL_DRIVE9_BANK2_PIN15_MA |
@@ -169,7 +169,7 @@ configure_emi_drive(int ma)
HW_PINCTRL_DRIVE9_BANK2_PIN10_MA |
HW_PINCTRL_DRIVE9_BANK2_PIN09_V | /* Pin 113, EMI_A00 */
HW_PINCTRL_DRIVE9_BANK2_PIN09_MA |
- HW_PINCTRL_DRIVE9_RSRVD6 | /* Always write zeroes */
+ HW_PINCTRL_DRIVE9_RSRVD6 | /* Always write zeroes */
HW_PINCTRL_DRIVE9_RSRVD5 |
HW_PINCTRL_DRIVE9_RSRVD4 |
HW_PINCTRL_DRIVE9_RSRVD3 |
@@ -186,10 +186,10 @@ configure_emi_drive(int ma)
__SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN10_MA) | /* EMI_A01 */
__SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN09_MA) /* EMI_A00 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9, drive);
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9, drive);
/* DRIVE 10 */
- drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10);
+ drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10);
drive &= ~(
HW_PINCTRL_DRIVE10_BANK2_PIN23_V | /* Pin 117, EMI_BA1 */
HW_PINCTRL_DRIVE10_BANK2_PIN23_MA |
@@ -207,7 +207,7 @@ configure_emi_drive(int ma)
HW_PINCTRL_DRIVE10_BANK2_PIN17_MA |
HW_PINCTRL_DRIVE10_BANK2_PIN16_V | /* Pin 105, EMI_A07 */
HW_PINCTRL_DRIVE10_BANK2_PIN16_MA |
- HW_PINCTRL_DRIVE10_RSRVD6 | /* Always write zeroes */
+ HW_PINCTRL_DRIVE10_RSRVD6 | /* Always write zeroes */
HW_PINCTRL_DRIVE10_RSRVD5 |
HW_PINCTRL_DRIVE10_RSRVD4 |
HW_PINCTRL_DRIVE10_RSRVD3 |
@@ -225,10 +225,10 @@ configure_emi_drive(int ma)
__SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN17_MA) | /* EMI_A08 */
__SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN16_MA) /* EMI_A07 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10, drive);
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10, drive);
/* DRIVE 11 */
- drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11);
+ drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11);
drive &= ~(
HW_PINCTRL_DRIVE11_BANK2_PIN31_V | /* Pin 114, EMI_WEN */
HW_PINCTRL_DRIVE11_BANK2_PIN31_MA |
@@ -245,7 +245,7 @@ configure_emi_drive(int ma)
HW_PINCTRL_DRIVE11_BANK2_PIN25_MA |
HW_PINCTRL_DRIVE11_BANK2_PIN24_V | /* Pin 97, EMI_CASN */
HW_PINCTRL_DRIVE11_BANK2_PIN24_MA |
- HW_PINCTRL_DRIVE11_RSRVD6 | /* Always write zeroes */
+ HW_PINCTRL_DRIVE11_RSRVD6 | /* Always write zeroes */
HW_PINCTRL_DRIVE11_RSRVD5 |
HW_PINCTRL_DRIVE11_RSRVD4 |
HW_PINCTRL_DRIVE11_RSRVD3 |
@@ -257,16 +257,17 @@ configure_emi_drive(int ma)
__SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN31_MA) | /* EMI_WEN */
__SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN30_MA) | /* EMI_RASN */
__SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN29_MA) | /* EMI_CKE */
-#if 0 /* 169-Pin BGA Package */
+#if 0
+ /* 169-Pin BGA Package */
__SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN26_MA) | /* EMI_CE1N */
#endif
__SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN25_MA) | /* EMI_CE0N */
__SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN24_MA) /* EMI_CASN */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11, drive);
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11, drive);
/* DRIVE 12 */
- drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12);
+ drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12);
drive &= ~(
HW_PINCTRL_DRIVE12_BANK3_PIN07_V | /* Pin 85, EMI_D07 */
HW_PINCTRL_DRIVE12_BANK3_PIN07_MA |
@@ -284,7 +285,7 @@ configure_emi_drive(int ma)
HW_PINCTRL_DRIVE12_BANK3_PIN01_MA |
HW_PINCTRL_DRIVE12_BANK3_PIN00_V | /* Pin 75, EMI_D00 */
HW_PINCTRL_DRIVE12_BANK3_PIN00_MA |
- HW_PINCTRL_DRIVE12_RSRVD6 | /* Always write zeroes */
+ HW_PINCTRL_DRIVE12_RSRVD6 | /* Always write zeroes */
HW_PINCTRL_DRIVE12_RSRVD5 |
HW_PINCTRL_DRIVE12_RSRVD4 |
HW_PINCTRL_DRIVE12_RSRVD3 |
@@ -302,10 +303,10 @@ configure_emi_drive(int ma)
__SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN01_MA) | /* EMI_D01 */
__SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN00_MA) /* EMI_D00 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12, drive);
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12, drive);
/* DRIVE 13 */
- drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13);
+ drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13);
drive &= ~(
HW_PINCTRL_DRIVE13_BANK3_PIN15_V | /* Pin 95, EMI_D15 */
HW_PINCTRL_DRIVE13_BANK3_PIN15_MA |
@@ -323,7 +324,7 @@ configure_emi_drive(int ma)
HW_PINCTRL_DRIVE13_BANK3_PIN09_MA |
HW_PINCTRL_DRIVE13_BANK3_PIN08_V | /* Pin 86, EMI_D08 */
HW_PINCTRL_DRIVE13_BANK3_PIN08_MA |
- HW_PINCTRL_DRIVE13_RSRVD6 | /* Always write zeroes */
+ HW_PINCTRL_DRIVE13_RSRVD6 | /* Always write zeroes */
HW_PINCTRL_DRIVE13_RSRVD5 |
HW_PINCTRL_DRIVE13_RSRVD4 |
HW_PINCTRL_DRIVE13_RSRVD3 |
@@ -341,10 +342,10 @@ configure_emi_drive(int ma)
__SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN09_MA) | /* EMI_D09 */
__SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN08_MA) /* EMI_D08 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13, drive);
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13, drive);
/* DRIVE 14 */
- drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14);
+ drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14);
drive &= ~(
HW_PINCTRL_DRIVE14_BANK3_PIN21_V | /* Pin 72, EMI_CLKN */
HW_PINCTRL_DRIVE14_BANK3_PIN21_MA |
@@ -358,7 +359,7 @@ configure_emi_drive(int ma)
HW_PINCTRL_DRIVE14_BANK3_PIN17_MA |
HW_PINCTRL_DRIVE14_BANK3_PIN16_V | /* Pin 81, EMI_DQM0 */
HW_PINCTRL_DRIVE14_BANK3_PIN16_MA |
- HW_PINCTRL_DRIVE14_RSRVD6 | /* Always write zeroes */
+ HW_PINCTRL_DRIVE14_RSRVD6 | /* Always write zeroes */
HW_PINCTRL_DRIVE14_RSRVD5 |
HW_PINCTRL_DRIVE14_RSRVD4 |
HW_PINCTRL_DRIVE14_RSRVD3 |
@@ -374,7 +375,7 @@ configure_emi_drive(int ma)
__SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN17_MA) | /* EMI_DQM1 */
__SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN16_MA) /* EMI_DQM0 */
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14, drive);
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14, drive);
return;
}
@@ -382,11 +383,11 @@ configure_emi_drive(int ma)
/*
* Disable internal gate keepers on EMI pins.
*/
-void
+static void
disable_emi_padkeepers(void)
{
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_PULL3_SET, (
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL3_SET, (
HW_PINCTRL_PULL3_BANK3_PIN17 | /* EMI_DQM1 */
HW_PINCTRL_PULL3_BANK3_PIN16 | /* EMI_DQM0 */
HW_PINCTRL_PULL3_BANK3_PIN15 | /* EMI_D15 */
@@ -413,16 +414,16 @@ disable_emi_padkeepers(void)
/*
* Configure external SSP pins to be used for SD/MMC.
*/
-void
+static void
configure_ssp_mux(void)
{
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, (
- HW_PINCTRL_MUXSEL4_BANK2_PIN00 | /* Pin 121, SSP1_CMD */
- HW_PINCTRL_MUXSEL4_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */
- HW_PINCTRL_MUXSEL4_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */
- HW_PINCTRL_MUXSEL4_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */
- HW_PINCTRL_MUXSEL4_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */
- HW_PINCTRL_MUXSEL4_BANK2_PIN06) /* Pin 127, SSP1_SCK */
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, (
+ HW_PINCTRL_MUXSEL4_BANK2_PIN00 | /* Pin 121, SSP1_CMD */
+ HW_PINCTRL_MUXSEL4_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */
+ HW_PINCTRL_MUXSEL4_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */
+ HW_PINCTRL_MUXSEL4_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */
+ HW_PINCTRL_MUXSEL4_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */
+ HW_PINCTRL_MUXSEL4_BANK2_PIN06) /* Pin 127, SSP1_SCK */
);
return;
@@ -432,20 +433,20 @@ configure_ssp_mux(void)
* Configure SSP pins drive strength to "ma".
* Out of reset, all non-EMI pins are configured as 3.3 V.
*/
-void
+static void
configure_ssp_drive(int ma)
{
- uint32_t reg = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8);
- reg &= ~(
- HW_PINCTRL_DRIVE8_BANK2_PIN06_MA | /* Pin 127, SSP1_SCK */
- HW_PINCTRL_DRIVE8_BANK2_PIN05_MA | /* Pin 125, SSP1_DATA3 */
- HW_PINCTRL_DRIVE8_BANK2_PIN04_MA | /* Pin 124, SSP1_DATA2 */
- HW_PINCTRL_DRIVE8_BANK2_PIN03_MA | /* Pin 123, SSP1_DATA1 */
- HW_PINCTRL_DRIVE8_BANK2_PIN02_MA | /* Pin 122, SSP1_DATA0 */
- HW_PINCTRL_DRIVE8_BANK2_PIN00_MA /* Pin 121, SSP1_CMD */
+ uint32_t reg = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8);
+ reg &= ~(
+ HW_PINCTRL_DRIVE8_BANK2_PIN06_MA | /* Pin 127, SSP1_SCK */
+ HW_PINCTRL_DRIVE8_BANK2_PIN05_MA | /* Pin 125, SSP1_DATA3 */
+ HW_PINCTRL_DRIVE8_BANK2_PIN04_MA | /* Pin 124, SSP1_DATA2 */
+ HW_PINCTRL_DRIVE8_BANK2_PIN03_MA | /* Pin 123, SSP1_DATA1 */
+ HW_PINCTRL_DRIVE8_BANK2_PIN02_MA | /* Pin 122, SSP1_DATA0 */
+ HW_PINCTRL_DRIVE8_BANK2_PIN00_MA /* Pin 121, SSP1_CMD */
);
- reg |= __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN06_MA) |
+ reg |= __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN06_MA) |
__SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN05_MA) |
__SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN04_MA) |
__SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN03_MA) |
@@ -453,32 +454,32 @@ configure_ssp_drive(int ma)
__SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN00_MA
);
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8, reg);
-
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8, reg);
+
return;
}
/*
* Configure SSP pull ups.
*/
-void
+static void
configure_ssp_pullups(void)
{
/* Disable pull ups for SSP and let HW take care of them. */
-// REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR, (
-// HW_PINCTRL_PULL2_BANK2_PIN05 |/* Pin 125, SSP1_DATA3 */
-// HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */
-// HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */
-// HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */
-// HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */
+// REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR, (
+// HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */
+// HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */
+// HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */
+// HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */
+// HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */
// ));
- REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_SET, (
- HW_PINCTRL_PULL2_BANK2_PIN05 |/* Pin 125, SSP1_DATA3 */
- HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */
- HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */
- HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */
- HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */
+ REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_SET, (
+ HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */
+ HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */
+ HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */
+ HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */
+ HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */
));
return;
Index: src/sys/arch/evbarm/stand/bootimx23/bootimx23.bd
diff -u src/sys/arch/evbarm/stand/bootimx23/bootimx23.bd:1.2 src/sys/arch/evbarm/stand/bootimx23/bootimx23.bd:1.3
--- src/sys/arch/evbarm/stand/bootimx23/bootimx23.bd:1.2 Tue Nov 20 21:36:35 2012
+++ src/sys/arch/evbarm/stand/bootimx23/bootimx23.bd Sun Dec 16 19:08:44 2012
@@ -1,4 +1,4 @@
-/* $Id: bootimx23.bd,v 1.2 2012/11/20 21:36:35 jkunz Exp $ */
+/* $Id: bootimx23.bd,v 1.3 2012/12/16 19:08:44 jkunz Exp $ */
/*
* elftosb command file.
@@ -25,7 +25,7 @@ section (0) {
load boot_prep;
call boot_prep;
- // Load and start NetBSD kernel.
+ // Load kernel to DRAM.
load netbsd;
jump netbsd;
}
Index: src/sys/arch/evbarm/stand/bootimx23/power_prep.c
diff -u src/sys/arch/evbarm/stand/bootimx23/power_prep.c:1.2 src/sys/arch/evbarm/stand/bootimx23/power_prep.c:1.3
--- src/sys/arch/evbarm/stand/bootimx23/power_prep.c:1.2 Tue Nov 20 23:39:33 2012
+++ src/sys/arch/evbarm/stand/bootimx23/power_prep.c Sun Dec 16 19:08:45 2012
@@ -1,4 +1,4 @@
-/* $Id: power_prep.c,v 1.2 2012/11/20 23:39:33 jkunz Exp $ */
+/* $Id: power_prep.c,v 1.3 2012/12/16 19:08:45 jkunz Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,8 +30,8 @@
*/
#include <sys/param.h>
-#include <sys/cdefs.h>
#include <sys/types.h>
+#include <sys/cdefs.h>
#include <arm/imx/imx23_powerreg.h>
@@ -39,542 +39,221 @@
#include "common.h"
-void charge_4p2_capacitance(void);
-void enable_4p2_linreg(void);
-void enable_dcdc(void);
-void enable_vbusvalid_comparator(void);
-void set_targets(void);
-void dcdc4p2_enable_dcdc(void);
-void p5vctrl_enable_dcdc(void);
-void enable_vddmem(void);
-
-/*
- * Power rail voltage targets, brownout levels and linear regulator
- * offsets from the target.
- *
- * Supply Target BO LinReg offset
- * ------------------------------------------
- * VDDD 1.550 V 1.450 V -25 mV
- * VDDA 1.750 V 1.575 V -25 mV
- * VDDIO 3.100 V 2.925 V -25 mV
- * VDDMEM 2.500 V <na> <na>
- *
- * BO = Brownout level below target.
- */
-#define VDDD_TARGET 0x1e
-#define VDDD_BO_OFFSET 0x4
-#define VDDD_LINREG_OFFSET 0x02
-
-#define VDDA_TARGET 0x0A
-#define VDDA_BO_OFFSET 0x07
-#define VDDA_LINREG_OFFSET 0x02
-
-#define VDDIO_TARGET 0x0C
-#define VDDIO_BO_OFFSET 0x07
-#define VDDIO_LINREG_OFFSET 0x02
-
-#define VDDMEM_TARGET 0x10
-
-/*
- * Threshold voltage for the VBUSVALID comparator.
- * Always make sure that the VDD5V voltage level is higher.
- */
-#define VBUSVALID_TRSH 0x02 /* 4.1 V */
-
-/* Limits for BATT charger + 4P2 current */
-#define P4P2_ILIMIT_MIN 0x01 /* 10 mA */
-#define P4P2_ILIMIT_MAX 0x3f /* 780 mA */
+static void set_vddd_target(uint8_t);
+static void set_vdda_target(uint8_t);
+static void set_vddio_target(uint8_t);
+static void set_vddmem_target(uint8_t);
+#ifdef DEBUG
+static void print_regs(void);
+#endif
+
+#define VDDD_TARGET 0x1e /* 1550 mV */
+#define VDDA_TARGET 0x0a /* 1750 mV */
+#define VDDIO_TARGET 0x0c /* 3100 mV */
+#define VDDMEM_TARGET 0x10 /* 2500 mV */
-/*
- * Trip point for the comparison between the DCDC_4P2 and BATTERY pin.
- * If this voltage comparation is true then 5 V originated power will supply
- * the DCDC. Otherwise battery will be used.
- */
-#define DCDC4P2_CMPTRIP 0x00 /* DCDC_4P2 pin > 0.85 * BATTERY pin */
+static int five_volts = 0;
/*
- * Adjust the behavior of the DCDC and 4.2 V circuit.
- * Two MSBs control the VDD4P2 brownout below the DCDC4P2_TRG before the
- * regulation circuit steals battery charge. Two LSBs control which power
- * source is selected by the DCDC.
- */
-#define DCDC4P2_DROPOUT_CTRL_BO_200 0x0C
-#define DCDC4P2_DROPOUT_CTRL_BO_100 0x08
-#define DCDC4P2_DROPOUT_CTRL_BO_050 0x04
-#define DCDC4P2_DROPOUT_CTRL_BO_025 0x00
-
-#define DCDC4P2_DROPOUT_CTRL_SEL_4P2 0x00 /* Don't use battery at all. */
-#define DCDC4P2_DROPOUT_CTRL_SEL_BATT_IF_GT_4P2 0x01 /* BATT if 4P2 < BATT */
-#define DCDC4P2_DROPOUT_CTRL_SEL_HIGHER 0x02 /* Selects which ever is
- * higher. */
-
-#define DCDC4P2_DROPOUT_CTRL (DCDC4P2_DROPOUT_CTRL_BO_200 |\
- DCDC4P2_DROPOUT_CTRL_SEL_4P2)
-
-/*
- * Prepare system for a 5 V operation.
+ * If 5V is present, all power rails are powered from the LinRegs.
*
- * The system uses inefficient linear regulators as a power source after boot.
- * This code enables the use of more energy efficient DC-DC converter as a
- * power source.
+ * If powered from the battery, the DC-DC converter starts when battery power
+ * is detected and the PSWITCH button is pressed. In this state, the VDDA and
+ * VDDIO rails are powered on from DC-DC, but the VDDD rail is powered from its
+ * LinReg.
*/
int
power_prep(void)
{
-
- /* Enable clocks to the power block */
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, HW_POWER_CTRL_CLKGATE);
-
- set_targets();
- enable_vbusvalid_comparator();
- enable_4p2_linreg();
- charge_4p2_capacitance();
- enable_dcdc();
- enable_vddmem();
-
+ if (REG_RD(HW_POWER_BASE + HW_POWER_STS) & HW_POWER_STS_VDD5V_GT_VDDIO)
+ five_volts = 1;
+#ifdef DEBUG
+ if (five_volts)
+ printf("Powered from 5V\n\r");
+ else
+ printf("Powered from the battery.\n\r");
+ print_regs();
+#endif
+ set_vddd_target(VDDD_TARGET);
+ set_vdda_target(VDDA_TARGET);
+ set_vddio_target(VDDIO_TARGET);
+ set_vddmem_target(VDDMEM_TARGET);
+#ifdef DEBUG
+ print_regs();
+#endif
return 0;
}
/*
- * Set switching converter voltage targets, brownout levels and linear
- * regulator output offsets.
+ * Set VDDD target voltage.
*/
-void
-set_targets(void)
+static void
+set_vddd_target(uint8_t target)
{
- uint32_t vddctrl;
-
- /* VDDD */
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDDCTRL);
-
- vddctrl &= ~(HW_POWER_VDDDCTRL_LINREG_OFFSET |
- HW_POWER_VDDDCTRL_BO_OFFSET |
- HW_POWER_VDDDCTRL_TRG);
- vddctrl |=
- __SHIFTIN(VDDD_LINREG_OFFSET, HW_POWER_VDDDCTRL_LINREG_OFFSET) |
- __SHIFTIN(VDDD_BO_OFFSET, HW_POWER_VDDDCTRL_BO_OFFSET) |
- __SHIFTIN(VDDD_TARGET, HW_POWER_VDDDCTRL_TRG);
-
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDDCTRL, vddctrl);
-
- /* VDDA */
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDACTRL);
-
- vddctrl &= ~(HW_POWER_VDDACTRL_LINREG_OFFSET |
- HW_POWER_VDDACTRL_BO_OFFSET |
- HW_POWER_VDDACTRL_TRG);
- vddctrl |=
- __SHIFTIN(VDDA_LINREG_OFFSET, HW_POWER_VDDACTRL_LINREG_OFFSET) |
- __SHIFTIN(VDDA_BO_OFFSET, HW_POWER_VDDACTRL_BO_OFFSET) |
- __SHIFTIN(VDDA_TARGET, HW_POWER_VDDACTRL_TRG);
-
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDACTRL, vddctrl);
-
- /* VDDIO */
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDIOCTRL);
-
- vddctrl &= ~(HW_POWER_VDDIOCTRL_LINREG_OFFSET |
- HW_POWER_VDDIOCTRL_BO_OFFSET |
- HW_POWER_VDDIOCTRL_TRG);
- vddctrl |=
- __SHIFTIN(VDDIO_LINREG_OFFSET, HW_POWER_VDDACTRL_LINREG_OFFSET) |
- __SHIFTIN(VDDIO_BO_OFFSET, HW_POWER_VDDACTRL_BO_OFFSET) |
- __SHIFTIN(VDDIO_TARGET, HW_POWER_VDDACTRL_TRG);
-
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDIOCTRL, vddctrl);
-
- /* VDDMEM */
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDMEMCTRL);
- vddctrl &= ~(HW_POWER_VDDMEMCTRL_TRG);
- vddctrl |= __SHIFTIN(VDDMEM_TARGET, HW_POWER_VDDMEMCTRL_TRG);
-
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddctrl);
-
- return;
-}
-
-/*
- * VBUSVALID comparator is accurate method to determine the presence of 5 V.
- * Turn on the comparator, set its voltage treshold and instruct DC-DC to
- * use it.
- */
-void
-enable_vbusvalid_comparator()
-{
- uint32_t p5vctrl;
+ uint32_t vddd;
+ uint8_t curtrg;
+ vddd = REG_RD(HW_POWER_BASE + HW_POWER_VDDDCTRL);
+
/*
- * Disable 5 V brownout detection temporarily because setting
- * VBUSVALID_5VDETECT can cause false brownout.
+ * VDDD is always powered from the linear regulator.
+ *
+ * Setting LINREG_OFFSET to 0 is recommended when powering VDDD from
+ * the linear regulator. It is also recommended to set DISABLE_STEPPING
+ * when powering VDDD from the linear regulators.
*/
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR,
- HW_POWER_5VCTRL_PWDN_5VBRNOUT);
+ vddd &= ~(HW_POWER_VDDDCTRL_LINREG_OFFSET);
+ vddd |= HW_POWER_VDDDCTRL_DISABLE_STEPPING;
- p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDDCTRL, vddd);
+ delay(1000);
- p5vctrl &= ~HW_POWER_5VCTRL_VBUSVALID_TRSH;
- p5vctrl |=
- /* Turn on VBUS comparators. */
- (HW_POWER_5VCTRL_PWRUP_VBUS_CMPS |
- /* Set treshold for VBUSVALID comparator. */
- __SHIFTIN(VBUSVALID_TRSH, HW_POWER_5VCTRL_VBUSVALID_TRSH) |
- /* Set DC-DC to use VBUSVALID comparator. */
- HW_POWER_5VCTRL_VBUSVALID_5VDETECT);
-
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl);
-
- /* Enable temporarily disabled 5 V brownout detection. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET,
- HW_POWER_5VCTRL_PWDN_5VBRNOUT);
+ curtrg = __SHIFTOUT(vddd, HW_POWER_VDDDCTRL_TRG);
- return;
-}
-
-/*
- * Enable 4P2 linear regulator.
- */
-void
-enable_4p2_linreg(void)
-{
- uint32_t dcdc4p2;
- uint32_t p5vctrl;
-
- dcdc4p2 = REG_READ(HW_POWER_BASE + HW_POWER_DCDC4P2);
- /* Set the 4P2 target to 4.2 V and BO to 3.6V by clearing TRG and BO
- * field. */
- dcdc4p2 &= ~(HW_POWER_DCDC4P2_TRG | HW_POWER_DCDC4P2_BO);
- /* Enable the 4P2 circuitry to control the LinReg. */
- dcdc4p2 |= HW_POWER_DCDC4P2_ENABLE_4P2;
- REG_WRITE(HW_POWER_BASE + HW_POWER_DCDC4P2, dcdc4p2);
-
- /* The 4P2 LinReg needs a static load to operate correctly. Since the
- * DC-DC is not yet loading the LinReg, another load must be used. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_CHARGE_SET,
- HW_POWER_CHARGE_ENABLE_LOAD);
-
- p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL);
- p5vctrl &= ~(HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT |
- /* Power on the 4P2 LinReg. ON = 0x0, OFF = 0x1 */
- HW_POWER_5VCTRL_PWD_CHARGE_4P2);
- p5vctrl |=
- /* Provide an initial current limit for the 4P2 LinReg with the
- * smallest value possible. */
- __SHIFTIN(P4P2_ILIMIT_MIN, HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl);
-
- /* Ungate the path from 4P2 LinReg to DC-DC. */
- dcdc4p2_enable_dcdc();
+ /* Because HW stepping is disabled, raise voltage to target slowly. */
+ for (curtrg++; curtrg <= target; curtrg++) {
+ vddd = REG_RD(HW_POWER_BASE + HW_POWER_VDDDCTRL);
+ vddd &= ~(HW_POWER_VDDDCTRL_TRG);
+ vddd |= __SHIFTIN(curtrg, HW_POWER_VDDDCTRL_TRG);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDDCTRL, vddd);
+ delay(1000);
+ }
return;
}
-/*
- * There is capacitor on the 4P2 output which must be charged before powering
- * on the 4P2 linear regulator to avoid brownouts on the 5 V source.
- * Charging is done by slowly increasing current limit until it reaches
- * P4P2_ILIMIT_MAX.
- */
-void
-charge_4p2_capacitance(void)
+static void
+set_vdda_target(uint8_t target)
{
- uint32_t ilimit;
- uint32_t p5vctrl;
+ uint32_t vdda;
+ uint8_t curtrg;
- p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL);
- ilimit = __SHIFTOUT(p5vctrl, HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
+ vdda = REG_RD(HW_POWER_BASE + HW_POWER_VDDACTRL);
- /* Increment current limit slowly. */
- while (ilimit < P4P2_ILIMIT_MAX) {
- ilimit++;
- p5vctrl &= ~(HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
- p5vctrl |= __SHIFTIN(ilimit, HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl);
- delay_us(10000);
+ /*
+ * Setting LINREG_OFFSET to 0 is recommended when powering VDDA from
+ * the linear regulator. It is also recommended to set DISABLE_STEPPING
+ * when powering VDDA from the linear regulators.
+ */
+ if (five_volts) {
+ vdda &= ~(HW_POWER_VDDACTRL_LINREG_OFFSET);
+ vdda |= HW_POWER_VDDACTRL_DISABLE_STEPPING;
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDACTRL, vdda);
+ delay(1000);
+
+ curtrg = __SHIFTOUT(vdda, HW_POWER_VDDACTRL_TRG);
+
+ /*
+ * Because HW stepping is disabled, raise voltage to target
+ * slowly.
+ */
+ for (curtrg++; curtrg <= target; curtrg++) {
+ vdda = REG_RD(HW_POWER_BASE + HW_POWER_VDDACTRL);
+ vdda &= ~(HW_POWER_VDDACTRL_TRG);
+ vdda |= __SHIFTIN(curtrg, HW_POWER_VDDACTRL_TRG);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDACTRL, vdda);
+ delay(1000);
+ }
+ } else {
+ vdda |= __SHIFTIN(target, HW_POWER_VDDACTRL_TRG);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDACTRL, vdda);
}
return;
}
-/*
- * Enable DCDC to use 4P2 regulator and set its power source selection logic.
- */
-void
-enable_dcdc(void)
+static void
+set_vddio_target(uint8_t target)
{
- uint32_t dcdc4p2;
- uint32_t vddctrl;
+ uint32_t vddio;
+ uint8_t curtrg;
- dcdc4p2 = REG_READ(HW_POWER_BASE + HW_POWER_DCDC4P2);
- dcdc4p2 &= ~(HW_POWER_DCDC4P2_CMPTRIP | HW_POWER_DCDC4P2_DROPOUT_CTRL);
- /* Comparison between the DCDC_4P2 pin and BATTERY pin to choose which
- * will supply the DCDC. */
- dcdc4p2 |= __SHIFTIN(DCDC4P2_CMPTRIP, HW_POWER_DCDC4P2_CMPTRIP);
- /* DC-DC brownout and select logic. */
- dcdc4p2 |= __SHIFTIN(DCDC4P2_DROPOUT_CTRL,
- HW_POWER_DCDC4P2_DROPOUT_CTRL);
- REG_WRITE(HW_POWER_BASE + HW_POWER_DCDC4P2, dcdc4p2);
-
- /* Disable the automatic DC-DC startup when 5 V is lost (it is on
- * already) */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR,
- HW_POWER_5VCTRL_DCDC_XFER);
-
- p5vctrl_enable_dcdc();
-
- /* Enable switching converter outputs and disable linear regulators
- * for VDDD, VDDIO and VDDA. */
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDDCTRL);
- vddctrl &= ~(HW_POWER_VDDDCTRL_DISABLE_FET |
- HW_POWER_VDDDCTRL_ENABLE_LINREG);
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDDCTRL, vddctrl);
-
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDIOCTRL);
- vddctrl &= ~HW_POWER_VDDIOCTRL_DISABLE_FET;
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDIOCTRL, vddctrl);
-
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDACTRL);
- vddctrl &= ~(HW_POWER_VDDACTRL_DISABLE_FET |
- HW_POWER_VDDACTRL_ENABLE_LINREG);
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDACTRL, vddctrl);
-
- /* The 4P2 LinReg needs a static load to operate correctly. Since the
- * DC-DC is already running we can remove extra 100 ohm load enabled
- * before. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_CHARGE_CLR,
- HW_POWER_CHARGE_ENABLE_LOAD);
+ vddio = REG_RD(HW_POWER_BASE + HW_POWER_VDDIOCTRL);
- return;
-}
-
-/*
- * DCDC4P2 DCDC enable sequence according to errata #5837
- */
-void
-dcdc4p2_enable_dcdc(void)
-{
- uint32_t dcdc4p2;
- uint32_t p5vctrl;
- uint32_t p5vctrl_saved;
- uint32_t pctrl;
- uint32_t pctrl_saved;
-
- pctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_CTRL);
- p5vctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL);
-
- /* Disable the power rail brownout interrupts. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- (HW_POWER_CTRL_ENIRQ_VDDA_BO |
- HW_POWER_CTRL_ENIRQ_VDDD_BO |
- HW_POWER_CTRL_ENIRQ_VDDIO_BO));
-
- /* Set the HW_POWER_5VCTRL PWRUP_VBUS_CMPS bit (may already be set) */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET,
- HW_POWER_5VCTRL_PWRUP_VBUS_CMPS);
-
- /* Set the HW_POWER_5VCTRL VBUSVALID_5VDETECT bit to 0 */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR,
- HW_POWER_5VCTRL_VBUSVALID_5VDETECT);
-
- /* Set the HW_POWER_5VCTRL VBUSVALID_TRSH to 0x0 (2.9 V) */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR,
- HW_POWER_5VCTRL_VBUSVALID_TRSH);
-
- /* Disable VBUSDROOP status and interrupt. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- (HW_POWER_CTRL_VDD5V_DROOP_IRQ | HW_POWER_CTRL_ENIRQ_VDD5V_DROOP));
-
- /* Set the ENABLE_DCDC bit in HW_POWER_DCDC4P2. */
- dcdc4p2 = REG_READ(HW_POWER_BASE + HW_POWER_DCDC4P2);
- dcdc4p2 |= HW_POWER_DCDC4P2_ENABLE_DCDC;
- REG_WRITE(HW_POWER_BASE + HW_POWER_DCDC4P2, dcdc4p2);
-
- delay_us(100);
-
- pctrl = REG_READ(HW_POWER_BASE + HW_POWER_CTRL);
- /* VBUSVALID_IRQ is set. */
- if (__SHIFTOUT(pctrl, HW_POWER_CTRL_VBUSVALID_IRQ)) {
- /* Set and clear the PWD_CHARGE_4P2 bit to repower on the 4P2
- * regulator because it is automatically shut off on a
- * VBUSVALID false condition. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET,
- HW_POWER_5VCTRL_PWD_CHARGE_4P2);
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR,
- HW_POWER_5VCTRL_PWD_CHARGE_4P2);
- /* Ramp up the CHARGE_4P2_ILIMIT value at this point. */
- charge_4p2_capacitance();
+ /*
+ * Setting LINREG_OFFSET to 0 is recommended when powering VDDIO from
+ * the linear regulator. It is also recommended to set DISABLE_STEPPING
+ * when powering VDDIO from the linear regulators.
+ */
+ if (five_volts) {
+ vddio &= ~(HW_POWER_VDDIOCTRL_LINREG_OFFSET);
+ vddio |= HW_POWER_VDDIOCTRL_DISABLE_STEPPING;
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDIOCTRL, vddio);
+ delay(1000);
+
+ curtrg = __SHIFTOUT(vddio, HW_POWER_VDDIOCTRL_TRG);
+
+ /*
+ * Because HW stepping is disabled, raise voltage to target
+ * slowly.
+ */
+ for (curtrg++; curtrg <= target; curtrg++) {
+ vddio = REG_RD(HW_POWER_BASE + HW_POWER_VDDIOCTRL);
+ vddio &= ~(HW_POWER_VDDIOCTRL_TRG);
+ vddio |= __SHIFTIN(curtrg, HW_POWER_VDDIOCTRL_TRG);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDIOCTRL, vddio);
+ delay(1000);
+ }
+ } else {
+ vddio |= __SHIFTIN(target, HW_POWER_VDDIOCTRL_TRG);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDIOCTRL, vddio);
}
- /* Restore modified bits back to HW_POWER_CTRL. */
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDA_BO)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDDA_BO);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDDA_BO);
-
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDD_BO)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDDD_BO);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDDD_BO);
-
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDIO_BO)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDDIO_BO);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDDIO_BO);
-
- if (pctrl_saved & HW_POWER_CTRL_VDD5V_DROOP_IRQ)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_VDD5V_DROOP_IRQ);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_VDD5V_DROOP_IRQ);
-
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDD5V_DROOP)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDD5V_DROOP);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDD5V_DROOP);
-
- /* Restore modified bits back to HW_POWER_5VCTRL. */
- p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL);
- p5vctrl &= ~(HW_POWER_5VCTRL_PWRUP_VBUS_CMPS |
- HW_POWER_5VCTRL_VBUSVALID_5VDETECT |
- HW_POWER_5VCTRL_VBUSVALID_TRSH);
- p5vctrl |= __SHIFTOUT(p5vctrl_saved, HW_POWER_5VCTRL_VBUSVALID_TRSH) |
- (p5vctrl_saved & HW_POWER_5VCTRL_PWRUP_VBUS_CMPS) |
- (p5vctrl_saved & HW_POWER_5VCTRL_VBUSVALID_5VDETECT);
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl);
-
return;
}
-/*
- * 5VCTRL DCDC enable sequence according to errata #5837
- */
-void
-p5vctrl_enable_dcdc(void)
+static void
+set_vddmem_target(uint8_t target)
{
- uint32_t p5vctrl;
- uint32_t p5vctrl_saved;
- uint32_t pctrl;
- uint32_t pctrl_saved;
-
- pctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_CTRL);
- p5vctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL);
-
- /* Disable the power rail brownout interrupts. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDDA_BO |
- HW_POWER_CTRL_ENIRQ_VDDD_BO |
- HW_POWER_CTRL_ENIRQ_VDDIO_BO);
-
- /* Set the HW_POWER_5VCTRL PWRUP_VBUS_CMPS bit (may already be set) */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET,
- HW_POWER_5VCTRL_PWRUP_VBUS_CMPS);
-
- /* Set the HW_POWER_5VCTRL VBUSVALID_5VDETECT bit to 1 */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET,
- HW_POWER_5VCTRL_VBUSVALID_5VDETECT);
-
- /* Set the HW_POWER_5VCTRL VBUSVALID_TRSH to 0x0 (2.9 V) */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR,
- HW_POWER_5VCTRL_VBUSVALID_TRSH);
-
- /* Disable VBUSDROOP status and interrupt. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- (HW_POWER_CTRL_VDD5V_DROOP_IRQ | HW_POWER_CTRL_ENIRQ_VDD5V_DROOP));
-
- /* Work over errata #2816 by disabling 5 V brownout while modifying
- * ENABLE_DCDC. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR,
- HW_POWER_5VCTRL_PWDN_5VBRNOUT);
-
- /* Set the ENABLE_DCDC bit in HW_POWER_5VCTRL. */
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET,
- HW_POWER_5VCTRL_ENABLE_DCDC);
-
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET,
- HW_POWER_5VCTRL_PWDN_5VBRNOUT);
-
- delay_us(100);
-
- pctrl = REG_READ(HW_POWER_BASE + HW_POWER_CTRL);
- /* VBUSVALID_IRQ is set. */
- if (__SHIFTOUT(pctrl, HW_POWER_CTRL_VBUSVALID_IRQ)) {
- /* repeat the sequence for enabling the 4P2 regulator and DCDC
- * from 4P2. */
- enable_4p2_linreg();
- }
- /* Restore modified bits back to HW_POWER_CTRL. */
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDA_BO)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDDA_BO);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDDA_BO);
+ uint32_t vddmem;
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDD_BO)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDDD_BO);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDDD_BO);
-
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDIO_BO)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDDIO_BO);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDDIO_BO);
-
- if (pctrl_saved & HW_POWER_CTRL_VDD5V_DROOP_IRQ)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_VDD5V_DROOP_IRQ);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_VDD5V_DROOP_IRQ);
-
- if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDD5V_DROOP)
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET,
- HW_POWER_CTRL_ENIRQ_VDD5V_DROOP);
- else
- REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR,
- HW_POWER_CTRL_ENIRQ_VDD5V_DROOP);
-
- /* Restore modified bits back to HW_POWER_5VCTRL. */
- p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL);
- p5vctrl &= ~(HW_POWER_5VCTRL_PWRUP_VBUS_CMPS |
- HW_POWER_5VCTRL_VBUSVALID_5VDETECT |
- HW_POWER_5VCTRL_VBUSVALID_TRSH);
- p5vctrl |= __SHIFTOUT(p5vctrl_saved, HW_POWER_5VCTRL_VBUSVALID_TRSH) |
- (p5vctrl_saved & HW_POWER_5VCTRL_PWRUP_VBUS_CMPS) |
- (p5vctrl_saved & HW_POWER_5VCTRL_VBUSVALID_5VDETECT);
- REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl);
+ /* Set target. */
+ vddmem = REG_RD(HW_POWER_BASE + HW_POWER_VDDMEMCTRL);
+ vddmem &= ~(HW_POWER_VDDMEMCTRL_TRG);
+ vddmem |= __SHIFTIN(target, HW_POWER_VDDMEMCTRL_TRG);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddmem);
+ delay(1000);
+
+ /* Enable VDDMEM */
+ vddmem = REG_RD(HW_POWER_BASE + HW_POWER_VDDMEMCTRL);
+ vddmem |= (HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE |
+ HW_POWER_VDDMEMCTRL_ENABLE_ILIMIT |
+ HW_POWER_VDDMEMCTRL_ENABLE_LINREG);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddmem);
+ delay(500);
+ vddmem &= ~(HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE |
+ HW_POWER_VDDMEMCTRL_ENABLE_ILIMIT);
+ REG_WR(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddmem);
return;
}
+#ifdef DEBUG
+#define PRINT_REG(REG) \
+ printf(#REG "\t%x\n\r", REG_RD(HW_POWER_BASE + REG));
-void
-enable_vddmem(void)
+static void
+print_regs(void)
{
- uint32_t vddctrl;
-
- /* VDDMEM */
- vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDMEMCTRL);
- vddctrl |= (HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE |
- HW_POWER_VDDMEMCTRL_ENABLE_ILIMIT |
- HW_POWER_VDDMEMCTRL_ENABLE_LINREG);
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddctrl);
- delay_us(500);
- vddctrl &= ~(HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE |
- HW_POWER_VDDMEMCTRL_ENABLE_ILIMIT);
- REG_WRITE(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddctrl);
- delay_us(10000);
+ PRINT_REG(HW_POWER_CTRL);
+ PRINT_REG(HW_POWER_5VCTRL);
+ PRINT_REG(HW_POWER_MINPWR);
+ PRINT_REG(HW_POWER_CHARGE);
+ PRINT_REG(HW_POWER_VDDDCTRL);
+ PRINT_REG(HW_POWER_VDDACTRL);
+ PRINT_REG(HW_POWER_VDDIOCTRL);
+ PRINT_REG(HW_POWER_VDDMEMCTRL);
+ PRINT_REG(HW_POWER_DCDC4P2);
+ PRINT_REG(HW_POWER_MISC);
+ PRINT_REG(HW_POWER_DCLIMITS);
+ PRINT_REG(HW_POWER_LOOPCTRL);
+ PRINT_REG(HW_POWER_STS);
+ PRINT_REG(HW_POWER_SPEED);
+ PRINT_REG(HW_POWER_BATTMONITOR);
+ PRINT_REG(HW_POWER_RESET);
+ PRINT_REG(HW_POWER_DEBUG);
+ PRINT_REG(HW_POWER_SPECIAL);
+ PRINT_REG(HW_POWER_VERSION);
return;
}
+#endif
