Module Name: src
Committed By: msaitoh
Date: Fri Dec 28 03:48:00 UTC 2012
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
Enable DCache Streaming Switch and Write Allocate.
This change improve system performance significantly.
To generate a diff of this commit:
cvs rdiff -u -r1.118 -r1.119 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.118 src/sys/arch/arm/arm/cpufunc.c:1.119
--- src/sys/arch/arm/arm/cpufunc.c:1.118 Mon Nov 12 18:00:34 2012
+++ src/sys/arch/arm/arm/cpufunc.c Fri Dec 28 03:48:00 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.118 2012/11/12 18:00:34 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.119 2012/12/28 03:48:00 msaitoh Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.118 2012/11/12 18:00:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.119 2012/12/28 03:48:00 msaitoh Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -3352,6 +3352,7 @@ void
sheeva_setup(char *args)
{
int cpuctrl, cpuctrlmask;
+ uint32_t sheeva_ext;
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@@ -3369,6 +3370,15 @@ sheeva_setup(char *args)
cpuctrl = parse_cpu_options(args, sheeva_options, cpuctrl);
+ /* Enable DCache Streaming Switch and Write Allocate */
+ __asm volatile("mrc p15, 1, %0, c15, c1, 0"
+ : "=r" (sheeva_ext));
+
+ sheeva_ext |= FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN;
+
+ __asm volatile("mcr p15, 1, %0, c15, c1, 0"
+ :: "r" (sheeva_ext));
+
/*
* Sheeva has L2 Cache. Enable/Disable it here.
* Really not support yet...
