Module Name: src
Committed By: skrll
Date: Fri Apr 19 05:36:16 UTC 2013
Modified Files:
src/common/lib/libc/arch/arm/quad: __aeabi_ldivmod.S
Log Message:
Fix logic inversion.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/arm/quad/__aeabi_ldivmod.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/quad/__aeabi_ldivmod.S
diff -u src/common/lib/libc/arch/arm/quad/__aeabi_ldivmod.S:1.2 src/common/lib/libc/arch/arm/quad/__aeabi_ldivmod.S:1.3
--- src/common/lib/libc/arch/arm/quad/__aeabi_ldivmod.S:1.2 Sun Apr 14 15:53:30 2013
+++ src/common/lib/libc/arch/arm/quad/__aeabi_ldivmod.S Fri Apr 19 05:36:16 2013
@@ -29,7 +29,7 @@
#include <machine/asm.h>
-RCSID("$NetBSD: __aeabi_ldivmod.S,v 1.2 2013/04/14 15:53:30 matt Exp $")
+RCSID("$NetBSD: __aeabi_ldivmod.S,v 1.3 2013/04/19 05:36:16 skrll Exp $")
ENTRY(__aeabi_ldivmod)
push {r4-r5, sl, lr}
@@ -80,9 +80,9 @@ ENTRY(__aeabi_ldivmod)
pop {r2, r3}
tst NEG, #2 /* does remainder need to be negative? */
- bleq .Lnegate_b
+ blne .Lnegate_b
tst NEG, #1 /* does quotient need to be negative? */
- bleq .Lnegate_a
+ blne .Lnegate_a
pop {r4-r5, sl, lr}
RET
