Module Name:    src
Committed By:   macallan
Date:           Tue May 14 09:16:59 UTC 2013

Modified Files:
        src/sys/arch/evbmips/evbmips: interrupt.c

Log Message:
always set up a clockframe and make it available to other drivers, so clocks
other than the MIPS cycle counter can be used ( for example pwmclock )


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/evbmips/evbmips/interrupt.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/evbmips/interrupt.c
diff -u src/sys/arch/evbmips/evbmips/interrupt.c:1.18 src/sys/arch/evbmips/evbmips/interrupt.c:1.19
--- src/sys/arch/evbmips/evbmips/interrupt.c:1.18	Tue Sep 27 01:02:33 2011
+++ src/sys/arch/evbmips/evbmips/interrupt.c	Tue May 14 09:16:59 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: interrupt.c,v 1.18 2011/09/27 01:02:33 jym Exp $	*/
+/*	$NetBSD: interrupt.c,v 1.19 2013/05/14 09:16:59 macallan Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.18 2011/09/27 01:02:33 jym Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.19 2013/05/14 09:16:59 macallan Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -40,6 +40,8 @@ __KERNEL_RCSID(0, "$NetBSD: interrupt.c,
 #include <mips/locore.h>
 #include <mips/mips3_clock.h>
 
+struct clockframe cf;
+
 void
 intr_init(void)
 {
@@ -69,15 +71,15 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
 		    "%s: cpl (%d) != ipl (%d)", __func__, ci->ci_cpl, ipl);
 		KASSERT(pending != 0);
 
+		cf.pc = pc;
+		cf.sr = status;
+		cf.intr = (ci->ci_idepth > 1);
+
 		if (pending & MIPS_INT_MASK_5) {
-			struct clockframe cf;
 			KASSERTMSG(ipl == IPL_SCHED,
 			    "%s: ipl (%d) != IPL_SCHED (%d)",
 			     __func__, ipl, IPL_SCHED);
 			/* call the common MIPS3 clock interrupt handler */ 
-			cf.pc = pc;
-			cf.sr = status;
-			cf.intr = (ci->ci_idepth > 1);
 			mips3_clockintr(&cf);
 			pending ^= MIPS_INT_MASK_5;
 		}

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