Module Name:    src
Committed By:   msaitoh
Date:           Sat Sep 14 17:21:19 UTC 2013

Modified Files:
        src/sys/arch/x86/include: cacheinfo.h

Log Message:
Add Shared L2 TLB and some cache and tlb entries from the latest document.


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.15 src/sys/arch/x86/include/cacheinfo.h:1.16
--- src/sys/arch/x86/include/cacheinfo.h:1.15	Wed Jul 17 15:26:38 2013
+++ src/sys/arch/x86/include/cacheinfo.h	Sat Sep 14 17:21:19 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: cacheinfo.h,v 1.15 2013/07/17 15:26:38 msaitoh Exp $	*/
+/*	$NetBSD: cacheinfo.h,v 1.16 2013/09/14 17:21:19 msaitoh Exp $	*/
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -30,8 +30,10 @@ struct x86_cache_info {
 #define CAI_L2_ITLB2	13		/* L2 Instruction TLB (2/4M pages) */
 #define CAI_L2_DTLB	14		/* L2 Data TLB (4K pages) */
 #define CAI_L2_DTLB2	15		/* L2 Data TLB (2/4M pages) */
+#define CAI_L2_STLB	16		/* Shared L2 TLB (4K pages) */
+#define CAI_L2_STLB2	17		/* Shared L2 TLB (4K/2M pages) */
 
-#define	CAI_COUNT	16
+#define	CAI_COUNT	18
 
 /*
  * AMD Cache Info:
@@ -209,13 +211,12 @@ struct x86_cache_info {
  */
 #define INTEL_CACHE_INFO { \
 __CI_TBL(CAI_ITLB,     0x01,    4, 32,        4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB,     0xb0,    4,128,        4 * 1024, NULL), \
 __CI_TBL(CAI_ITLB2,    0x02, 0xff,  2, 4 * 1024 * 1024, NULL), \
 __CI_TBL(CAI_DTLB,     0x03,    4, 64,        4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB,     0xb3,    4,128,        4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB,     0xb4,    4,256,        4 * 1024, NULL), \
 __CI_TBL(CAI_DTLB2,    0x04,    4,  8, 4 * 1024 * 1024, NULL), \
 __CI_TBL(CAI_DTLB2,    0x05,    4, 32, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2,    0x0b,    4,  4, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB,     0x4f, 0xff, 32,        4 * 1024, NULL), \
 __CI_TBL(CAI_ITLB,     0x50, 0xff, 64,        4 * 1024, "4K/4M: 64 entries"), \
 __CI_TBL(CAI_ITLB,     0x51, 0xff, 64,        4 * 1024, "4K/4M: 128 entries"),\
 __CI_TBL(CAI_ITLB,     0x52, 0xff, 64,        4 * 1024, "4K/4M: 256 entries"),\
@@ -227,17 +228,36 @@ __CI_TBL(CAI_DTLB,     0x5a, 0xff, 64,  
 __CI_TBL(CAI_DTLB,     0x5b, 0xff, 64,        4 * 1024, "4K/4M: 64 entries"), \
 __CI_TBL(CAI_DTLB,     0x5c, 0xff, 64,        4 * 1024, "4K/4M: 128 entries"),\
 __CI_TBL(CAI_DTLB,     0x5d, 0xff, 64,        4 * 1024, "4K/4M: 256 entries"),\
+__CI_TBL(CAI_ITLB,     0x61, 0xff, 48,        4 * 1024, NULL), \
+__CI_TBL(CAI_L1_1GBDTLB,0x63,   4,  4,1024*1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2,    0x76, 0xff,  8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
+__CI_TBL(CAI_ITLB,     0xb0,    4,128,        4 * 1024, NULL), \
 __CI_TBL(CAI_ITLB,     0xb1,    4, 64,               0, "8 2M/4 4M entries"), \
 __CI_TBL(CAI_ITLB,     0xb2,    4, 64,        4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB,     0xb3,    4,128,        4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB,     0xb4,    4,256,        4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB,     0xb5,    8, 64,        4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB,     0xb6,    8,128,        4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB,     0xba,    4, 64,        4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB,     0xc0,    4,  8,        4 * 1024, "4K/4M: 8 entries"), \
+__CI_TBL(CAI_L2_STLB2, 0xc1,    8,1024,       4 * 1024, "4K/2M: 1024 entries"), \
+__CI_TBL(CAI_DTLB,     0xc2,    4, 16,        4 * 1024, "2M/4M: 16 entries"), \
+__CI_TBL(CAI_L2_STLB,  0xca,    4,512,        4 * 1024, "4K/4M: 512 entries"), \
 __CI_TBL(CAI_ICACHE,   0x06,    4,        8 * 1024, 32, NULL), \
 __CI_TBL(CAI_ICACHE,   0x08,    4,       16 * 1024, 32, NULL), \
 __CI_TBL(CAI_ICACHE,   0x09,    4,       32 * 1024, 64, NULL), \
-__CI_TBL(CAI_ICACHE,   0x30,    8,       32 * 1024, 64, NULL), \
 __CI_TBL(CAI_DCACHE,   0x0a,    2,        8 * 1024, 32, NULL), \
 __CI_TBL(CAI_DCACHE,   0x0c,    4,       16 * 1024, 32, NULL), \
 __CI_TBL(CAI_DCACHE,   0x0d,    4,       16 * 1024, 64, NULL), \
 __CI_TBL(CAI_DCACHE,   0x0e,    6,       24 * 1024, 64, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x21,    8,      256 * 1024, 64, NULL), /* L2 (MLC) */ \
+__CI_TBL(CAI_L3CACHE,  0x22, 0xff,      512 * 1024, 64, "sectored, 4-way "), \
+__CI_TBL(CAI_L3CACHE,  0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_L2CACHE,  0x24,   16, 1 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_L3CACHE,  0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_DCACHE,   0x2c,    8,       32 * 1024, 64, NULL), \
+__CI_TBL(CAI_ICACHE,   0x30,    8,       32 * 1024, 64, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x39,    4,      128 * 1024, 64, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x3a,    6,      192 * 1024, 64, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x3b,    2,      128 * 1024, 64, NULL), \
@@ -250,15 +270,21 @@ __CI_TBL(CAI_L2CACHE,  0x42,    4,      
 __CI_TBL(CAI_L2CACHE,  0x43,    4,      512 * 1024, 32, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x44,    4, 1 * 1024 * 1024, 32, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x45,    4, 2 * 1024 * 1024, 32, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x46,    4, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x47,    8, 8 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x48,   12, 3 * 1024 * 1024, 64, NULL), \
 								\
 /* 0x49 Is L2 on Xeon MP (Family 0f, Model 06), L3 otherwise */	\
 __CI_TBL(CAI_L2CACHE,  0x49,   16, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x49,   16, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x4a,   12, 6 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x4b,   16, 8 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x4c,   12,12 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE,  0x4d,   16,16 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x4e,   24, 6 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_DCACHE,   0x60,    8,       16 * 1024, 64, NULL), \
 __CI_TBL(CAI_DCACHE,   0x66,    4,        8 * 1024, 64, NULL), \
 __CI_TBL(CAI_DCACHE,   0x67,    4,       16 * 1024, 64, NULL), \
-__CI_TBL(CAI_DCACHE,   0x2c,    8,       32 * 1024, 64, NULL), \
 __CI_TBL(CAI_DCACHE,   0x68,    4,       32 * 1024, 64, NULL), \
 __CI_TBL(CAI_ICACHE,   0x70,    8,       12 * 1024, 64, "12K uOp cache"), \
 __CI_TBL(CAI_ICACHE,   0x71,    8,       16 * 1024, 64, "16K uOp cache"), \
@@ -278,17 +304,6 @@ __CI_TBL(CAI_L2CACHE,  0x84,    8, 1 * 1
 __CI_TBL(CAI_L2CACHE,  0x85,    8, 2 * 1024 * 1024, 32, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x86,    4,      512 * 1024, 64, NULL), \
 __CI_TBL(CAI_L2CACHE,  0x87,    8, 1 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE,  0x22, 0xff,      512 * 1024, 64, "sectored, 4-way "), \
-__CI_TBL(CAI_L3CACHE,  0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \
-__CI_TBL(CAI_L3CACHE,  0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \
-__CI_TBL(CAI_L3CACHE,  0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \
-__CI_TBL(CAI_L3CACHE,  0x46,    4, 4 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE,  0x47,    8, 8 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE,  0x49,   16, 4 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE,  0x4a,   12, 6 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE,  0x4b,   16, 8 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE,  0x4c,   12,12 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE,  0x4d,   16,16 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_L3CACHE,  0xd0,    4,      512 * 1024, 64, NULL), \
 __CI_TBL(CAI_L3CACHE,  0xd1,    4, 1 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_L3CACHE,  0xd2,    4, 2 * 1024 * 1024, 64, NULL), \

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