Module Name:    src
Committed By:   msaitoh
Date:           Tue Nov 12 15:58:38 UTC 2013

Modified Files:
        src/sys/arch/x86/x86: coretemp.c

Log Message:
 Fix calculation of the cpu model (display model) in coretemp_tjmax().
The CPUID2MODEL() macro returns only low 4bit, so the checking against 0x17
doesn't work correctly. The correct way is to use the display model.
Remove incorrect extmodel check. Same as FreeBSD.


To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/x86/coretemp.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/x86/coretemp.c
diff -u src/sys/arch/x86/x86/coretemp.c:1.29 src/sys/arch/x86/x86/coretemp.c:1.30
--- src/sys/arch/x86/x86/coretemp.c:1.29	Tue Aug 14 14:36:43 2012
+++ src/sys/arch/x86/x86/coretemp.c	Tue Nov 12 15:58:38 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.29 2012/08/14 14:36:43 jruoho Exp $ */
+/* $NetBSD: coretemp.c,v 1.30 2013/11/12 15:58:38 msaitoh Exp $ */
 
 /*-
  * Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.29 2012/08/14 14:36:43 jruoho Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.30 2013/11/12 15:58:38 msaitoh Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -256,11 +256,13 @@ coretemp_tjmax(device_t self)
 {
 	struct coretemp_softc *sc = device_private(self);
 	struct cpu_info *ci = sc->sc_ci;
-	uint32_t extmodel, model, stepping;
+	uint32_t family, model, stepping;
 	uint64_t msr;
 
+	family = CPUID2FAMILY(ci->ci_signature);
 	model = CPUID2MODEL(ci->ci_signature);
-	extmodel = CPUID2EXTMODEL(ci->ci_signature);
+	if ((family == 0xf) || (family == 0x6))
+		model |= CPUID2EXTMODEL(ci->ci_signature) << 4;
 	stepping = CPUID2STEPPING(ci->ci_signature);
 
 	sc->sc_tjmax = 100;
@@ -279,7 +281,7 @@ coretemp_tjmax(device_t self)
 	 * that MSR_IA32_EXT_CONFIG is not safe on all CPUs.
 	 */
 	if ((model == 0x0F && stepping >= 2) ||
-	    (model == 0x0E && extmodel != 1)) {
+	    (model == 0x0E)) {
 
 		if (rdmsr_safe(MSR_IA32_EXT_CONFIG, &msr) == EFAULT)
 			return;
@@ -295,7 +297,7 @@ coretemp_tjmax(device_t self)
 	 * but only consider the interval [70, 100] C as valid.
 	 * It is not fully known which CPU models have the MSR.
 	 */
-	if (model == 0x0E && extmodel != 0) {
+	if (model == 0x0E) {
 
 		if (rdmsr_safe(MSR_TEMPERATURE_TARGET, &msr) == EFAULT)
 			return;

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