Module Name: src
Committed By: matt
Date: Fri Dec 27 12:16:01 UTC 2013
Modified Files:
src/sys/arch/arm/include: armreg.h
src/sys/arch/arm/vfp: vfp_init.c
Log Message:
Switch to using FP instructions instead of cp10/11 instructions.
To generate a diff of this commit:
cvs rdiff -u -r1.83 -r1.84 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/vfp/vfp_init.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.83 src/sys/arch/arm/include/armreg.h:1.84
--- src/sys/arch/arm/include/armreg.h:1.83 Sat Sep 7 00:32:33 2013
+++ src/sys/arch/arm/include/armreg.h Fri Dec 27 12:16:01 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.83 2013/09/07 00:32:33 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.84 2013/12/27 12:16:01 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -650,6 +650,20 @@ static inline void armreg_##name##_write
__asm __volatile("mcr " __insnstring :: "r"(__val)); \
}
+#define ARMREG_READ_INLINE2(name, __insnstring) \
+static inline uint32_t armreg_##name##_read(void) \
+{ \
+ uint32_t __rv; \
+ __asm __volatile(__insnstring : "=r"(__rv)); \
+ return __rv; \
+}
+
+#define ARMREG_WRITE_INLINE2(name, __insnstring) \
+static inline void armreg_##name##_write(uint32_t __val) \
+{ \
+ __asm __volatile(__insnstring :: "r"(__val)); \
+}
+
#define ARMREG_READ64_INLINE(name, __insnstring) \
static inline uint64_t armreg_##name##_read(void) \
{ \
@@ -665,17 +679,17 @@ static inline void armreg_##name##_write
}
/* cp10 registers */
-ARMREG_READ_INLINE(fpsid, "p10,7,%0,c0,c0,0") /* VFP System ID */
-ARMREG_READ_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */
-ARMREG_WRITE_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */
-ARMREG_READ_INLINE(mvfr1, "p10,7,%0,c6,c0,0") /* Media and VFP Feature Register 1 */
-ARMREG_READ_INLINE(mvfr0, "p10,7,%0,c7,c0,0") /* Media and VFP Feature Register 0 */
-ARMREG_READ_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */
-ARMREG_WRITE_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */
-ARMREG_READ_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */
-ARMREG_WRITE_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */
-ARMREG_READ_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */
-ARMREG_WRITE_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */
+ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */
+ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */
+ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */
+ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
+ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
+ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */
+ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */
+ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */
+ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */
+ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
+ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
/* cp15 c0 registers */
ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
Index: src/sys/arch/arm/vfp/vfp_init.c
diff -u src/sys/arch/arm/vfp/vfp_init.c:1.28 src/sys/arch/arm/vfp/vfp_init.c:1.29
--- src/sys/arch/arm/vfp/vfp_init.c:1.28 Sat Dec 14 15:47:18 2013
+++ src/sys/arch/arm/vfp/vfp_init.c Fri Dec 27 12:16:01 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: vfp_init.c,v 1.28 2013/12/14 15:47:18 matt Exp $ */
+/* $NetBSD: vfp_init.c,v 1.29 2013/12/27 12:16:01 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -49,19 +49,24 @@ extern int cpu_neon_present;
#ifdef FPU_VFP
+#ifdef CPU_CORTEX
+__asm(".fpu\tvfpv4");
+#else
+__asm(".fpu\tvfp");
+#endif
+
/* FLDMD <X>, {d0-d15} */
static inline void
load_vfpregs_lo(const uint64_t *p)
{
- /* vldmia rN, {d0-d15} */
- __asm __volatile("ldc\tp11, c0, [%0], {32}" :: "r" (p) : "memory");
+ __asm __volatile("vldmia %0, {d0-d15}" :: "r" (p) : "memory");
}
/* FSTMD <X>, {d0-d15} */
static inline void
save_vfpregs_lo(uint64_t *p)
{
- __asm __volatile("stc\tp11, c0, [%0], {32}" :: "r" (p) : "memory");
+ __asm __volatile("vstmia %0, {d0-d15}" :: "r" (p) : "memory");
}
#ifdef CPU_CORTEX
@@ -69,14 +74,14 @@ save_vfpregs_lo(uint64_t *p)
static inline void
load_vfpregs_hi(const uint64_t *p)
{
- __asm __volatile("ldcl\tp11, c0, [%0], {32}" :: "r" (&p[16]) : "memory");
+ __asm __volatile("vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
}
/* FLDMD <X>, {d16-d31} */
static inline void
save_vfpregs_hi(uint64_t *p)
{
- __asm __volatile("stcl\tp11, c0, [%0], {32}" :: "r" (&p[16]) : "memory");
+ __asm __volatile("vstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
}
#endif
