Module Name: src
Committed By: palle
Date: Fri Feb 21 18:00:09 UTC 2014
Modified Files:
src/lib/libkvm: kvm_sparc64.c
src/sys/arch/sparc/stand/ofwboot: loadfile_machdep.c
src/sys/arch/sparc64/doc: TODO
src/sys/arch/sparc64/include: cpu.h param.h pte.h
src/sys/arch/sparc64/sparc64: autoconf.c genassym.cf locore.s
Log Message:
sun4v: Rename TLB_ defines to SUN4U_TLB_ so entries created using TSB_DATA()
are properly setup for sun4u and sun4v. Relocate the cputyp variable from
autoconf.c to locore.s and make it const in param.h so optimized code can be
generated. Parts from OpenBSD. Optimization suggested by nakayama@. OK martin@,
mrg@, nakayama@
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/lib/libkvm/kvm_sparc64.c
cvs rdiff -u -r1.11 -r1.12 \
src/sys/arch/sparc/stand/ofwboot/loadfile_machdep.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/sparc64/doc/TODO
cvs rdiff -u -r1.109 -r1.110 src/sys/arch/sparc64/include/cpu.h
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/sparc64/include/param.h
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/sparc64/include/pte.h
cvs rdiff -u -r1.192 -r1.193 src/sys/arch/sparc64/sparc64/autoconf.c
cvs rdiff -u -r1.72 -r1.73 src/sys/arch/sparc64/sparc64/genassym.cf
cvs rdiff -u -r1.355 -r1.356 src/sys/arch/sparc64/sparc64/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libkvm/kvm_sparc64.c
diff -u src/lib/libkvm/kvm_sparc64.c:1.16 src/lib/libkvm/kvm_sparc64.c:1.17
--- src/lib/libkvm/kvm_sparc64.c:1.16 Wed Feb 19 20:21:22 2014
+++ src/lib/libkvm/kvm_sparc64.c Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: kvm_sparc64.c,v 1.16 2014/02/19 20:21:22 dsl Exp $ */
+/* $NetBSD: kvm_sparc64.c,v 1.17 2014/02/21 18:00:09 palle Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -38,7 +38,7 @@
#if 0
static char sccsid[] = "@(#)kvm_sparc.c 8.1 (Berkeley) 6/4/93";
#else
-__RCSID("$NetBSD: kvm_sparc64.c,v 1.16 2014/02/19 20:21:22 dsl Exp $");
+__RCSID("$NetBSD: kvm_sparc64.c,v 1.17 2014/02/21 18:00:09 palle Exp $");
#endif
#endif /* LIBC_SCCS and not lint */
@@ -64,6 +64,7 @@ __RCSID("$NetBSD: kvm_sparc64.c,v 1.16 2
#include <machine/pmap.h>
#include <machine/kcore.h>
#include <machine/vmparam.h>
+#include <machine/param.h>
#include <limits.h>
#include <db.h>
@@ -210,7 +211,7 @@ _kvm_kvatop(kvm_t *kd, vaddr_t va, paddr
* XXXX -- We could support multiple page sizes.
*/
va = va & (kd->nbpg - 1);
- data &= TLB_PA_MASK;
+ data &= SUN4U_TLB_PA_MASK; /* XXX handle sun4u/sun4v */
*pa = data + va;
/*
Index: src/sys/arch/sparc/stand/ofwboot/loadfile_machdep.c
diff -u src/sys/arch/sparc/stand/ofwboot/loadfile_machdep.c:1.11 src/sys/arch/sparc/stand/ofwboot/loadfile_machdep.c:1.12
--- src/sys/arch/sparc/stand/ofwboot/loadfile_machdep.c:1.11 Sun Dec 8 14:41:28 2013
+++ src/sys/arch/sparc/stand/ofwboot/loadfile_machdep.c Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: loadfile_machdep.c,v 1.11 2013/12/08 14:41:28 palle Exp $ */
+/* $NetBSD: loadfile_machdep.c,v 1.12 2014/02/21 18:00:09 palle Exp $ */
/*-
* Copyright (c) 2005 The NetBSD Foundation, Inc.
@@ -341,7 +341,7 @@ mmu_mapin_sun4u(vaddr_t rva, vsize_t len
DPRINTF(("mmu_mapin: 0x%lx:0x%x.0x%x\n", va,
hi(pa), lo(pa)));
- data = TSB_DATA(0, /* global */
+ data = SUN4U_TSB_DATA(0, /* global */
PGSZ_4M, /* 4mb page */
pa, /* phys.address */
1, /* privileged */
@@ -351,7 +351,7 @@ mmu_mapin_sun4u(vaddr_t rva, vsize_t len
1, /* valid */
0 /* endianness */
);
- data |= TLB_L | TLB_CV; /* locked, virt.cache */
+ data |= SUN4U_TLB_L | SUN4U_TLB_CV; /* locked, virt.cache */
dtlb_store[dtlb_slot].te_pa = pa;
dtlb_store[dtlb_slot].te_va = va;
@@ -634,7 +634,7 @@ sparc64_finalize_tlb_sun4u(u_long data_v
continue;
}
- data = TSB_DATA(0, /* global */
+ data = SUN4U_TSB_DATA(0, /* global */
PGSZ_4M, /* 4mb page */
dtlb_store[i].te_pa, /* phys.address */
1, /* privileged */
@@ -644,7 +644,7 @@ sparc64_finalize_tlb_sun4u(u_long data_v
1, /* valid */
0 /* endianness */
);
- data |= TLB_L | TLB_CV; /* locked, virt.cache */
+ data |= SUN4U_TLB_L | SUN4U_TLB_CV; /* locked, virt.cache */
if (!writable_text)
dtlb_replace(dtlb_store[i].te_va, hi(data), lo(data));
itlb_store[itlb_slot] = dtlb_store[i];
Index: src/sys/arch/sparc64/doc/TODO
diff -u src/sys/arch/sparc64/doc/TODO:1.1 src/sys/arch/sparc64/doc/TODO:1.2
--- src/sys/arch/sparc64/doc/TODO:1.1 Sat Jan 25 19:07:25 2014
+++ src/sys/arch/sparc64/doc/TODO Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
- /* $NetBSD: TODO,v 1.1 2014/01/25 19:07:25 palle Exp $ */
+ /* $NetBSD: TODO,v 1.2 2014/02/21 18:00:09 palle Exp $ */
Things to be done:
@@ -7,3 +7,6 @@ sun4u:
sun4v:
- 64-bit kernel support
- 32-bit kernel support
+- libkvm
+- ofwboot: tlb_init_sun4v() hardcodes number of slots to 64
+- sun4v_datatrap: missing implementation
Index: src/sys/arch/sparc64/include/cpu.h
diff -u src/sys/arch/sparc64/include/cpu.h:1.109 src/sys/arch/sparc64/include/cpu.h:1.110
--- src/sys/arch/sparc64/include/cpu.h:1.109 Thu Jan 9 20:28:23 2014
+++ src/sys/arch/sparc64/include/cpu.h Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.109 2014/01/09 20:28:23 palle Exp $ */
+/* $NetBSD: cpu.h,v 1.110 2014/02/21 18:00:09 palle Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -381,6 +381,7 @@ void loadfpstate(struct fpstate64 *);
void clearfpstate(void);
uint64_t probeget(paddr_t, int, int);
int probeset(paddr_t, int, int, uint64_t);
+void setcputyp(int);
#define write_all_windows() __asm volatile("flushw" : : )
#define write_user_windows() __asm volatile("flushw" : : )
Index: src/sys/arch/sparc64/include/param.h
diff -u src/sys/arch/sparc64/include/param.h:1.52 src/sys/arch/sparc64/include/param.h:1.53
--- src/sys/arch/sparc64/include/param.h:1.52 Mon Dec 16 20:17:35 2013
+++ src/sys/arch/sparc64/include/param.h Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: param.h,v 1.52 2013/12/16 20:17:35 palle Exp $ */
+/* $NetBSD: param.h,v 1.53 2014/02/21 18:00:09 palle Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -228,7 +228,8 @@ extern void delay(unsigned int);
#define mstohz(ms) ((ms + 0UL) * hz / 1000)
#endif
-extern int cputyp;
+/* Keep this a const so compiler optimization is done */
+extern const int cputyp;
#if defined (SUN4US) || defined (SUN4V)
#define CPU_ISSUN4U (cputyp == CPU_SUN4U)
Index: src/sys/arch/sparc64/include/pte.h
diff -u src/sys/arch/sparc64/include/pte.h:1.24 src/sys/arch/sparc64/include/pte.h:1.25
--- src/sys/arch/sparc64/include/pte.h:1.24 Mon Dec 16 20:17:35 2013
+++ src/sys/arch/sparc64/include/pte.h Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.24 2013/12/16 20:17:35 palle Exp $ */
+/* $NetBSD: pte.h,v 1.25 2014/02/21 18:00:09 palle Exp $ */
/*
* Copyright (c) 1996-1999 Eduardo Horvath
@@ -152,41 +152,41 @@ typedef struct sun4u_tte pte_t;
#define PGSZ_512K 2
#define PGSZ_4M 3
-#define PGSZ_SHIFT 61
-#define TLB_SZ(s) (((uint64_t)(s))<<PGSZ_SHIFT)
+#define SUN4U_PGSZ_SHIFT 61
+#define SUN4U_TLB_SZ(s) (((uint64_t)(s))<<SUN4U_PGSZ_SHIFT)
/* TLB data masks */
-#define TLB_V 0x8000000000000000LL
-#define TLB_8K TLB_SZ(PGSZ_8K)
-#define TLB_64K TLB_SZ(PGSZ_64K)
-#define TLB_512K TLB_SZ(PGSZ_512K)
-#define TLB_4M TLB_SZ(PGSZ_4M)
-#define TLB_SZ_MASK 0x6000000000000000LL
-#define TLB_NFO 0x1000000000000000LL
-#define TLB_IE 0x0800000000000000LL
-#define TLB_SOFT2_MASK 0x07fc000000000000LL
-#define TLB_RESERVED_MASK 0x0003f80000000000LL
-#define TLB_PA_MASK 0x000007ffffffe000LL
-#define TLB_SOFT_MASK 0x0000000000001f80LL
+#define SUN4U_TLB_V 0x8000000000000000LL
+#define SUN4U_TLB_8K SUN4U_TLB_SZ(PGSZ_8K)
+#define SUN4U_TLB_64K SUN4U_TLB_SZ(PGSZ_64K)
+#define SUN4U_TLB_512K SUN4U_TLB_SZ(PGSZ_512K)
+#define SUN4U_TLB_4M SUN4U_TLB_SZ(PGSZ_4M)
+#define SUN4U_TLB_SZ_MASK 0x6000000000000000LL
+#define SUN4U_TLB_NFO 0x1000000000000000LL
+#define SUN4U_TLB_IE 0x0800000000000000LL
+#define SUN4U_TLB_SOFT2_MASK 0x07fc000000000000LL
+#define SUN4U_TLB_RESERVED_MASK 0x0003f80000000000LL
+#define SUN4U_TLB_PA_MASK 0x000007ffffffe000LL
+#define SUN4U_TLB_SOFT_MASK 0x0000000000001f80LL
/* S/W bits */
/* Access & TSB locked bits are swapped so I can set access w/one insn */
-/* #define TLB_ACCESS 0x0000000000001000LL */
-#define TLB_ACCESS 0x0000000000000200LL
-#define TLB_MODIFY 0x0000000000000800LL
-#define TLB_REAL_W 0x0000000000000400LL
-/* #define TLB_TSB_LOCK 0x0000000000000200LL */
-#define TLB_TSB_LOCK 0x0000000000001000LL
+/* #define SUN4U_TLB_ACCESS 0x0000000000001000LL */
+#define SUN4U_TLB_ACCESS 0x0000000000000200LL
+#define SUN4U_TLB_MODIFY 0x0000000000000800LL
+#define SUN4U_TLB_REAL_W 0x0000000000000400LL
+/* #define SUN4U_TLB_TSB_LOCK 0x0000000000000200LL */
+#define SUN4U_TLB_TSB_LOCK 0x0000000000001000LL
#define SUN4U_TLB_EXEC 0x0000000000000100LL
-#define TLB_EXEC_ONLY 0x0000000000000080LL
+#define SUN4U_TLB_EXEC_ONLY 0x0000000000000080LL
/* H/W bits */
-#define TLB_L 0x0000000000000040LL
-#define TLB_CACHE_MASK 0x0000000000000030LL
-#define TLB_CP 0x0000000000000020LL
-#define TLB_CV 0x0000000000000010LL
-#define TLB_E 0x0000000000000008LL
-#define TLB_P 0x0000000000000004LL
-#define TLB_W 0x0000000000000002LL
-#define TLB_G 0x0000000000000001LL
+#define SUN4U_TLB_L 0x0000000000000040LL
+#define SUN4U_TLB_CACHE_MASK 0x0000000000000030LL
+#define SUN4U_TLB_CP 0x0000000000000020LL
+#define SUN4U_TLB_CV 0x0000000000000010LL
+#define SUN4U_TLB_E 0x0000000000000008LL
+#define SUN4U_TLB_P 0x0000000000000004LL
+#define SUN4U_TLB_W 0x0000000000000002LL
+#define SUN4U_TLB_G 0x0000000000000001LL
/* Use a bit in the SOFT2 area to indicate a locked mapping. */
#define TLB_WIRED 0x0010000000000000LL
@@ -196,23 +196,23 @@ typedef struct sun4u_tte pte_t;
* be duplicates of the above w/o the "long long"
*/
/* S/W bits */
-/* #define TTE_ACCESS 0x0000000000001000 */
-#define TTE_ACCESS 0x0000000000000200
-#define TTE_MODIFY 0x0000000000000800
-#define TTE_REAL_W 0x0000000000000400
-/* #define TTE_TSB_LOCK 0x0000000000000200 */
-#define TTE_TSB_LOCK 0x0000000000001000
-#define TTE_EXEC 0x0000000000000100
-#define TTE_EXEC_ONLY 0x0000000000000080
+/* #define SUN4U_TTE_ACCESS 0x0000000000001000 */
+#define SUN4U_TTE_ACCESS 0x0000000000000200
+#define SUN4U_TTE_MODIFY 0x0000000000000800
+#define SUN4U_TTE_REAL_W 0x0000000000000400
+/* #define SUN4U_TTE_TSB_LOCK 0x0000000000000200 */
+#define SUN4U_TTE_TSB_LOCK 0x0000000000001000
+#define SUN4U_TTE_EXEC 0x0000000000000100
+#define SUN4U_TTE_EXEC_ONLY 0x0000000000000080
/* H/W bits */
-#define TTE_L 0x0000000000000040
-#define TTE_CACHE_MASK 0x0000000000000030
-#define TTE_CP 0x0000000000000020
-#define TTE_CV 0x0000000000000010
-#define TTE_E 0x0000000000000008
-#define TTE_P 0x0000000000000004
-#define TTE_W 0x0000000000000002
-#define TTE_G 0x0000000000000001
+#define SUN4U_TTE_L 0x0000000000000040
+#define SUN4U_TTE_CACHE_MASK 0x0000000000000030
+#define SUN4U_TTE_CP 0x0000000000000020
+#define SUN4U_TTE_CV 0x0000000000000010
+#define SUN4U_TTE_E 0x0000000000000008
+#define SUN4U_TTE_P 0x0000000000000004
+#define SUN4U_TTE_W 0x0000000000000002
+#define SUN4U_TTE_G 0x0000000000000001
#define TTE_DATA_BITS "\177\20" \
"b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \
@@ -255,10 +255,10 @@ typedef struct sun4u_tte pte_t;
#define SUN4V_TLB_W 0x0000000000000040LL
#define SUN4V_TLB_G 0x0000000000000000LL
-#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
-(((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((uint64_t)(pa))&TLB_PA_MASK)|\
-((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\
-((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL))
+#define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
+(((valid)?SUN4U_TLB_V:0LL)|SUN4U_TLB_SZ(sz)|(((uint64_t)(pa))&SUN4U_TLB_PA_MASK)|\
+((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):SUN4U_TLB_E)|\
+((priv)?SUN4U_TLB_P:0LL)|((write)?SUN4U_TLB_W:0LL)|((g)?SUN4U_TLB_G:0LL)|((ie)?SUN4U_TLB_IE:0LL))
#define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
(((valid)?SUN4V_TLB_V:0LL)|SUN4V_TLB_SZ(sz)|\
@@ -267,8 +267,23 @@ typedef struct sun4u_tte pte_t;
((priv)?SUN4V_TLB_P:0LL)|((write)?SUN4V_TLB_W:0LL)|((g)?SUN4V_TLB_G:0LL)|\
((ie)?SUN4V_TLB_IE:0LL))
+#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
+(CPU_ISSUN4V ? SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) : \
+ SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie))
-#define TLB_EXEC (CPU_ISSUN4V ? SUN4V_TLB_EXEC : SUN4U_TLB_EXEC)
+#define TLB_EXEC (CPU_ISSUN4V ? SUN4V_TLB_EXEC : SUN4U_TLB_EXEC)
+#define TLB_V (CPU_ISSUN4V ? SUN4V_TLB_V : SUN4U_TLB_V)
+#define TLB_PA_MASK (CPU_ISSUN4V ? SUN4V_TLB_PA_MASK : SUN4U_TLB_PA_MASK)
+#define TLB_CP (CPU_ISSUN4V ? SUN4V_TLB_CP : SUN4U_TLB_CP)
+#define TLB_P (CPU_ISSUN4V ? SUN4V_TLB_P : SUN4U_TLB_P)
+#define TLB_W (CPU_ISSUN4V ? SUN4V_TLB_W : SUN4U_TLB_W)
+#define TLB_ACCESS (CPU_ISSUN4V ? SUN4V_TLB_ACCESS : SUN4U_TLB_ACCESS)
+#define TLB_MODIFY (CPU_ISSUN4V ? SUN4V_TLB_MODIFY : SUN4U_TLB_MODIFY)
+#define TLB_REAL_W (CPU_ISSUN4V ? SUN4V_TLB_REAL_W : SUN4U_TLB_REAL_W)
+#define TLB_TSB_LOCK (CPU_ISSUN4V ? SUN4V_TLB_TSB_LOCK : SUN4U_TLB_TSB_LOCK)
+#define TLB_EXEC_ONLY (CPU_ISSUN4V ? SUN4V_TLB_EXEC_ONLY : SUN4U_TLB_EXEC_ONLY)
+#define TLB_L (CPU_ISSUN4V ? SUN4V_TLB_L : SUN4U_TLB_L)
+#define TLB_CV (CPU_ISSUN4V ? SUN4V_TLB_CV : SUN4U_TLB_CV)
#define MMU_CACHE_VIRT 0x3
#define MMU_CACHE_PHYS 0x2
Index: src/sys/arch/sparc64/sparc64/autoconf.c
diff -u src/sys/arch/sparc64/sparc64/autoconf.c:1.192 src/sys/arch/sparc64/sparc64/autoconf.c:1.193
--- src/sys/arch/sparc64/sparc64/autoconf.c:1.192 Tue Sep 24 18:11:54 2013
+++ src/sys/arch/sparc64/sparc64/autoconf.c Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.192 2013/09/24 18:11:54 jdc Exp $ */
+/* $NetBSD: autoconf.c,v 1.193 2014/02/21 18:00:09 palle Exp $ */
/*
* Copyright (c) 1996
@@ -48,7 +48,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.192 2013/09/24 18:11:54 jdc Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.193 2014/02/21 18:00:09 palle Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -139,9 +139,6 @@ void *bootinfo = 0;
int kgdb_break_at_attach;
#endif
-/* Default to sun4u */
-int cputyp = CPU_SUN4U;
-
#define OFPATHLEN 128
#define OFNODEKEY "OFpnode"
@@ -344,12 +341,11 @@ die_old_boot_loader:
#endif
#endif
#endif
-
if (OF_getprop(findroot(), "compatible", buf, sizeof(buf)) > 0) {
if (strcmp(buf, "sun4us") == 0)
- cputyp = CPU_SUN4US;
+ setcputyp(CPU_SUN4US);
else if (strcmp(buf, "sun4v") == 0)
- cputyp = CPU_SUN4V;
+ setcputyp(CPU_SUN4V);
}
bi_howto = lookup_bootinfo(BTINFO_BOOTHOWTO);
Index: src/sys/arch/sparc64/sparc64/genassym.cf
diff -u src/sys/arch/sparc64/sparc64/genassym.cf:1.72 src/sys/arch/sparc64/sparc64/genassym.cf:1.73
--- src/sys/arch/sparc64/sparc64/genassym.cf:1.72 Sun Jan 26 20:12:32 2014
+++ src/sys/arch/sparc64/sparc64/genassym.cf Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.72 2014/01/26 20:12:32 palle Exp $
+# $NetBSD: genassym.cf,v 1.73 2014/02/21 18:00:09 palle Exp $
#
# Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -137,9 +137,10 @@ define PM_RESIDENT offsetof(struct pmap,
define PM_WIRED offsetof(struct pmap, pm_stats.wired_count)
# the assembler doesn't grok C constants with LL suffix
-define A_TLB_TSB_LOCK TLB_TSB_LOCK
+define A_SUN4U_TLB_TSB_LOCK SUN4U_TLB_TSB_LOCK
ifdef SUN4V
define A_SUN4V_TLB_ACCESS SUN4V_TLB_ACCESS
+define A_SUN4V_TLB_TSB_LOCK SUN4V_TLB_TSB_LOCK
endif
# CPU info structure
Index: src/sys/arch/sparc64/sparc64/locore.s
diff -u src/sys/arch/sparc64/sparc64/locore.s:1.355 src/sys/arch/sparc64/sparc64/locore.s:1.356
--- src/sys/arch/sparc64/sparc64/locore.s:1.355 Fri Jan 31 18:56:24 2014
+++ src/sys/arch/sparc64/sparc64/locore.s Fri Feb 21 18:00:09 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.355 2014/01/31 18:56:24 tsutsui Exp $ */
+/* $NetBSD: locore.s,v 1.356 2014/02/21 18:00:09 palle Exp $ */
/*
* Copyright (c) 2006-2010 Matthew R. Green
@@ -166,6 +166,9 @@ romp: POINTER 0
.globl romtba
romtba: POINTER 0
+ .globl cputyp
+cputyp: .word CPU_SUN4U ! Default to sun4u
+
_ALIGN
.text
@@ -1523,9 +1526,9 @@ dmmu_write_fault:
1:
ldxa [%g6] ASI_PHYS_CACHED, %g4
brgez,pn %g4, winfix ! Entry invalid? Punt
- or %g4, TTE_MODIFY|TTE_ACCESS|TTE_W, %g7 ! Update the modified bit
+ or %g4, SUN4U_TTE_MODIFY|SUN4U_TTE_ACCESS|SUN4U_TTE_W, %g7 ! Update the modified bit
- btst TTE_REAL_W|TTE_W, %g4 ! Is it a ref fault?
+ btst SUN4U_TTE_REAL_W|SUN4U_TTE_W, %g4 ! Is it a ref fault?
bz,pn %xcc, winfix ! No -- really fault
#ifdef DEBUG
/* Make sure we don't try to replace a kernel translation */
@@ -1550,7 +1553,7 @@ dmmu_write_fault:
membar #StoreLoad
cmp %g4, %g7
bne,pn %xcc, 1b
- or %g4, TTE_MODIFY|TTE_ACCESS|TTE_W, %g4 ! Update the modified bit
+ or %g4, SUN4U_TTE_MODIFY|SUN4U_TTE_ACCESS|SUN4U_TTE_W, %g4 ! Update the modified bit
stx %g1, [%g2] ! Update TSB entry tag
mov SFSR, %g7
stx %g4, [%g2+8] ! Update TSB entry data
@@ -1654,15 +1657,15 @@ data_miss:
1:
ldxa [%g6] ASI_PHYS_CACHED, %g4
brgez,pn %g4, data_nfo ! Entry invalid? Punt
- or %g4, TTE_ACCESS, %g7 ! Update the access bit
+ or %g4, SUN4U_TTE_ACCESS, %g7 ! Update the access bit
- btst TTE_ACCESS, %g4 ! Need to update access git?
+ btst SUN4U_TTE_ACCESS, %g4 ! Need to update access git?
bne,pt %xcc, 1f
nop
casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and write it out
cmp %g4, %g7
bne,pn %xcc, 1b
- or %g4, TTE_ACCESS, %g4 ! Update the access bit
+ or %g4, SUN4U_TTE_ACCESS, %g4 ! Update the access bit
1:
stx %g1, [%g2] ! Update TSB entry tag
@@ -2431,18 +2434,18 @@ instr_miss:
nop
/* Check if it's an executable mapping. */
- andcc %g4, TTE_EXEC, %g0
+ andcc %g4, SUN4U_TTE_EXEC, %g0
bz,pn %xcc, textfault
nop
- or %g4, TTE_ACCESS, %g7 ! Update accessed bit
- btst TTE_ACCESS, %g4 ! Need to update access git?
+ or %g4, SUN4U_TTE_ACCESS, %g7 ! Update accessed bit
+ btst SUN4U_TTE_ACCESS, %g4 ! Need to update access git?
bne,pt %xcc, 1f
nop
casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and store it
cmp %g4, %g7
bne,pn %xcc, 1b
- or %g4, TTE_ACCESS, %g4 ! Update accessed bit
+ or %g4, SUN4U_TTE_ACCESS, %g4 ! Update accessed bit
1:
stx %g1, [%g2] ! Update TSB entry tag
stx %g4, [%g2+8] ! Update TSB entry data
@@ -3457,7 +3460,7 @@ ENTRY_NOPROFILE(sparc_interrupt)
#ifdef TRAPS_USE_IG
! This is for interrupt debugging
wrpr %g0, PSTATE_KERN|PSTATE_IG, %pstate ! DEBUG
-#endif
+#endif
/*
* If this is a %tick or %stick softint, clear it then call
* interrupt_vector. Only one of them should be enabled at any given
@@ -4219,17 +4222,17 @@ dostart:
*/
#ifdef NO_VCACHE
-#define TTE_DATABITS TTE_L|TTE_CP|TTE_P|TTE_W
+#define SUN4U_TTE_DATABITS SUN4U_TTE_L|SUN4U_TTE_CP|SUN4U_TTE_P|SUN4U_TTE_W
#else
-#define TTE_DATABITS TTE_L|TTE_CP|TTE_CV|TTE_P|TTE_W
+#define SUN4U_TTE_DATABITS SUN4U_TTE_L|SUN4U_TTE_CP|SUN4U_TTE_CV|SUN4U_TTE_P|SUN4U_TTE_W
#endif
ENTRY_NOPROFILE(cpu_initialize) /* for cosmetic reasons - nicer backtrace */
/* Cache the cputyp in %l6 for later user below */
- sethi %hi(_C_LABEL(cputyp)), %l6
- ld [%l6 + %lo(_C_LABEL(cputyp))], %l6
+ sethi %hi(cputyp), %l6
+ ld [%l6 + %lo(cputyp)], %l6
/*
* Step 5: is no more.
@@ -4279,7 +4282,7 @@ ENTRY_NOPROFILE(cpu_initialize) /* for c
andn %l1, %l4, %l1 ! Mask the phys page number
or %l2, %l1, %l1 ! Now take care of the high bits
- or %l1, TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0
+ or %l1, SUN4U_TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0
!!
!! Now, map in the interrupt stack as context==0
@@ -4441,6 +4444,12 @@ ENTRY(get_romtba)
retl
rdpr %tba, %o0
+ENTRY(setcputyp)
+ sethi %hi(cputyp), %o1 ! Trash %o1 assuming this is ok
+ st %o0, [%o1 + %lo(cputyp)]
+ retl
+ nop
+
#ifdef MULTIPROCESSOR
/*
* cpu_mp_startup is called with:
@@ -4468,7 +4477,7 @@ ENTRY(cpu_mp_startup)
or %l4, 0xfff, %l4 ! We can just load this in 12 (of 13) bits
andn %l1, %l4, %l1 ! Mask the phys page number
or %l2, %l1, %l1 ! Now take care of the high bits
- or %l1, TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0
+ or %l1, SUN4U_TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0
/*
* Now, map in the interrupt stack & cpu_info as context==0
@@ -5940,7 +5949,20 @@ ENTRY(pseg_set_real)
!! %o5 = old TTE
!! see if stats needs an update
- set A_TLB_TSB_LOCK, %g5
+#ifdef SUN4V
+ sethi %hi(cputyp), %g5
+ ld [%g5 + %lo(cputyp)], %g5
+ cmp %g5, CPU_SUN4V
+ bne,pt %icc, 0f
+ nop
+ sethi %hh(A_SUN4V_TLB_TSB_LOCK), %g5
+ sllx %g5, 32, %g5
+ ba 1f
+ nop
+0:
+#endif
+ set A_SUN4U_TLB_TSB_LOCK, %g5
+1:
xor %o2, %o5, %o3 ! %o3 - what changed
brgez,pn %o3, 5f ! has resident changed? (we predict it has)
