Module Name: src
Committed By: matt
Date: Fri Feb 21 22:18:47 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
Add EMAC and CPUCFG registers
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.9 src/sys/arch/arm/allwinner/awin_reg.h:1.10
--- src/sys/arch/arm/allwinner/awin_reg.h:1.9 Mon Sep 9 17:52:48 2013
+++ src/sys/arch/arm/allwinner/awin_reg.h Fri Feb 21 22:18:47 2014
@@ -108,7 +108,7 @@
#define AWIN_TP_OFFSET 0x00025000
#define AWIN_PMU_OFFSET 0x00025400
#define AWIN__RSVD6_OFFSET 0x00025800
-#define AWIN_CPUCNF_OFFSET 0x00025C00
+#define AWIN_CPUCFG_OFFSET 0x00025C00
#define AWIN__RSVD7_OFFSET 0x00026000
#define AWIN__RSVD8_OFFSET 0x00026400
#define AWIN__RSVD9_OFFSET 0x00026800
@@ -153,6 +153,13 @@
#define AWIN_AVG_OFFSET 0x002A0000
#define AWIN_SDRAM_PBASE 0x40000000
+/* A10/A20 SRAM Controller */
+#define AWIN_SRAM_CTL0_REG 0x0000
+#define AWIN_SRAM_CTL1_REG 0x0004
+
+#define AWIN_SRAM_CTL1_A3_A4 __BITS(5,4)
+#define AWIN_SRAM_CTL1_A3_A4_EMAC 1
+
/* A10/A20 DRAM Controller */
#define AWIN_DRAM_CCR_REG 0x0000
#define AWIN_DRAM_DCR_REG 0x0004
@@ -224,6 +231,124 @@
#define AWIN_DRAM_HPCR_PRIORITY_LEVEL __BIT(2)
#define AWIN_DRAM_HPCR_ACCESS_EN __BIT(0)
+/* DMA controller defintions */
+#define AWIN_DMA_IRQ_EN_REG 0x0000
+#define AWIN_DMA_IRQ_PEND_STA_REG 0x0004
+#define AWIN_NDMA_AUTO_GATE_REG 0x0008
+#define AWIN_NDMA_REG(n) (0x100+0x20*(n))
+#define AWIN_NDMA_CTL_REG 0x0000
+#define AWIN_NDMA_SRC_ADDR_REG 0x0004
+#define AWIN_NDMA_DEST_ADDR_REG 0x0008
+#define AWIN_NDMA_BC_REG 0x000c
+
+#define AWIN_DDMA_REG(n) (0x300+0x20*(n))
+#define AWIN_DDMA_CTL_REG 0x0000
+#define AWIN_DDMA_SRC_START_ADDR_REG 0x0004
+#define AWIN_DDMA_DEST_START_ADDR_REG 0x0008
+#define AWIN_DDMA_BC_REG 0x000c
+#define AWIN_DDMA_PARA_REG 0x0018
+
+#define AWIN_DMA_IRQ_DDMA_END(n) __BIT(17+2*(n))
+#define AWIN_DMA_IRQ_DDMA_HF(n) __BIT(16+2*(n))
+#define AWIN_DMA_IRQ_NDMA_END(n) __BIT(1+2*(n))
+#define AWIN_DMA_IRQ_NDMA_HF(n) __BIT(0+2*(n))
+
+#define AWIN_NDMA_AUTO_GATING_DIS __BIT(16)
+
+#define AWIN_DMA_CTL_DST_DATA_WIDTH __BITS(26,25)
+#define AWIN_DMA_CTL_DATA_WIDTH_8 0
+#define AWIN_DMA_CTL_DATA_WIDTH_16 1
+#define AWIN_DMA_CTL_DATA_WIDTH_32 2
+#define AWIN_DMA_CTL_DST_BURST_LEN __BITS(24,23)
+#define AWIN_DMA_CTL_BURST_LEN_1 0
+#define AWIN_DMA_CTL_BURST_LEN_4 1
+#define AWIN_DMA_CTL_BURST_LEN_8 2
+#define AWIN_DMA_CTL_DST_DRQ_TYPE __BITS(20,16)
+#define AWIN_DMA_CTL_BC_REMAINING __BIT(15)
+#define AWIN_DMA_CTL_SRC_DATA_WIDTH __BITS(10,9)
+#define AWIN_DMA_CTL_SRC_BURST_LEN __BITS(8,7)
+#define AWIN_DMA_CTL_SRC_DRQ_TYPE __BITS(4,0)
+
+#define AWIN_NDMA_CTL_DMA_LOADING __BIT(31)
+#define AWIN_NDMA_CTL_DMA_CONTIN_MODE __BIT(30)
+#define AWIN_NDMA_CTL_WAIT_STATE_LOG2 __BITS(29,27)
+#define AWIN_NDMA_CTL_DST_NON_SECURE __BIT(22)
+#define AWIN_NDMA_CTL_DST_ADDR_NOINCR __BIT(21)
+#define AWIN_NDMA_CTL_DRQ_IRO 0
+#define AWIN_NDMA_CTL_DRQ_IR1 1
+#define AWIN_NDMA_CTL_DRQ_SPDIF 2
+#define AWIN_NDMA_CTL_DRQ_IISO 3
+#define AWIN_NDMA_CTL_DRQ_IIS1 4
+#define AWIN_NDMA_CTL_DRQ_AC97 5
+#define AWIN_NDMA_CTL_DRQ_IIS2 6
+#define AWIN_NDMA_CTL_DRQ_UARTO 8
+#define AWIN_NDMA_CTL_DRQ_UART1 9
+#define AWIN_NDMA_CTL_DRQ_UART2 10
+#define AWIN_NDMA_CTL_DRQ_UART3 11
+#define AWIN_NDMA_CTL_DRQ_UART4 12
+#define AWIN_NDMA_CTL_DRQ_UART5 13
+#define AWIN_NDMA_CTL_DRQ_UART6 14
+#define AWIN_NDMA_CTL_DRQ_UART7 15
+#define AWIN_NDMA_CTL_DRQ_DDC 16
+#define AWIN_NDMA_CTL_DRQ_USB_EP1 17
+#define AWIN_NDMA_CTL_DRQ_CODEC 19
+#define AWIN_NDMA_CTL_DRQ_SRAM 21
+#define AWIN_NDMA_CTL_DRQ_SDRAM 22
+#define AWIN_NDMA_CTL_DRQ_TP_AD 23
+#define AWIN_NDMA_CTL_DRQ_SPI0 24
+#define AWIN_NDMA_CTL_DRQ_SPI1 25
+#define AWIN_NDMA_CTL_DRQ_SPI2 26
+#define AWIN_NDMA_CTL_DRQ_SPI3 27
+#define AWIN_NDMA_CTL_DRQ_USB_EP2 28
+#define AWIN_NDMA_CTL_DRQ_USB_EP3 29
+#define AWIN_NDMA_CTL_DRQ_USB_EP4 30
+#define AWIN_NDMA_CTL_DRQ_USB_EP5 31
+#define AWIN_NDMA_CTL_SRC_NON_SECURE __BIT(6)
+#define AWIN_NDMA_CTL_SRC_ADDR_NOINCR __BIT(5)
+
+#define AWIN_NDMA_BC_COUNT __BITS(17,0)
+
+#define AWIN_DDMA_CTL_DMA_LOADING __BIT(31)
+#define AWIN_DDMA_CTL_BUSY __BIT(30)
+#define AWIN_DDMA_CTL_DMA_CONTIN_MODE __BIT(29)
+#define AWIN_DDMA_CTL_DST_NON_SECURE __BIT(28)
+#define AWIN_DDMA_CTL_DST_ADDR_MODE __BITS(22,21)
+#define AWIN_DDMA_CTL_DMA_ADDR_LINEAR 0
+#define AWIN_DDMA_CTL_DMA_ADDR_IO 1
+#define AWIN_DDMA_CTL_DMA_ADDR_HPAGE 2
+#define AWIN_DDMA_CTL_DMA_ADDR_VPAGE 3
+#define AWIN_DDMA_CTL_DST_DRQ_TYPE __BITS(20,16)
+#define AWIN_DDMA_CTL_DRQ_SRAM 0
+#define AWIN_DDMA_CTL_DRQ_SDRAM 1
+#define AWIN_DDMA_CTL_DRQ_NFC 3
+#define AWIN_DDMA_CTL_DRQ_USB0 4
+#define AWIN_DDMA_CTL_DRQ_EMAC_TX 6
+#define AWIN_DDMA_CTL_DRQ_EMAC_RX 7
+#define AWIN_DDMA_CTL_DRQ_SPI1_TX 8
+#define AWIN_DDMA_CTL_DRQ_SPI1_RX 9
+#define AWIN_DDMA_CTL_DRQ_SS_TX 10
+#define AWIN_DDMA_CTL_DRQ_SS_RX 11
+#define AWIN_DDMA_CTL_DRQ_TCON0 14
+#define AWIN_DDMA_CTL_DRQ_TCON1 15
+#define AWIN_DDMA_CTL_DRQ_MS_TX 23
+#define AWIN_DDMA_CTL_DRQ_MS_RX 23
+#define AWIN_DDMA_CTL_DRQ_HDMI_AUDIO 24
+#define AWIN_DDMA_CTL_DRQ_SPI0_TX 26
+#define AWIN_DDMA_CTL_DRQ_SPI0_RX 27
+#define AWIN_DDMA_CTL_DRQ_SPI2_TX 28
+#define AWIN_DDMA_CTL_DRQ_SPI2_RX 29
+#define AWIN_DDMA_CTL_DRQ_SPI3_TX 30
+#define AWIN_DDMA_CTL_DRQ_SPI3_RX 31
+#define AWIN_DDMA_CTL_SRC_NON_SECURE __BIT(12)
+#define AWIN_DDMA_CTL_SRC_ADDR_MODE __BITS(6,5)
+
+#define AWIN_DDMA_BC_COUNT __BITS(13,0)
+
+#define AWIN_DDMA_PARA_DST_DATA_BLK_SIZ __BITS(31,24)
+#define AWIN_DDMA_PARA_DST_WAIT_CYC __BITS(23,16)
+#define AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ __BITS(15,8)
+#define AWIN_DDMA_PARA_SRC_WAIT_CYC __BITS(7,0)
+
#define AWIN_NFC_CTL_REG 0x0000
#define AWIN_NFC_ST_REG 0x0004
#define AWIN_NFC_INT_REG 0x0008
@@ -265,16 +390,16 @@
#define AWIN_NFC_CTL_RESET __BIT(1)
#define AWIN_NFC_CTL_EN __BIT(0)
-#define AWIN_NFC_ST_STATE3 __BIT(11)
-#define AWIN_NFC_ST_STATE2 __BIT(10)
-#define AWIN_NFC_ST_STATE1 __BIT(9)
-#define AWIN_NFC_ST_STATE0 __BIT(8)
-#define AWIN_NFC_ST_MATCH_INT __BIT(5)
-#define AWIN_NFC_ST_STAT __BIT(4)
-#define AWIN_MFC_ST_CMD_FIFO __BIT(3)
-#define AWIN_MFC_ST_DMA_INT __BIT(2)
-#define AWIN_MFC_ST_CMD_INT __BIT(1)
-#define AWIN_MFC_ST_RB_B2R __BIT(0)
+#define AWIN_NFC_ST_STATE3 __BIT(11)
+#define AWIN_NFC_ST_STATE2 __BIT(10)
+#define AWIN_NFC_ST_STATE1 __BIT(9)
+#define AWIN_NFC_ST_STATE0 __BIT(8)
+#define AWIN_NFC_ST_MATCH_INT __BIT(5)
+#define AWIN_NFC_ST_STAT __BIT(4)
+#define AWIN_MFC_ST_CMD_FIFO __BIT(3)
+#define AWIN_MFC_ST_DMA_INT __BIT(2)
+#define AWIN_MFC_ST_CMD_INT __BIT(1)
+#define AWIN_MFC_ST_RB_B2R __BIT(0)
#define AWIN_NFC_INT_DMA_EN __BIT(2)
#define AWIN_NFC_INT_CMD_EN __BIT(1)
@@ -326,12 +451,15 @@
#define AWIN_EMAC_TX_FLOW_REG 0x0008
#define AWIN_EMAC_TX_CTL0_REG 0x000C
#define AWIN_EMAC_TX_CTL1_REG 0x0010
+#define AWIN_EMAC_TX_CTL_REG(n) (0x000C+4*(n))
#define AWIN_EMAC_TX_INS_REG 0x0014
#define AWIN_EMAC_TX_PL0_REG 0x0018
#define AWIN_EMAC_TX_PL1_REG 0x001C
+#define AWIN_EMAC_TX_PL_REG(n) (0x0018+4*(n))
#define AWIN_EMAC_TX_STA_REG 0x0020
#define AWIN_EMAC_TX_IO_DATA0_REG 0x0024
#define AWIN_EMAC_TX_IO_DATA1_REG 0x0028
+#define AWIN_EMAC_TX_IO_DATA_REG(n) (0x0024+4*(n))
#define AWIN_EMAC_TX_TSVL0_REG 0x002C
#define AWIN_EMAC_TX_TSVH0_REG 0x0030
#define AWIN_EMAC_TX_TSVL1_REG 0x0034
@@ -371,6 +499,69 @@
#define AWIN_EMAC_SAFX3_L_REG 0x00BC
#define AWIN_EMAC_SAFX3_H_REG 0x00C0
+#define AWIN_EMAC_RXHDR_STS __BITS(31,16)
+#define AWIN_EMAC_RXHDR_LEN __BITS(15,0)
+
+#define AWIN_EMAC_TX_MODE_ABF_ENA __BIT(0)
+#define AWIN_EMAC_TX_MODE_DMA __BIT(1)
+
+#define AWIN_EMAC_TX_CTL_START __BIT(0)
+
+#define AWIN_EMAC_RX_CTL_SA_IF __BIT(25) // SA filter invert
+#define AWIN_EMAC_RX_CTL_SA __BIT(24) // SA filter
+#define AWIN_EMAC_RX_CTL_BC0 __BIT(22) // broadcast ena
+#define AWIN_EMAC_RX_CTL_MHF __BIT(21) // multicast hash ena
+#define AWIN_EMAC_RX_CTL_MC0 __BIT(20) // multicast accept
+#define AWIN_EMAC_RX_CTL_DAF __BIT(17) // DA filter
+#define AWIN_EMAC_RX_CTL_UCAD __BIT(16) // unicast accept
+#define AWIN_EMAC_RX_CTL_POR __BIT(8) // pass too long
+#define AWIN_EMAC_RX_CTL_PLE __BIT(7) // pass length err
+#define AWIN_EMAC_RX_CTL_PCRCE __BIT(6) // pass crc errors
+#define AWIN_EMAC_RX_CTL_PCF __BIT(5) // pass control frames
+#define AWIN_EMAC_RX_CTL_PROMISC __BIT(4) // pass all frames
+#define AWIN_EMAC_RX_CTL_FIFO_RESET __BIT(3)
+#define AWIN_EMAC_RX_CTL_DMA __BIT(2)
+#define AWIN_EMAC_RX_CTL_DRQ_MODE __BIT(1)
+#define AWIN_EMAC_RX_CTL_START __BIT(0)
+
+#define AWIN_EMAC_RX_MAGIC 0x0143414d // M A C \001
+
+#define AWIN_EMAC_MAC_CTL0_SOFT_RESET __BIT(15)
+#define AWIN_EMAC_MAC_CTL0_TFC __BIT(3)
+#define AWIN_EMAC_MAC_CTL0_RFC __BIT(2)
+
+#define AWIN_EMAC_MAC_CTL1_ED __BIT(15)
+#define AWIN_EMAC_MAC_CTL1_NB __BIT(13)
+#define AWIN_EMAC_MAC_CTL1_BNB __BIT(12)
+#define AWIN_EMAC_MAC_CTL1_LPE __BIT(9)
+#define AWIN_EMAC_MAC_CTL1_PRE __BIT(8)
+#define AWIN_EMAC_MAC_CTL1_ADP __BIT(7) // auto detect short
+#define AWIN_EMAC_MAC_CTL1_VC __BIT(6) // pad short and append
+#define AWIN_EMAC_MAC_CTL1_PC __BIT(5) // enable pad short
+#define AWIN_EMAC_MAC_CTL1_CRC __BIT(4) // append crc
+#define AWIN_EMAC_MAC_CTL1_DCRC __BIT(3) // delayed CRC
+#define AWIN_EMAC_MAC_CTL1_HF __BIT(2) // huge frame
+#define AWIN_EMAC_MAC_CTL1_FLC __BIT(1) // frame length check
+#define AWIN_EMAC_MAC_CTL1_FD __BIT(0) // full duplex
+
+#define AWIN_EMAC_MAC_IPGR_IPG1 __BITS(7,0)
+#define AWIN_EMAC_MAC_IPGR_IPG2 __BITS(15,8)
+
+#define AWIN_EMAC_MAC_CLRT_RM __BITS(7,0)
+#define AWIN_EMAC_MAC_CLRT_CW __BITS(15,8)
+
+#define AWIN_EMAC_MAC_SUPP_100M __BIT(8)
+
+#define AWIN_EMAC_RX_STA_CRCERR __BIT(4)
+#define AWIN_EMAC_RX_STA_LENERR __BIT(5)
+#define AWIN_EMAC_RX_STA_ALNERR __BIT(6)
+
+#define AWIN_MAC_MCFG_CLK __BITS(5,2)
+
+#define AWIN_EMAC_INT_RX __BIT(8)
+#define AWIN_EMAC_INT_TX1 __BIT(1)
+#define AWIN_EMAC_INT_TX0 __BIT(0)
+
#define AWIN_AHCI_DMA_REG 0x0070
#define AWIN_AHCI_BISTAFR_REG 0x00A0
#define AWIN_AHCI_BISTCR_REG 0x00A4
@@ -396,6 +587,23 @@
#define AWIN_AHCI_P0PHYCR_REG 0x0178
#define AWIN_AHCI_P0PHYSR_REG 0x017C
+#define AWIN_CPUCFG_CPU0_RST_CTRL_REG 0x0040
+#define AWIN_CPUCFG_CPU0_CTRL_REG 0x0044
+#define AWIN_CPUCFG_CPU0_STATUS_REG 0x0048
+#define AWIN_CPUCFG_CPU1_RST_CTRL_REG 0x0080
+#define AWIN_CPUCFG_CPU1_CTRL_REG 0x0084
+#define AWIN_CPUCFG_CPU1_STATUS_REG 0x0088
+#define AWIN_CPUCFG_PRIVATE_REG 0x01A4
+
+#define AWIN_CPUCFG_CPU_RST_CTRL_CORE_RESET __BIT(1)
+#define AWIN_CPUCFG_CPU_RST_CTRL_RESET __BIT(0)
+
+#define AWIN_CPUCFG_CPU_CTRL_CP15_WRITE_DISABLE __BIT(0)
+
+#define AWIN_CPUCFG_CPU_STATUS_STANDBYWFI __BIT(2)
+#define AWIN_CPUCFG_CPU_STATUS_STANDBYWFE __BIT(1)
+#define AWIN_CPUCFG_CPU_STATUS_SMP_AMP __BIT(0)
+
#define AWIN_PLL1_CFG_REG 0x0000
#define AWIN_PLL1_TUN_REG 0x0004
#define AWIN_PLL2_CFG_REG 0x0008
