Module Name: src
Committed By: matt
Date: Mon Apr 14 20:53:28 UTC 2014
Modified Files:
src/sys/arch/evbarm/marvell: marvell_start.S
Log Message:
Add hook to set L2 cache to write-through
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbarm/marvell/marvell_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/marvell/marvell_start.S
diff -u src/sys/arch/evbarm/marvell/marvell_start.S:1.5 src/sys/arch/evbarm/marvell/marvell_start.S:1.6
--- src/sys/arch/evbarm/marvell/marvell_start.S:1.5 Wed Jan 29 04:27:26 2014
+++ src/sys/arch/evbarm/marvell/marvell_start.S Mon Apr 14 20:53:28 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: marvell_start.S,v 1.5 2014/01/29 04:27:26 kiyohara Exp $ */
+/* $NetBSD: marvell_start.S,v 1.6 2014/04/14 20:53:28 matt Exp $ */
/*
* Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
* All rights reserved.
@@ -66,7 +66,7 @@
#include <evbarm/marvell/marvellreg.h>
#include "assym.h"
-RCSID("$NetBSD: marvell_start.S,v 1.5 2014/01/29 04:27:26 kiyohara Exp $")
+RCSID("$NetBSD: marvell_start.S,v 1.6 2014/04/14 20:53:28 matt Exp $")
#ifndef SDRAM_START
#define SDRAM_START 0x00000000
@@ -124,6 +124,15 @@ sheeva_l2_disable:
mrc p15, 1, r5, c15, c1, 0 @ Get Marvell Extra Features Register
bic r5, r5, #0x00400000 @ disable L2 cache
mcr p15, 1, r5, c15, c1, 0
+
+#ifdef SHEEVA_L2_CACHE_WT
+ /* L2 WT Mode */
+ ldr r2, =0xf1020128 /* CPU L2 Configuration Register */
+ ldr r3, [r2]
+ bic r3, r3, #0x10 /* Force Write Through */
+ str r3, [r2]
+#endif
+
1:
/* save u-boot's args */
