Module Name: src
Committed By: jmcneill
Date: Thu Sep 11 00:50:39 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
add some HDMI regs
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.23 src/sys/arch/arm/allwinner/awin_reg.h:1.24
--- src/sys/arch/arm/allwinner/awin_reg.h:1.23 Mon Sep 8 11:06:03 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Thu Sep 11 00:50:39 2014
@@ -872,6 +872,10 @@ struct awin_mmc_idma_descriptor {
#define AWIN_PLL6_PLL_BIAS __BITS(24,20)
#define AWIN_PLL6_CFG_SATA_CLK_EN __BIT(14)
+#define AWIN_PLL7_MODE_SEL __BIT(15)
+#define AWIN_PLL7_FRAC_SET __BIT(14)
+#define AWIN_PLL7_FACTOR_M __BITS(6,0)
+
#define AWIN_CPU_CLK_SRC_SEL __BITS(17,16)
#define AWIN_CPU_CLK_SRC_SEL_LOSC 0
#define AWIN_CPU_CLK_SRC_SEL_OSC24M 1
@@ -1005,6 +1009,13 @@ struct awin_mmc_idma_descriptor {
#define AWIN_GMAC_CLK_TCS_EXT_125 1
#define AWIN_GMAC_CLK_TCS_INT_RGMII 2
+#define AWIN_HDMI_CLK_SRC_SEL __BITS(25,24)
+#define AWIN_HDMI_CLK_SRC_SEL_PLL3 0
+#define AWIN_HDMI_CLK_SRC_SEL_PLL7 1
+#define AWIN_HDMI_CLK_SRC_SEL_PLL3_2X 2
+#define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X 3
+#define AWIN_HDMI_CLK_DIV_RATIO_M __BITS(3,0)
+
#define AWIN_CLK_OUT_ENABLE __BIT(31)
#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
#define AWIN_CLK_OUT_SRC_SEL_32K 0
@@ -1448,4 +1459,187 @@ struct awin_mmc_idma_descriptor {
#define AWIN_HSTMR_TMR3_CURNT_LO_REG 0x007c
#define AWIN_HSTMR_TMR3_CURNT_HI_REG 0x0080
+/* HDMI */
+#define AWIN_HDMI_VERSION_ID_REG 0x0000
+#define AWIN_HDMI_CTRL_REG 0x0004
+#define AWIN_HDMI_INT_STATUS_REG 0x0008
+#define AWIN_HDMI_HPD_REG 0x000c
+#define AWIN_HDMI_VID_CTRL_REG 0x0010
+#define AWIN_HDMI_VID_TIMING_0_REG 0x0014
+#define AWIN_HDMI_VID_TIMING_1_REG 0x0018
+#define AWIN_HDMI_VID_TIMING_2_REG 0x001c
+#define AWIN_HDMI_VID_TIMING_3_REG 0x0020
+#define AWIN_HDMI_VID_TIMING_4_REG 0x0024
+#define AWIN_HDMI_AUD_CTRL_REG 0x0040
+#define AWIN_HDMI_ADMA_CTRL_REG 0x0044
+#define AWIN_HDMI_AUD_FMT_REG 0x0048
+#define AWIN_HDMI_AUD_PCM_CTRL_REG 0x004c
+#define AWIN_HDMI_AUD_CTS_REG 0x0050
+#define AWIN_HDMI_AUD_N_REG 0x0054
+#define AWIN_HDMI_AUD_CH_STATUS0_REG 0x0058
+#define AWIN_HDMI_AUD_CH_STATUS1_REG 0x005c
+#define AWIN_HDMI_AVI_INFO_PKT_REG 0x0080
+#define AWIN_HDMI_AUD_INFO_PKT_REG 0x00a0
+#define AWIN_HDMI_ACP_PKT_REG 0x00c0
+#define AWIN_HDMI_GP_PKT_REG 0x00e0
+#define AWIN_HDMI_PAD_CTRL0_REG 0x0200
+#define AWIN_HDMI_PAD_CTRL1_REG 0x0204
+#define AWIN_HDMI_PLL_CTRL_REG 0x0208
+#define AWIN_HDMI_PLL_DBG0_REG 0x020c
+#define AWIN_HDMI_PLL_DBG1_REG 0x0210
+#define AWIN_HDMI_HPD_CEC_REG 0x0214
+#define AWIN_HDMI_SPD_PKT_REG 0x0240
+#define AWIN_HDMI_PKT_CTRL0_REG 0x02f0
+#define AWIN_HDMI_PKT_CTRL1_REG 0x02f4
+#define AWIN_HDMI_DBG4_REG 0x0310
+#define AWIN_HDMI_AUX_TX_FIFO_REG 0x0400
+#define AWIN_HDMI_DDC_CTRL_REG 0x0500
+#define AWIN_HDMI_DDC_SLAVE_ADDR_REG 0x0504
+#define AWIN_HDMI_DDC_INT_MASK_REG 0x0508
+#define AWIN_HDMI_DDC_INT_STATUS_REG 0x050c
+#define AWIN_HDMI_DDC_FIFO_CTRL_REG 0x0510
+#define AWIN_HDMI_DDC_FIFO_STATUS_REG 0x0514
+#define AWIN_HDMI_DDC_FIFO_ACCESS_REG 0x0518
+#define AWIN_HDMI_DDC_BYTE_COUNTER_REG 0x051c
+#define AWIN_HDMI_DDC_COMMAND_REG 0x0520
+#define AWIN_HDMI_DDC_EX_REG 0x0524
+#define AWIN_HDMI_DDC_CLOCK_REG 0x0528
+#define AWIN_HDMI_DDC_DBG_REG 0x0540
+
+#define AWIN_HDMI_VERSION_ID_H __BITS(31,16)
+#define AWIN_HDMI_VERSION_ID_L __BITS(15,0)
+
+#define AWIN_HDMI_CTRL_MODULE_EN __BIT(31)
+#define AWIN_HDMI_CTRL_HDCP_EN __BIT(30)
+#define AWIN_HDMI_CTRL_CLR_AVMUTE __BIT(1)
+#define AWIN_HDMI_CTRL_SET_AVMUTE __BIT(0)
+
+#define AWIN_HDMI_HPD_HOTPLUG_DET __BIT(0)
+
+#define AWIN_HDMI_VID_CTRL_VIDEO_EN __BIT(31)
+#define AWIN_HDMI_VID_CTRL_HDMI_MODE __BIT(30)
+#define AWIN_HDMI_VID_CTRL_HDMI_MODE_DVI 0
+#define AWIN_HDMI_VID_CTRL_HDMI_MODE_HDMI 1
+#define AWIN_HDMI_VID_CTRL_SRC_SEL __BIT(5)
+#define AWIN_HDMI_VID_CTRL_SRC_SEL_RGB 0
+#define AWIN_HDMI_VID_CTRL_SRC_SEL_CBGEN 1
+#define AWIN_HDMI_VID_CTRL_OUTPUT_FMT __BIT(4)
+#define AWIN_HDMI_VID_CTRL_OUTPUT_FMT_PROGRESS 0
+#define AWIN_HDMI_VID_CTRL_OUTPUT_FMT_INTERLACE 1
+#define AWIN_HDMI_VID_CTRL_COLOR_MODE __BITS(3,2)
+#define AWIN_HDMI_VID_CTRL_COLOR_MODE_24 0
+#define AWIN_HDMI_VID_CTRL_COLOR_MODE_30 1
+#define AWIN_HDMI_VID_CTRL_COLOR_MODE_36 2
+#define AWIN_HDMI_VID_CTRL_COLOR_MODE_48 3
+#define AWIN_HDMI_VID_CTRL_REPEATER_SEL __BITS(1,0)
+#define AWIN_HDMI_VID_CTRL_REPEATER_SEL_NORMAL 0
+#define AWIN_HDMI_VID_CTRL_REPEATER_SEL_2X 1
+#define AWIN_HDMI_VID_CTRL_REPEATER_SEL_4X 2
+
+#define AWIN_HDMI_VID_TIMING_0_ACT_V __BITS(27,16)
+#define AWIN_HDMI_VID_TIMING_0_ACT_H __BITS(11,0)
+
+#define AWIN_HDMI_VID_TIMING_1_VBP __BITS(27,16)
+#define AWIN_HDMI_VID_TIMING_1_HBP __BITS(11,0)
+
+#define AWIN_HDMI_VID_TIMING_2_VFP __BITS(27,16)
+#define AWIN_HDMI_VID_TIMING_2_HFP __BITS(11,0)
+
+#define AWIN_HDMI_VID_TIMING_3_VSPW __BITS(27,16)
+#define AWIN_HDMI_VID_TIMING_3_HSPW __BITS(11,0)
+
+#define AWIN_HDMI_VID_TIMING_4_TX_CLOCK __BITS(25,16)
+#define AWIN_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL __BIT(1)
+#define AWIN_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL __BIT(0)
+
+#define AWIN_HDMI_PAD_CTRL0_BIAS __BIT(31)
+#define AWIN_HDMI_PAD_CTRL0_LDOCEN __BIT(30)
+#define AWIN_HDMI_PAD_CTRL0_LD0DEN __BIT(29)
+#define AWIN_HDMI_PAD_CTRL0_PWENC __BIT(28)
+#define AWIN_HDMI_PAD_CTRL0_PWEND __BIT(27)
+#define AWIN_HDMI_PAD_CTRL0_PWENG __BIT(26)
+#define AWIN_HDMI_PAD_CTRL0_CKEN __BIT(25)
+#define AWIN_HDMI_PAD_CTRL0_SEN __BIT(24)
+#define AWIN_HDMI_PAD_CTRL0_TXEN __BIT(23)
+#define AWIN_HDMI_PAD_CTRL0_AUTOSYNC_DIS __BIT(22)
+#define AWIN_HDMI_PAD_CTRL0_LSB_MSB __BIT(21)
+
+#define AWIN_HDMI_PAD_CTRL1_AMP_OPT __BIT(23)
+#define AWIN_HDMI_PAD_CTRL1_AMPCK_OPT __BIT(22)
+#define AWIN_HDMI_PAD_CTRL1_DMP_OPT __BIT(21)
+#define AWIN_HDMI_PAD_CTRL1_EMP_OPT __BIT(20)
+#define AWIN_HDMI_PAD_CTRL1_EMPCK_OPT __BIT(19)
+#define AWIN_HDMI_PAD_CTRL1_PWSCK __BIT(18)
+#define AWIN_HDMI_PAD_CTRL1_PWSDT __BIT(17)
+#define AWIN_HDMI_PAD_CTRL1_REG_CSMPS __BIT(16)
+#define AWIN_HDMI_PAD_CTRL1_REG_DEN __BIT(15)
+#define AWIN_HDMI_PAD_CTRL1_REG_DENCK __BIT(14)
+#define AWIN_HDMI_PAD_CTRL1_REG_PLRCK __BIT(13)
+#define AWIN_HDMI_PAD_CTRL1_REG_EMP __BITS(12,10)
+#define AWIN_HDMI_PAD_CTRL1_REG_CD __BITS(9,8)
+#define AWIN_HDMI_PAD_CTRL1_REG_CKSS __BITS(7,6)
+#define AWIN_HDMI_PAD_CTRL1_REG_AMP __BITS(5,3)
+#define AWIN_HDMI_PAD_CTRL1_REG_PLR __BITS(2,0)
+
+#define AWIN_HDMI_PLL_CTRL_PLL_EN __BIT(31)
+#define AWIN_HDMI_PLL_CTRL_BWS __BIT(30)
+#define AWIN_HDMI_PLL_CTRL_HV_IS_33 __BIT(29)
+#define AWIN_HDMI_PLL_CTRL_LDO1_EN __BIT(28)
+#define AWIN_HDMI_PLL_CTRL_LDO2_EN __BIT(27)
+#define AWIN_HDMI_PLL_CTRL_S6P25_7P5 __BIT(26)
+#define AWIN_HDMI_PLL_CTRL_SDIV2 __BIT(25)
+#define AWIN_HDMI_PLL_CTRL_SINT_FRAC __BIT(24)
+#define AWIN_HDMI_PLL_CTRL_VCO_GAIN_EN __BIT(23)
+#define AWIN_HDMI_PLL_CTRL_VCO_GAIN __BITS(22,20)
+#define AWIN_HDMI_PLL_CTRL_S __BITS(19,17)
+#define AWIN_HDMI_PLL_CTRL_CP_S __BITS(16,12)
+#define AWIN_HDMI_PLL_CTRL_CS __BITS(11,8)
+#define AWIN_HDMI_PLL_CTRL_PREDIV __BITS(7,4)
+#define AWIN_HDMI_PLL_CTRL_VCO_S __BITS(3,0)
+
+#define AWIN_HDMI_DDC_CTRL_EN __BIT(31)
+#define AWIN_HDMI_DDC_CTRL_ACCESS_CMD_START __BIT(30)
+#define AWIN_HDMI_DDC_CTRL_FIFO_DIR __BIT(8)
+#define AWIN_HDMI_DDC_CTRL_FIFO_DIR_READ 0
+#define AWIN_HDMI_DDC_CTRL_FIFO_DIR_WRITE 1
+#define AWIN_HDMI_DDC_CTRL_SW_RST __BIT(0)
+
+#define AWIN_HDMI_DDC_SLAVE_ADDR_0 __BITS(31,24)
+#define AWIN_HDMI_DDC_SLAVE_ADDR_1 __BITS(23,16)
+#define AWIN_HDMI_DDC_SLAVE_ADDR_2 __BITS(15,8)
+#define AWIN_HDMI_DDC_SLAVE_ADDR_3 __BITS(6,0)
+
+#define AWIN_HDMI_DDC_INT_STATUS_CLEAR __BIT(8)
+#define AWIN_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OP __BIT(7)
+#define AWIN_HDMI_DDC_INT_STATUS_RX_UNDERFLOW __BIT(6)
+#define AWIN_HDMI_DDC_INT_STATUS_TX_OVERFLOW __BIT(5)
+#define AWIN_HDMI_DDC_INT_STATUS_FIFO_REQ __BIT(4)
+#define AWIN_HDMI_DDC_INT_STATUS_ARB_ERR __BIT(3)
+#define AWIN_HDMI_DDC_INT_STATUS_ACK_ERR __BIT(2)
+#define AWIN_HDMI_DDC_INT_STATUS_BUS_ERR __BIT(1)
+#define AWIN_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE __BIT(0)
+
+#define AWIN_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR __BIT(31)
+#define AWIN_HDMI_DDC_FIFO_CTRL_REQUEST_EN __BIT(8)
+#define AWIN_HDMI_DDC_FIFO_CTRL_RX_TRIGGER_THRESH __BITS(7,4)
+#define AWIN_HDMI_DDC_FIFO_CTRL_TX_TRIGGER_THRESH __BITS(3,0)
+
+#define AWIN_HDMI_DDC_FIFO_STATUS_REQ_READY __BIT(7)
+#define AWIN_HDMI_DDC_FIFO_STATUS_FULL __BIT(6)
+#define AWIN_HDMI_DDC_FIFO_STATUS_EMPTY __BIT(5)
+#define AWIN_HDMI_DDC_FIFO_STATUS_LEVEL __BITS(4,0)
+
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD __BITS(2,0)
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_ABORT 0
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_SOREAD 1
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_EOWRITE 2
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_IOWRITE 3
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_EOREAD 4
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_IOREAD 5
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_EOEDDCREAD 6
+#define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_IOEDDCREAD 7
+
+#define AWIN_HDMI_DDC_CLOCK_M __BITS(6,3)
+#define AWIN_HDMI_DDC_CLOCK_N __BITS(2,0)
+
#endif /* _ARM_ALLWINNER_AWIN_REG_H_ */
