Module Name: src
Committed By: jmcneill
Date: Fri Oct 3 11:21:56 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
add some more bit definitions
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.25 src/sys/arch/arm/allwinner/awin_reg.h:1.26
--- src/sys/arch/arm/allwinner/awin_reg.h:1.25 Sat Sep 13 17:48:00 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Fri Oct 3 11:21:56 2014
@@ -867,6 +867,10 @@ struct awin_mmc_idma_descriptor {
#define AWIN_PLL2_CFG_FACTOR_N __BITS(14,8)
#define AWIN_PLL2_CFG_PREVDIV __BITS(4,0)
+#define AWIN_PLL3_MODE_SEL __BIT(15)
+#define AWIN_PLL3_FRAC_SET __BIT(14)
+#define AWIN_PLL3_FACTOR_M __BITS(6,0)
+
#define AWIN_PLL5_CFG_DDR_CLK_EN __BIT(29)
#define AWIN_PLL5_CFG_LDO_EN __BIT(7)
#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
@@ -1012,6 +1016,14 @@ struct awin_mmc_idma_descriptor {
#define AWIN_GMAC_CLK_TCS_EXT_125 1
#define AWIN_GMAC_CLK_TCS_INT_RGMII 2
+#define AWIN_LCDx_CH0_CLK_LCDx_RST __BIT(30)
+#define AWIN_LCDx_CHx_CLK_SRC_SEL __BITS(25,24)
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL3 0
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL7 1
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL3_2X 2
+#define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL6_2 3
+#define AWIN_LCDx_CH1_CLK_DIV_RATIO_M __BITS(3,0)
+
#define AWIN_HDMI_CLK_SRC_SEL __BITS(25,24)
#define AWIN_HDMI_CLK_SRC_SEL_PLL3 0
#define AWIN_HDMI_CLK_SRC_SEL_PLL7 1
@@ -1019,6 +1031,9 @@ struct awin_mmc_idma_descriptor {
#define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X 3
#define AWIN_HDMI_CLK_DIV_RATIO_M __BITS(3,0)
+#define AWIN_SD_CLK_PHASE_CTR __BITS(22,20)
+#define AWIN_SD_CLK_OUTPUT_PHASE_CTR __BITS(10,8)
+
#define AWIN_CLK_OUT_ENABLE __BIT(31)
#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
#define AWIN_CLK_OUT_SRC_SEL_32K 0
@@ -1578,6 +1593,7 @@ struct awin_mmc_idma_descriptor {
#define AWIN_HDMI_VID_TIMING_3_HSPW __BITS(11,0)
#define AWIN_HDMI_VID_TIMING_4_TX_CLOCK __BITS(25,16)
+#define AWIN_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL 0x3e0
#define AWIN_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL __BIT(1)
#define AWIN_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL __BIT(0)
