Module Name: src
Committed By: martin
Date: Sun Nov 9 16:05:26 UTC 2014
Modified Files:
src/sys/arch/arm/arm [netbsd-7]: arm_machdep.c cpufunc_asm_arm11.S
cpufunc_asm_armv7.S cpufunc_asm_pj4b.S undefined.c
src/sys/arch/arm/arm32 [netbsd-7]: arm32_boot.c arm32_kvminit.c
arm32_machdep.c arm32_tlb.c db_interface.c db_machdep.c pmap.c
src/sys/arch/arm/cortex [netbsd-7]: a9_mpsubr.S gic.c
src/sys/arch/arm/include [netbsd-7]: armreg.h
src/sys/arch/arm/include/arm32 [netbsd-7]: pmap.h
src/sys/arch/arm/mainbus [netbsd-7]: cpu_mainbus.c
src/sys/arch/arm/pic [netbsd-7]: pic.c picvar.h
src/sys/arch/evbarm/conf [netbsd-7]: BPI CUBIETRUCK
src/sys/uvm/pmap [netbsd-7]: pmap_tlb.c
Log Message:
Pull up following revision(s) (requested by skrll in ticket #188):
sys/arch/arm/include/arm32/pmap.h: revision 1.136
sys/arch/arm/include/armreg.h: revision 1.100
sys/arch/arm/cortex/gic.c: revision 1.11
sys/arch/arm/arm32/db_interface.c: revision 1.54
sys/arch/arm/include/armreg.h: revision 1.101
sys/arch/arm/cortex/gic.c: revision 1.12
sys/arch/arm/arm32/arm32_machdep.c: revision 1.107
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20
sys/arch/evbarm/conf/BPI: revision 1.5
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21
sys/arch/arm/arm32/pmap.c: revision 1.306
sys/arch/arm/arm32/db_machdep.c: revision 1.22
sys/arch/arm/arm32/arm32_tlb.c: revision 1.3
sys/arch/arm/arm/undefined.c: revision 1.55
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22
sys/arch/arm/arm32/pmap.c: revision 1.307
sys/arch/arm/arm32/arm32_tlb.c: revision 1.4
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23
sys/arch/arm/arm32/arm32_tlb.c: revision 1.5
sys/arch/evbarm/conf/BPI: revision 1.8
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24
sys/arch/arm/arm32/arm32_tlb.c: revision 1.6
sys/arch/arm/arm32/arm32_tlb.c: revision 1.7
sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5
sys/arch/arm/pic/pic.c: revision 1.23
sys/arch/arm/pic/pic.c: revision 1.24
sys/arch/arm/pic/picvar.h: revision 1.11
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20
sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16
sys/arch/arm/arm32/pmap.c: revision 1.298
sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17
sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5
sys/arch/arm/arm32/pmap.c: revision 1.310
sys/arch/arm/arm32/pmap.c: revision 1.311
sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19
sys/arch/arm/arm32/arm32_boot.c: revision 1.10
sys/arch/arm/arm/ast.c: revision 1.25
sys/arch/arm/include/armreg.h: revision 1.98
sys/uvm/pmap/pmap_tlb.c: revision 1.10
sys/arch/arm/arm32/arm32_boot.c: revision 1.8
sys/arch/arm/arm32/arm32_boot.c: revision 1.9
sys/arch/arm/arm/arm_machdep.c: revision 1.43
Various ARM MP fixes.
To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.42.2.1 src/sys/arch/arm/arm/arm_machdep.c
cvs rdiff -u -r1.15 -r1.15.2.1 src/sys/arch/arm/arm/cpufunc_asm_arm11.S
cvs rdiff -u -r1.18 -r1.18.2.1 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
cvs rdiff -u -r1.4 -r1.4.6.1 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
cvs rdiff -u -r1.54 -r1.54.4.1 src/sys/arch/arm/arm/undefined.c
cvs rdiff -u -r1.7 -r1.7.4.1 src/sys/arch/arm/arm32/arm32_boot.c
cvs rdiff -u -r1.30 -r1.30.2.1 src/sys/arch/arm/arm32/arm32_kvminit.c
cvs rdiff -u -r1.105 -r1.105.2.1 src/sys/arch/arm/arm32/arm32_machdep.c
cvs rdiff -u -r1.2 -r1.2.6.1 src/sys/arch/arm/arm32/arm32_tlb.c
cvs rdiff -u -r1.52 -r1.52.4.1 src/sys/arch/arm/arm32/db_interface.c
cvs rdiff -u -r1.21 -r1.21.4.1 src/sys/arch/arm/arm32/db_machdep.c
cvs rdiff -u -r1.295.2.1 -r1.295.2.2 src/sys/arch/arm/arm32/pmap.c
cvs rdiff -u -r1.18 -r1.18.2.1 src/sys/arch/arm/cortex/a9_mpsubr.S
cvs rdiff -u -r1.10 -r1.10.2.1 src/sys/arch/arm/cortex/gic.c
cvs rdiff -u -r1.97 -r1.97.2.1 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.135 -r1.135.2.1 src/sys/arch/arm/include/arm32/pmap.h
cvs rdiff -u -r1.15 -r1.15.2.1 src/sys/arch/arm/mainbus/cpu_mainbus.c
cvs rdiff -u -r1.22 -r1.22.2.1 src/sys/arch/arm/pic/pic.c
cvs rdiff -u -r1.10 -r1.10.2.1 src/sys/arch/arm/pic/picvar.h
cvs rdiff -u -r1.2.2.2 -r1.2.2.3 src/sys/arch/evbarm/conf/BPI
cvs rdiff -u -r1.2.4.1 -r1.2.4.2 src/sys/arch/evbarm/conf/CUBIETRUCK
cvs rdiff -u -r1.8 -r1.8.4.1 src/sys/uvm/pmap/pmap_tlb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.42 src/sys/arch/arm/arm/arm_machdep.c:1.42.2.1
--- src/sys/arch/arm/arm/arm_machdep.c:1.42 Sat Jun 14 09:13:30 2014
+++ src/sys/arch/arm/arm/arm_machdep.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.42 2014/06/14 09:13:30 ozaki-r Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.42.2.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -75,10 +75,11 @@
#include "opt_cpuoptions.h"
#include "opt_cputypes.h"
#include "opt_arm_debug.h"
+#include "opt_multiprocessor.h"
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.42 2014/06/14 09:13:30 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.42.2.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/exec.h>
#include <sys/proc.h>
Index: src/sys/arch/arm/arm/cpufunc_asm_arm11.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm11.S:1.15 src/sys/arch/arm/arm/cpufunc_asm_arm11.S:1.15.2.1
--- src/sys/arch/arm/arm/cpufunc_asm_arm11.S:1.15 Thu Jul 31 10:44:58 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm11.S Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm11.S,v 1.15 2014/07/31 10:44:58 skrll Exp $ */
+/* $NetBSD: cpufunc_asm_arm11.S,v 1.15.2.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@@ -99,7 +99,8 @@ END(arm11_tlb_flushI)
ENTRY(arm11_tlb_flushI_SE)
#ifdef ARM_MMU_EXTENDED
- orr r0, r0, r1 /* insert ASID into MVA */
+ bic r0, r0, #0xff
+ bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
#endif
mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
#if PAGE_SIZE == 2 * L2_S_SIZE
@@ -121,7 +122,8 @@ END(arm11_tlb_flushD)
ENTRY(arm11_tlb_flushD_SE)
#ifdef ARM_MMU_EXTENDED
- orr r0, r0, r1 /* insert ASID into MVA */
+ bic r0, r0, #0xff
+ bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
#endif
mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
#if PAGE_SIZE == 2 * L2_S_SIZE
@@ -142,7 +144,8 @@ END(arm11_tlb_flushID)
ENTRY(arm11_tlb_flushID_SE)
#ifdef ARM_MMU_EXTENDED
- orr r0, r0, r1 /* insert ASID into MVA */
+ bic r0, r0, #0xff
+ bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
#endif
mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
#if PAGE_SIZE == 2 * L2_S_SIZE
Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.18 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.18.2.1
--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.18 Thu Jul 31 06:26:06 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Sun Nov 9 16:05:25 2014
@@ -78,10 +78,7 @@ END(armv7_tlb_flushID_ASID)
STRONG_ALIAS(armv7_tlb_flushD_SE, armv7_tlb_flushID_SE)
STRONG_ALIAS(armv7_tlb_flushI_SE, armv7_tlb_flushID_SE)
ENTRY(armv7_tlb_flushID_SE)
- bfc r0, #0, #12 @ clear ASID
-#ifdef ARM_MMU_EXTENDED
- bfi r0, r1, #0, #8 @ insert ASID into MVA
-#endif
+ bfc r0, #0, #12 @ Always KERNEL_PID, i.e. 0
#ifdef MULTIPROCESSOR
mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry
#if PAGE_SIZE == 2*L2_S_SIZE
@@ -380,6 +377,7 @@ ENTRY_NP(armv7_dcache_inv_all)
b 1b
.Lnext_level_inv:
+ dsb
mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
ubfx ip, r0, #24, #3 @ narrow to LoC
add r3, r3, #2 @ go to next level
@@ -440,6 +438,7 @@ ENTRY_NP(armv7_dcache_wbinv_all)
b 1b
.Lnext_level_wbinv:
+ dsb
mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
ubfx ip, r0, #24, #3 @ narrow to LoC
add r3, r3, #2 @ go to next level
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.4 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.4.6.1
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.4 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.4 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.4.6.1 2014/11/09 16:05:25 martin Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -78,6 +78,7 @@ ENTRY(pj4b_tlb_flushID)
END(pj4b_tlb_flushID)
ENTRY(pj4b_tlb_flushID_SE)
+ bfc r0, #0, #12 @ always KERNEL_PID (i.e. 0)
mcr p15, 0, r0, c8, c7, 1 @flush I+D tlb single entry
#if PAGE_SIZE == 2 * L2_S_SIZE
add r0, r0, L2_S_SIZE
Index: src/sys/arch/arm/arm/undefined.c
diff -u src/sys/arch/arm/arm/undefined.c:1.54 src/sys/arch/arm/arm/undefined.c:1.54.4.1
--- src/sys/arch/arm/arm/undefined.c:1.54 Fri Mar 28 21:44:35 2014
+++ src/sys/arch/arm/arm/undefined.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: undefined.c,v 1.54 2014/03/28 21:44:35 matt Exp $ */
+/* $NetBSD: undefined.c,v 1.54.4.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@@ -55,7 +55,7 @@
#include <sys/kgdb.h>
#endif
-__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.54 2014/03/28 21:44:35 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.54.4.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/kmem.h>
#include <sys/queue.h>
@@ -102,7 +102,8 @@ install_coproc_handler(int coproc, undef
KASSERT(coproc >= 0 && coproc < NUM_UNKNOWN_HANDLERS);
KASSERT(handler != NULL); /* Used to be legal. */
- uh = kmem_alloc(sizeof(*uh), KM_SLEEP);
+ uh = kmem_alloc(sizeof(*uh), KM_NOSLEEP);
+ KASSERT(uh != NULL);
uh->uh_handler = handler;
install_coproc_handler_static(coproc, uh);
return uh;
Index: src/sys/arch/arm/arm32/arm32_boot.c
diff -u src/sys/arch/arm/arm32/arm32_boot.c:1.7 src/sys/arch/arm/arm32/arm32_boot.c:1.7.4.1
--- src/sys/arch/arm/arm32/arm32_boot.c:1.7 Fri Mar 28 21:39:09 2014
+++ src/sys/arch/arm/arm32/arm32_boot.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_boot.c,v 1.7 2014/03/28 21:39:09 matt Exp $ */
+/* $NetBSD: arm32_boot.c,v 1.7.4.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@@ -123,10 +123,11 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.7 2014/03/28 21:39:09 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.7.4.1 2014/11/09 16:05:25 martin Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
+#include "opt_multiprocessor.h"
#include <sys/param.h>
#include <sys/reboot.h>
@@ -351,13 +352,13 @@ cpu_hatch(struct cpu_info *ci, cpuid_t c
printf(" stacks");
#endif
set_stackptr(PSR_FIQ32_MODE,
- fiqstack.pv_va + cpu_index(ci) * FIQ_STACK_SIZE * PAGE_SIZE);
+ fiqstack.pv_va + (cpu_index(ci) + 1) * FIQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_IRQ32_MODE,
- irqstack.pv_va + cpu_index(ci) * IRQ_STACK_SIZE * PAGE_SIZE);
+ irqstack.pv_va + (cpu_index(ci) + 1) * IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
- abtstack.pv_va + cpu_index(ci) * ABT_STACK_SIZE * PAGE_SIZE);
+ abtstack.pv_va + (cpu_index(ci) + 1) * ABT_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_UND32_MODE,
- undstack.pv_va + cpu_index(ci) * UND_STACK_SIZE * PAGE_SIZE);
+ undstack.pv_va + (cpu_index(ci) + 1) * UND_STACK_SIZE * PAGE_SIZE);
ci->ci_lastlwp = NULL;
ci->ci_pmap_lastuser = NULL;
@@ -408,6 +409,7 @@ cpu_hatch(struct cpu_info *ci, cpuid_t c
printf(" done!\n");
#endif
atomic_and_32(&arm_cpu_mbox, ~(1 << cpuid));
+ membar_producer();
__asm __volatile("sev; sev; sev");
}
#endif /* MULTIPROCESSOR */
Index: src/sys/arch/arm/arm32/arm32_kvminit.c
diff -u src/sys/arch/arm/arm32/arm32_kvminit.c:1.30 src/sys/arch/arm/arm32/arm32_kvminit.c:1.30.2.1
--- src/sys/arch/arm/arm32/arm32_kvminit.c:1.30 Fri May 23 13:24:15 2014
+++ src/sys/arch/arm/arm32/arm32_kvminit.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_kvminit.c,v 1.30 2014/05/23 13:24:15 kiyohara Exp $ */
+/* $NetBSD: arm32_kvminit.c,v 1.30.2.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@@ -121,8 +121,10 @@
* SUCH DAMAGE.
*/
+#include "opt_multiprocessor.h"
+
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_kvminit.c,v 1.30 2014/05/23 13:24:15 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_kvminit.c,v 1.30.2.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/param.h>
#include <sys/device.h>
Index: src/sys/arch/arm/arm32/arm32_machdep.c
diff -u src/sys/arch/arm/arm32/arm32_machdep.c:1.105 src/sys/arch/arm/arm32/arm32_machdep.c:1.105.2.1
--- src/sys/arch/arm/arm32/arm32_machdep.c:1.105 Mon May 19 22:47:53 2014
+++ src/sys/arch/arm/arm32/arm32_machdep.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_machdep.c,v 1.105 2014/05/19 22:47:53 rmind Exp $ */
+/* $NetBSD: arm32_machdep.c,v 1.105.2.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -42,11 +42,12 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.105 2014/05/19 22:47:53 rmind Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.105.2.1 2014/11/09 16:05:25 martin Exp $");
#include "opt_modular.h"
#include "opt_md.h"
#include "opt_pmap_debug.h"
+#include "opt_multiprocessor.h"
#include <sys/param.h>
#include <sys/systm.h>
Index: src/sys/arch/arm/arm32/arm32_tlb.c
diff -u src/sys/arch/arm/arm32/arm32_tlb.c:1.2 src/sys/arch/arm/arm32/arm32_tlb.c:1.2.6.1
--- src/sys/arch/arm/arm32/arm32_tlb.c:1.2 Fri Apr 11 02:39:03 2014
+++ src/sys/arch/arm/arm32/arm32_tlb.c Sun Nov 9 16:05:25 2014
@@ -26,8 +26,11 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+
+#include "opt_multiprocessor.h"
+
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.2 2014/04/11 02:39:03 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.2.6.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -48,8 +51,9 @@ void
tlb_set_asid(tlb_asid_t asid)
{
arm_dsb();
- if (asid == 0) {
+ if (asid == KERNEL_PID) {
armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0);
+ arm_isb();
}
armreg_contextidr_write(asid);
arm_isb();
@@ -60,7 +64,11 @@ tlb_invalidate_all(void)
{
const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
arm_dsb();
+#ifdef MULTIPROCESSOR
+ armreg_tlbiallis_write(0);
+#else
armreg_tlbiall_write(0);
+#endif
arm_isb();
if (__predict_false(vivt_icache_p)) {
if (arm_has_tlbiasid_p) {
@@ -85,7 +93,7 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_
arm_dsb();
if (arm_has_tlbiasid_p) {
for (; lo <= hi; lo++) {
- armreg_tlbiasid_write(lo);
+ armreg_tlbiasidis_write(lo);
}
arm_isb();
if (__predict_false(vivt_icache_p)) {
@@ -107,7 +115,11 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid
arm_dsb();
va = trunc_page(va) | asid;
for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
+#ifdef MULTIPROCESSOR
+ armreg_tlbimvais_write(va);
+#else
armreg_tlbimva_write(va);
+#endif
//armreg_tlbiall_write(asid);
}
arm_isb();
Index: src/sys/arch/arm/arm32/db_interface.c
diff -u src/sys/arch/arm/arm32/db_interface.c:1.52 src/sys/arch/arm/arm32/db_interface.c:1.52.4.1
--- src/sys/arch/arm/arm32/db_interface.c:1.52 Sun Mar 30 08:00:34 2014
+++ src/sys/arch/arm/arm32/db_interface.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.52 2014/03/30 08:00:34 skrll Exp $ */
+/* $NetBSD: db_interface.c,v 1.52.4.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 1996 Scott K. Stevens
@@ -35,10 +35,11 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.52 2014/03/30 08:00:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.52.4.1 2014/11/09 16:05:25 martin Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
+#include "opt_multiprocessor.h"
#include <sys/param.h>
#include <sys/proc.h>
Index: src/sys/arch/arm/arm32/db_machdep.c
diff -u src/sys/arch/arm/arm32/db_machdep.c:1.21 src/sys/arch/arm/arm32/db_machdep.c:1.21.4.1
--- src/sys/arch/arm/arm32/db_machdep.c:1.21 Sun Mar 30 08:00:34 2014
+++ src/sys/arch/arm/arm32/db_machdep.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.21 2014/03/30 08:00:34 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.21.4.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
@@ -33,7 +33,7 @@
#endif
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.21 2014/03/30 08:00:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.21.4.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -337,7 +337,7 @@ tlb_print_cortex_a7_entry(size_t way, si
const u_int sh = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SH);
static const char is_types[3][3] = { "NC", "WB", "WT" };
static const char os_types[4][6] = { "NC", "WB+WA", "WT", "WB" };
- static const char sh_types[4][3] = { "NC", "na", "OS", "IS" };
+ static const char sh_types[4][3] = { "NS", "na", "OS", "IS" };
db_printf(" %2s %5s %2s\n", is_types[is], os_types[os], sh_types[sh]);
}
Index: src/sys/arch/arm/arm32/pmap.c
diff -u src/sys/arch/arm/arm32/pmap.c:1.295.2.1 src/sys/arch/arm/arm32/pmap.c:1.295.2.2
--- src/sys/arch/arm/arm32/pmap.c:1.295.2.1 Thu Oct 30 12:14:36 2014
+++ src/sys/arch/arm/arm32/pmap.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.295.2.1 2014/10/30 12:14:36 martin Exp $ */
+/* $NetBSD: pmap.c,v 1.295.2.2 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -216,7 +216,7 @@
#include <arm/locore.h>
//#include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.295.2.1 2014/10/30 12:14:36 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.295.2.2 2014/11/09 16:05:25 martin Exp $");
//#define PMAP_DEBUG
#ifdef PMAP_DEBUG
@@ -1312,7 +1312,7 @@ pmap_alloc_l1(pmap_t pm)
KASSERTMSG(kernel_map != NULL, "pm %p", pm);
vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
UVM_KMF_WIRED|UVM_KMF_ZERO);
- KASSERT(!va);
+ KASSERT(va);
pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa);
#endif
pm->pm_l1 = (pd_entry_t *)va;
@@ -2506,11 +2506,14 @@ pmap_clearbit(struct vm_page_md *md, pad
}
if (npte != opte) {
- l2pte_set(ptep, npte, opte);
+ l2pte_reset(ptep);
PTE_SYNC(ptep);
/* Flush the TLB entry if a current pmap. */
pmap_tlb_flush_SE(pm, va, oflags);
+
+ l2pte_set(ptep, npte, 0);
+ PTE_SYNC(ptep);
}
pmap_release_pmap_lock(pm);
@@ -2665,6 +2668,9 @@ pmap_syncicache_page(struct vm_page_md *
for (size_t i = 0, j = 0; i < way_size;
i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) {
+ l2pte_reset(ptep + j);
+ PTE_SYNC(ptep + j);
+
pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC);
/*
* Set up a PTE with to flush these cache lines.
@@ -2893,10 +2899,6 @@ pmap_page_remove(struct vm_page_md *md,
pmap_release_page_lock(md);
pmap_acquire_pmap_lock(pm);
-#ifdef ARM_MMU_EXTENDED
- pmap_tlb_invalidate_addr(pm, pv->pv_va);
-#endif
-
l2b = pmap_get_l2_bucket(pm, pv->pv_va);
KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va);
@@ -2918,7 +2920,14 @@ pmap_page_remove(struct vm_page_md *md,
*/
l2pte_reset(ptep);
PTE_SYNC_CURRENT(pm, ptep);
+
+#ifdef ARM_MMU_EXTENDED
+ /* XXXNH pmap_tlb_flush_SE()? */
+ pmap_tlb_invalidate_addr(pm, pv->pv_va);
+#endif
+
pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE);
+
pmap_release_pmap_lock(pm);
pool_put(&pmap_pv_pool, pv);
@@ -3317,8 +3326,12 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
* identical, so there's no need to update the page table.
*/
if (npte != opte) {
-
- l2pte_set(ptep, npte, opte);
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
+ if (l2pte_valid_p(opte)) {
+ pmap_tlb_flush_SE(pm, va, oflags);
+ }
+ l2pte_set(ptep, npte, 0);
PTE_SYNC(ptep);
#ifndef ARM_MMU_EXTENDED
bool is_cached = pmap_is_cached(pm);
@@ -3346,8 +3359,6 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
}
#endif /* !ARMM_MMU_EXTENDED */
- pmap_tlb_flush_SE(pm, va, oflags);
-
#ifndef ARM_MMU_EXTENDED
UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n",
is_cached, pm->pm_cstate.cs_all, 0, 0);
@@ -3491,6 +3502,7 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
*/
l2pte_reset(ptep);
PTE_SYNC_CURRENT(pm, ptep);
+ pmap_tlb_flush_SE(pm, sva, flags);
continue;
}
@@ -3498,7 +3510,7 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
if (pm == pmap_kernel()) {
l2pte_reset(ptep);
PTE_SYNC(ptep);
- pmap_tlb_flush_SE(pm, sva, flags);
+ pmap_tlb_flush_SE(pm, sva, flags);
continue;
}
#endif
@@ -3541,6 +3553,8 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) {
total += cleanlist_idx;
for (cnt = 0; cnt < cleanlist_idx; cnt++) {
+ l2pte_reset(cleanlist[cnt].ptep);
+ PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep);
#ifdef ARM_MMU_EXTENDED
vaddr_t clva = cleanlist[cnt].va;
pmap_tlb_flush_SE(pm, clva, PVF_REF);
@@ -3557,8 +3571,6 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
PVF_REF | flags);
}
#endif /* ARM_MMU_EXTENDED */
- l2pte_reset(cleanlist[cnt].ptep);
- PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep);
}
/*
@@ -3692,6 +3704,8 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, v
}
#endif
if (l2pte_valid_p(opte)) {
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
#ifdef PMAP_CACHE_VIVT
cpu_dcache_wbinv_range(va, PAGE_SIZE);
#endif
@@ -3709,7 +3723,7 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, v
if (prot & VM_PROT_EXECUTE)
npte &= ~L2_XS_XN;
#endif
- l2pte_set(ptep, npte, opte);
+ l2pte_set(ptep, npte, 0);
PTE_SYNC(ptep);
if (pg) {
@@ -3798,7 +3812,8 @@ pmap_kremove(vaddr_t va, vsize_t len)
if (next_bucket > eva)
next_bucket = eva;
- struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va);
+ pmap_t kpm = pmap_kernel();
+ struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va);
KDASSERT(l2b != NULL);
pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)];
@@ -3833,13 +3848,13 @@ pmap_kremove(vaddr_t va, vsize_t len)
}
}
if (l2pte_valid_p(opte)) {
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
#ifdef PMAP_CACHE_VIVT
cpu_dcache_wbinv_range(va, PAGE_SIZE);
#endif
cpu_tlb_flushD_SE(va);
- }
- if (opte) {
- l2pte_reset(ptep);
+
mappings += PAGE_SIZE / L2_S_SIZE;
}
va += PAGE_SIZE;
@@ -3848,7 +3863,7 @@ pmap_kremove(vaddr_t va, vsize_t len)
KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u",
mappings, l2b->l2b_occupancy);
l2b->l2b_occupancy -= mappings;
- PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
+ //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
#ifdef UVMHIST
total_mappings += mappings;
#endif
@@ -3947,9 +3962,11 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad
pmap_acquire_pmap_lock(pm);
+#ifndef ARM_MMU_EXTENDED
const bool flush = eva - sva >= PAGE_SIZE * 4;
- u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC);
u_int flags = 0;
+#endif
+ u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC);
while (sva < eva) {
next_bucket = L2_NEXT_BUCKET_VA(sva);
@@ -3968,7 +3985,9 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad
const pt_entry_t opte = *ptep;
if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) {
struct vm_page *pg;
+#ifndef ARM_MMU_EXTENDED
u_int f;
+#endif
#ifdef PMAP_CACHE_VIVT
/*
@@ -3982,7 +4001,12 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad
pg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
pt_entry_t npte = l2pte_set_readonly(opte);
- l2pte_set(ptep, npte, opte);
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
+#ifdef ARM_MMU_EXTENDED
+ pmap_tlb_flush_SE(pm, sva, PVF_REF);
+#endif
+ l2pte_set(ptep, npte, 0);
PTE_SYNC(ptep);
if (pg != NULL) {
@@ -3990,10 +4014,14 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad
paddr_t pa = VM_PAGE_TO_PHYS(pg);
pmap_acquire_page_lock(md);
- f = pmap_modify_pv(md, pa, pm, sva,
- clr_mask, 0);
+#ifndef ARM_MMU_EXTENDED
+ f =
+#endif
+ pmap_modify_pv(md, pa, pm, sva,
+ clr_mask, 0);
pmap_vac_me_harder(md, pa, pm, sva);
pmap_release_page_lock(md);
+#ifndef ARM_MMU_EXTENDED
} else {
f = PVF_REF | PVF_EXEC;
}
@@ -4002,6 +4030,7 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad
flags |= f;
} else {
pmap_tlb_flush_SE(pm, sva, f);
+#endif
}
}
@@ -4010,6 +4039,7 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad
}
}
+#ifndef ARM_MMU_EXTENDED
if (flush) {
if (PV_BEEN_EXECD(flags)) {
pmap_tlb_flushID(pm);
@@ -4017,6 +4047,7 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad
pmap_tlb_flushD(pm);
}
}
+#endif
pmap_release_pmap_lock(pm);
}
@@ -4215,12 +4246,15 @@ pmap_prefetchabt_fixup(void *v)
KASSERT(pv != NULL);
if (PV_IS_EXEC_P(pv->pv_flags)) {
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
+ pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF);
if (!PV_IS_EXEC_P(md->pvh_attrs)) {
pmap_syncicache_page(md, pa);
}
rv = ABORT_FIXUP_RETURN;
- l2pte_set(ptep, opte & ~L2_XS_XN, opte);
- pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF);
+ l2pte_set(ptep, opte & ~L2_XS_XN, 0);
+ PTE_SYNC(ptep);
}
pmap_release_page_lock(md);
@@ -4366,7 +4400,11 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va,
| (pm != pmap_kernel() ? L2_XS_nG : 0)
#endif
| 0;
- l2pte_set(ptep, npte, opte);
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
+ pmap_tlb_flush_SE(pm, va,
+ (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF);
+ l2pte_set(ptep, npte, 0);
PTE_SYNC(ptep);
PMAPCOUNT(fixup_mod);
rv = 1;
@@ -4433,7 +4471,11 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va,
}
#endif /* ARM_MMU_EXTENDED */
pmap_release_page_lock(md);
- l2pte_set(ptep, npte, opte);
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
+ pmap_tlb_flush_SE(pm, va,
+ (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF);
+ l2pte_set(ptep, npte, 0);
PTE_SYNC(ptep);
PMAPCOUNT(fixup_ref);
rv = 1;
@@ -4471,7 +4513,10 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va,
* Turn off no-execute.
*/
KASSERT(opte & L2_XS_nG);
- l2pte_set(ptep, opte & ~L2_XS_XN, opte);
+ l2pte_reset(ptep);
+ PTE_SYNC(ptep);
+ pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF);
+ l2pte_set(ptep, opte & ~L2_XS_XN, 0);
PTE_SYNC(ptep);
rv = 1;
PMAPCOUNT(fixup_exec);
@@ -4539,6 +4584,7 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va,
}
#endif
+#ifndef MULTIPROCESSOR
#if defined(DEBUG) || 1
/*
* If 'rv == 0' at this point, it generally indicates that there is a
@@ -4618,9 +4664,7 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va,
#endif
}
#endif
-
- pmap_tlb_flush_SE(pm, va,
- (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF);
+#endif
rv = 1;
@@ -4880,7 +4924,6 @@ pmap_deactivate(struct lwp *l)
#ifdef ARM_MMU_EXTENDED
kpreempt_disable();
struct cpu_info * const ci = curcpu();
- struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci));
/*
* Disable translation table walks from TTBR0 while no pmap has been
* activated.
@@ -4889,7 +4932,7 @@ pmap_deactivate(struct lwp *l)
armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0);
arm_isb();
pmap_tlb_asid_deactivate(pm);
- cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid);
+ cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID);
ci->ci_pmap_cur = pmap_kernel();
kpreempt_enable();
#else
@@ -4929,6 +4972,11 @@ pmap_update(pmap_t pm)
}
#ifdef ARM_MMU_EXTENDED
+#if defined(MULTIPROCESSOR)
+ armreg_bpiallis_write(0);
+#else
+ armreg_bpiall_write(0);
+#endif
#if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1
u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0);
Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.18 src/sys/arch/arm/cortex/a9_mpsubr.S:1.18.2.1
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.18 Wed May 21 01:02:45 2014
+++ src/sys/arch/arm/cortex/a9_mpsubr.S Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: a9_mpsubr.S,v 1.18 2014/05/21 01:02:45 ozaki-r Exp $ */
+/* $NetBSD: a9_mpsubr.S,v 1.18.2.1 2014/11/09 16:05:25 martin Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -343,8 +343,8 @@ cortex_init:
bxne r10 // return if set
#endif
-#if defined(CPU_CORTEXA7)
mrc p15, 0, r4, c1, c0, 0 // SCTLR read
+#if defined(CPU_CORTEXA7)
//
// Before turning on SMP, turn off the caches and the MMU.
//
@@ -369,9 +369,9 @@ cortex_init:
#ifdef __ARMEB__
setend le
#endif
- ldr r0, [r3, #SCU_CFG] // read scu config
- and r0, r0, #7 // get cpu max
- add r0, r0, #2 // adjust to cpu num shift
+ mrc p15, 0, r0, c0, c0, 5 // MPIDR get
+ and r0, r0, #3 // get our cpu numder
+ lsl r0, r0, #2 // adjust to cpu num shift
mov r1, #0xf // select all ways
lsl r1, r1, r0 // shift into place
str r1, [r3, #SCU_INV_ALL_REG] // write scu invalidate all
@@ -443,26 +443,37 @@ cortex_init:
mcr p15, 0, r1, c8, c7, 0 // TLBIALL (just this core)
#endif
+ // For the A7, SMP must be on ldrex/strex to work.
+ //
+#if defined(MULTIPROCESSOR) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9)
+#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9)
//
- // Step 4b, set ACTLR.SMP=1
+ // Step 4a, set ACTLR.SMP=1
//
mrc p15, 0, r0, c1, c0, 1 // ACTLR read
orr r0, r0, #CORTEXA9_AUXCTL_SMP // enable SMP
- mcr p15, 0, r0, c1, c0, 1 // ACTLR write
- isb
-#if defined(MULTIPROCESSOR) && (defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9))
+#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA9)
//
- // Step 4b (continued on A5/A9), ACTRL.FW=1)
+ // Step 4a (continued on A5/A9), ACTLR.FW=1)
//
orr r0, r0, #CORTEXA9_AUXCTL_FW // enable cache/tlb/coherency
- mcr p15, 0, r0, c1, c0, 1 // ACTRL write
+#endif /* A5 || A9 */
+#if defined(CPU_CORTEXA9)
+ //
+ // Step 4b (continued on A9), ACTLR.L2PE=1)
+ //
+ orr r0, r0, #CORTEXA9_AUXCTL_L2PE // enable L2 cache prefetch
+#endif
+
+ mcr p15, 0, r0, c1, c0, 1 // ACTLR write
isb
dsb
-#endif
+#endif /* A5 || A7 || A9 */
+#endif /* MULTIPROCESSOR */
//
- // Step 4a, resoter SCTRL (enable the data cache)
+ // Step 4b, restore SCTRL (enable the data cache)
//
orr r4, r4, #CPU_CONTROL_IC_ENABLE // enable icache
orr r4, r4, #CPU_CONTROL_DC_ENABLE // enable dcache
@@ -509,7 +520,7 @@ cortex_mpstart:
#if 0
mrc p15, 0, r0, c1, c1, 2 // NSACR read
- // Allow non-secure access to ACTRL[SMP]
+ // Allow non-secure access to ACTLR[SMP]
orr r0, r0, #NSACR_SMP
#ifdef FPU_VFP
// Allow non-secure access to VFP/Neon
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.10 src/sys/arch/arm/cortex/gic.c:1.10.2.1
--- src/sys/arch/arm/cortex/gic.c:1.10 Mon May 19 22:47:53 2014
+++ src/sys/arch/arm/cortex/gic.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.10 2014/05/19 22:47:53 rmind Exp $ */
+/* $NetBSD: gic.c,v 1.10.2.1 2014/11/09 16:05:25 martin Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,11 +29,12 @@
*/
#include "opt_ddb.h"
+#include "opt_multiprocessor.h"
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.10 2014/05/19 22:47:53 rmind Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.10.2.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -349,11 +350,13 @@ armgic_establish_irq(struct pic_softc *p
* to the primary cpu.
*/
targets &= ~(0xff << byte_shift);
+#if 0
#ifdef MULTIPROCESSOR
if (is->is_mpsafe) {
- targets |= sc->sc_mptargets;
+ targets |= sc->sc_mptargets << byte_shift;
} else
#endif
+#endif
targets |= 1 << byte_shift;
gicd_write(sc, targets_reg, targets);
@@ -442,7 +445,7 @@ armgic_cpu_init_targets(struct armgic_so
struct intrsource * const is = sc->sc_pic.pic_sources[irq];
const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4);
if (is != NULL && is->is_mpsafe) {
- const u_int byte_shift = 0xff << (8 * (irq & 3));
+ const u_int byte_shift = 8 * (irq & 3);
uint32_t targets = gicd_read(sc, targets_reg);
targets |= sc->sc_mptargets << byte_shift;
gicd_write(sc, targets_reg, targets);
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.97 src/sys/arch/arm/include/armreg.h:1.97.2.1
--- src/sys/arch/arm/include/armreg.h:1.97 Mon Apr 14 20:50:47 2014
+++ src/sys/arch/arm/include/armreg.h Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.97 2014/04/14 20:50:47 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.97.2.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -417,16 +417,6 @@
#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
-/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */
-#define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Enable parity */
-#define CORTEXA9_AUXCTL_1WAY 0x00000100 /* Alloc in one way only */
-#define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache */
-#define CORTEXA9_AUXCTL_SMP 0x00000040 /* CPU is in SMP mode */
-#define CORTEXA9_AUXCTL_WRZERO 0x00000008 /* Write full line of zeroes */
-#define CORTEXA9_AUXCTL_L1PLD 0x00000004 /* L1 Dside prefetch */
-#define CORTEXA9_AUXCTL_L2PLD 0x00000002 /* L2 Dside prefetch */
-#define CORTEXA9_AUXCTL_FW 0x00000001 /* Forward Cache/TLB ops */
-
/* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
@@ -448,8 +438,8 @@
/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
#define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */
-#define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */
-#define CORTEXA9_AUXCTL_L1_PLD 0x00000004 /* Data prefetch hint enable */
+#define CORTEXA9_AUXCTL_L2PE 0x00000002 /* Prefetch hint enable */
+#define CORTEXA9_AUXCTL_L1PE 0x00000004 /* Data prefetch hint enable */
#define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */
#define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */
#define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */
@@ -922,12 +912,13 @@ ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0
ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */
/* cp15 c7 registers */
ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */
-ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */
+ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Predictor Invalidate All (IS) */
ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */
ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */
ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */
ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */
-ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */
+ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c7,c5,6") /* Branch Predictor Invalidate All */
+ARMREG_WRITE_INLINE(bpimva, "p15,0,%0,c7,c5,7") /* Branch Predictor invalidate by MVA */
ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */
ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */
ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */
@@ -938,7 +929,7 @@ ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c
ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */
ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */
ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */
-ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */
+ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c11,1") /* Data Clean MVA to PoU */
ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */
ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */
/* cp15 c8 registers */
Index: src/sys/arch/arm/include/arm32/pmap.h
diff -u src/sys/arch/arm/include/arm32/pmap.h:1.135 src/sys/arch/arm/include/arm32/pmap.h:1.135.2.1
--- src/sys/arch/arm/include/arm32/pmap.h:1.135 Thu Jul 31 08:04:57 2014
+++ src/sys/arch/arm/include/arm32/pmap.h Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.135 2014/07/31 08:04:57 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.135.2.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -75,6 +75,7 @@
#ifndef _LOCORE
#if defined(_KERNEL_OPT)
#include "opt_arm32_pmap.h"
+#include "opt_multiprocessor.h"
#endif
#include <arm/cpufunc.h>
#include <uvm/uvm_object.h>
Index: src/sys/arch/arm/mainbus/cpu_mainbus.c
diff -u src/sys/arch/arm/mainbus/cpu_mainbus.c:1.15 src/sys/arch/arm/mainbus/cpu_mainbus.c:1.15.2.1
--- src/sys/arch/arm/mainbus/cpu_mainbus.c:1.15 Thu Jun 5 03:46:26 2014
+++ src/sys/arch/arm/mainbus/cpu_mainbus.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_mainbus.c,v 1.15 2014/06/05 03:46:26 matt Exp $ */
+/* $NetBSD: cpu_mainbus.c,v 1.15.2.1 2014/11/09 16:05:25 martin Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -42,9 +42,10 @@
*/
#include "locators.h"
+#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.15 2014/06/05 03:46:26 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.15.2.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
Index: src/sys/arch/arm/pic/pic.c
diff -u src/sys/arch/arm/pic/pic.c:1.22 src/sys/arch/arm/pic/pic.c:1.22.2.1
--- src/sys/arch/arm/pic/pic.c:1.22 Mon May 19 22:47:53 2014
+++ src/sys/arch/arm/pic/pic.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pic.c,v 1.22 2014/05/19 22:47:53 rmind Exp $ */
+/* $NetBSD: pic.c,v 1.22.2.1 2014/11/09 16:05:25 martin Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -32,7 +32,7 @@
#include "opt_ddb.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.22 2014/05/19 22:47:53 rmind Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.22.2.1 2014/11/09 16:05:25 martin Exp $");
#include <sys/param.h>
#include <sys/atomic.h>
@@ -119,7 +119,7 @@ pic_ipi_generic(void *arg)
int
pic_ipi_ddb(void *arg)
{
- printf("%s: %s: tf=%p\n", __func__, curcpu()->ci_cpuname, arg);
+// printf("%s: %s: tf=%p\n", __func__, curcpu()->ci_cpuname, arg);
kdb_trap(-1, arg);
return 1;
}
@@ -646,7 +646,7 @@ pic_establish_intr(struct pic_softc *pic
is->is_func = func;
is->is_arg = arg;
#ifdef MULTIPROCESSOR
- is->is_mpsafe = (type & IST_MPSAFE);
+ is->is_mpsafe = (type & IST_MPSAFE) || ipl != IPL_VM;
#endif
if (pic->pic_ops->pic_source_name)
Index: src/sys/arch/arm/pic/picvar.h
diff -u src/sys/arch/arm/pic/picvar.h:1.10 src/sys/arch/arm/pic/picvar.h:1.10.2.1
--- src/sys/arch/arm/pic/picvar.h:1.10 Mon May 19 22:47:53 2014
+++ src/sys/arch/arm/pic/picvar.h Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: picvar.h,v 1.10 2014/05/19 22:47:53 rmind Exp $ */
+/* $NetBSD: picvar.h,v 1.10.2.1 2014/11/09 16:05:25 martin Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -30,6 +30,8 @@
#ifndef _ARM_PIC_PICVAR_H_
#define _ARM_PIC_PICVAR_H_
+#include "opt_multiprocessor.h"
+
#ifdef MULTIPROCESSOR
#include <sys/kcpuset.h>
#endif
Index: src/sys/arch/evbarm/conf/BPI
diff -u src/sys/arch/evbarm/conf/BPI:1.2.2.2 src/sys/arch/evbarm/conf/BPI:1.2.2.3
--- src/sys/arch/evbarm/conf/BPI:1.2.2.2 Wed Sep 10 09:37:51 2014
+++ src/sys/arch/evbarm/conf/BPI Sun Nov 9 16:05:25 2014
@@ -1,5 +1,5 @@
#
-# $NetBSD: BPI,v 1.2.2.2 2014/09/10 09:37:51 martin Exp $
+# $NetBSD: BPI,v 1.2.2.3 2014/11/09 16:05:25 martin Exp $
#
# BPI -- Banana Pi - an Allwinner A20 Eval Board Kernel
#
@@ -20,12 +20,11 @@ options RTC_OFFSET=0 # hardware clock i
no makeoptions BOARDTYPE
makeoptions BOARDTYPE="bpi"
#options UVMHIST,UVMHIST_PRINT
-options CPU_CORTEXA8
options CPU_CORTEXA7
-options ALLWINNER_A10
options ALLWINNER_A20
options PMAPCOUNTERS
options AWIN_CONSOLE_EARLY
+options MULTIPROCESSOR
# Architecture options
Index: src/sys/arch/evbarm/conf/CUBIETRUCK
diff -u src/sys/arch/evbarm/conf/CUBIETRUCK:1.2.4.1 src/sys/arch/evbarm/conf/CUBIETRUCK:1.2.4.2
--- src/sys/arch/evbarm/conf/CUBIETRUCK:1.2.4.1 Wed Sep 10 09:37:51 2014
+++ src/sys/arch/evbarm/conf/CUBIETRUCK Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-# $NetBSD: CUBIETRUCK,v 1.2.4.1 2014/09/10 09:37:51 martin Exp $
+# $NetBSD: CUBIETRUCK,v 1.2.4.2 2014/11/09 16:05:25 martin Exp $
#
# CUBIETRUCK - Cubieboard3 (mostly cubieboard2 with 2GB)
#
@@ -20,9 +20,6 @@ makeoptions BOARDTYPE="cubietruck"
#
options PMAP_NEED_ALLOC_POOLPAGE
-#
-# not fully working yet
-#
-# options MULTIPROCESSOR
-# cpu* at mainbus?
-# options VERBOSE_INIT_ARM # verbose bootstraping messages
+options MULTIPROCESSOR
+cpu* at mainbus?
+#options VERBOSE_INIT_ARM # verbose bootstraping messages
Index: src/sys/uvm/pmap/pmap_tlb.c
diff -u src/sys/uvm/pmap/pmap_tlb.c:1.8 src/sys/uvm/pmap/pmap_tlb.c:1.8.4.1
--- src/sys/uvm/pmap/pmap_tlb.c:1.8 Thu Apr 3 14:46:25 2014
+++ src/sys/uvm/pmap/pmap_tlb.c Sun Nov 9 16:05:25 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_tlb.c,v 1.8 2014/04/03 14:46:25 matt Exp $ */
+/* $NetBSD: pmap_tlb.c,v 1.8.4.1 2014/11/09 16:05:25 martin Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap_tlb.c,v 1.8 2014/04/03 14:46:25 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap_tlb.c,v 1.8.4.1 2014/11/09 16:05:25 martin Exp $");
/*
* Manages address spaces in a TLB.
@@ -935,7 +935,7 @@ pmap_tlb_asid_deactivate(pmap_t pm)
#endif
curcpu()->ci_pmap_asid_cur = 0;
UVMHIST_LOG(maphist, " <-- done (pm=%#x)", pm, 0, 0, 0);
- tlb_set_asid(0);
+ tlb_set_asid(KERNEL_PID);
#if defined(DEBUG)
pmap_tlb_asid_check();
#endif
