Module Name: src
Committed By: macallan
Date: Sat Nov 22 15:14:35 UTC 2014
Modified Files:
src/sys/dev/ic: com.c comreg.h comvar.h
Log Message:
deal with quirk in Ingenic UARTs
( they have a bit in the FIFO control register which turns the entire
port off if not set )
To generate a diff of this commit:
cvs rdiff -u -r1.328 -r1.329 src/sys/dev/ic/com.c
cvs rdiff -u -r1.22 -r1.23 src/sys/dev/ic/comreg.h
cvs rdiff -u -r1.78 -r1.79 src/sys/dev/ic/comvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/com.c
diff -u src/sys/dev/ic/com.c:1.328 src/sys/dev/ic/com.c:1.329
--- src/sys/dev/ic/com.c:1.328 Sat Nov 15 19:18:18 2014
+++ src/sys/dev/ic/com.c Sat Nov 22 15:14:35 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: com.c,v 1.328 2014/11/15 19:18:18 christos Exp $ */
+/* $NetBSD: com.c,v 1.329 2014/11/22 15:14:35 macallan Exp $ */
/*-
* Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
@@ -66,7 +66,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.328 2014/11/15 19:18:18 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.329 2014/11/22 15:14:35 macallan Exp $");
#include "opt_com.h"
#include "opt_ddb.h"
@@ -403,7 +403,6 @@ com_attach_subr(struct com_softc *sc)
dict = device_properties(sc->sc_dev);
prop_dictionary_get_bool(dict, "is_console", &is_console);
-
callout_init(&sc->sc_diag_callout, 0);
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
@@ -460,6 +459,12 @@ com_attach_subr(struct com_softc *sc)
fifo_msg = "OMAP UART, working fifo";
SET(sc->sc_hwflags, COM_HW_FIFO);
goto fifodelay;
+
+ case COM_TYPE_INGENIC:
+ sc->sc_fifolen = 64;
+ fifo_msg = "Ingenic UART, working fifo";
+ SET(sc->sc_hwflags, COM_HW_FIFO);
+ goto fifodelay;
}
sc->sc_fifolen = 1;
@@ -2302,8 +2307,16 @@ cominit(struct com_regs *regsp, int rate
}
CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
- CSR_WRITE_1(regsp, COM_REG_FIFO,
- FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
+
+ if (type == COM_TYPE_INGENIC) {
+ CSR_WRITE_1(regsp, COM_REG_FIFO,
+ FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
+ FIFO_TRIGGER_1 | FIFO_UART_ON);
+ } else {
+ CSR_WRITE_1(regsp, COM_REG_FIFO,
+ FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
+ FIFO_TRIGGER_1);
+ }
if (type == COM_TYPE_OMAP) {
/* setup the fifos. the FCR value is not used as long
Index: src/sys/dev/ic/comreg.h
diff -u src/sys/dev/ic/comreg.h:1.22 src/sys/dev/ic/comreg.h:1.23
--- src/sys/dev/ic/comreg.h:1.22 Thu Oct 3 13:23:03 2013
+++ src/sys/dev/ic/comreg.h Sat Nov 22 15:14:35 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: comreg.h,v 1.22 2013/10/03 13:23:03 kiyohara Exp $ */
+/* $NetBSD: comreg.h,v 1.23 2014/11/22 15:14:35 macallan Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -72,6 +72,7 @@
#define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
#define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
#define FIFO_DMA_MODE 0x08
+#define FIFO_UART_ON 0x10 /* JZ47xx only */
#define FIFO_64B_ENABLE 0x20 /* 64byte FIFO Enable (16750) */
#define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
#define FIFO_TRIGGER_4 0x40 /* ibid 4 */
Index: src/sys/dev/ic/comvar.h
diff -u src/sys/dev/ic/comvar.h:1.78 src/sys/dev/ic/comvar.h:1.79
--- src/sys/dev/ic/comvar.h:1.78 Thu Oct 3 13:23:03 2013
+++ src/sys/dev/ic/comvar.h Sat Nov 22 15:14:35 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: comvar.h,v 1.78 2013/10/03 13:23:03 kiyohara Exp $ */
+/* $NetBSD: comvar.h,v 1.79 2014/11/22 15:14:35 macallan Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -234,6 +234,7 @@ struct com_softc {
#define COM_TYPE_AU1x00 3 /* AMD/Alchemy Au1x000 proc. built-in */
#define COM_TYPE_OMAP 4 /* TI OMAP processor built-in */
#define COM_TYPE_16550_NOERS 5 /* like a 16550, no ERS */
+#define COM_TYPE_INGENIC 6 /* JZ4780 built-in */
/* power management hooks */
int (*enable)(struct com_softc *);
