Module Name: src
Committed By: martin
Date: Mon Dec 29 15:14:27 UTC 2014
Modified Files:
src/sys/arch/x86/include [netbsd-6]: cacheinfo.h
Log Message:
Pullup the following revisions, requested by msaitoh in #1219:
sys/arch/x86/include/cacheinfo.h 1.14-1.19
Update Intel's cache and TLB descripotr table. This changes the number
of page coloring on some CPUs.
- Add Shared L2 TLB.
- Support prefetch size.
- Add some new TLB and cache entries from the document.
- Fix some entries:
- Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry.
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.13.2.1 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.13 src/sys/arch/x86/include/cacheinfo.h:1.13.2.1
--- src/sys/arch/x86/include/cacheinfo.h:1.13 Sun Dec 4 17:00:10 2011
+++ src/sys/arch/x86/include/cacheinfo.h Mon Dec 29 15:14:26 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.13 2011/12/04 17:00:10 chs Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.13.2.1 2014/12/29 15:14:26 martin Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -8,7 +8,10 @@ struct x86_cache_info {
uint8_t cai_desc;
uint8_t cai_associativity;
u_int cai_totalsize; /* #entries for TLB, bytes for cache */
- u_int cai_linesize; /* or page size for TLB */
+ u_int cai_linesize; /*
+ * or page size for TLB,
+ * or prefetch size
+ */
#ifndef _KERNEL
const char *cai_string;
#endif
@@ -30,8 +33,11 @@ struct x86_cache_info {
#define CAI_L2_ITLB2 13 /* L2 Instruction TLB (2/4M pages) */
#define CAI_L2_DTLB 14 /* L2 Data TLB (4K pages) */
#define CAI_L2_DTLB2 15 /* L2 Data TLB (2/4M pages) */
+#define CAI_L2_STLB 16 /* Shared L2 TLB (4K pages) */
+#define CAI_L2_STLB2 17 /* Shared L2 TLB (4K/2M pages) */
+#define CAI_PREFETCH 18 /* Prefetch */
-#define CAI_COUNT 16
+#define CAI_COUNT 19
/*
* AMD Cache Info:
@@ -209,33 +215,55 @@ struct x86_cache_info {
*/
#define INTEL_CACHE_INFO { \
__CI_TBL(CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2, 0x0b, 4, 4, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0x4f, 0xff, 32, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
-__CI_TBL(CAI_ITLB, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
+__CI_TBL(CAI_ITLB2, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
__CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0x57, 4, 16, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
+__CI_TBL(CAI_DTLB, 0x57, 4, 16, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x59, 0xff, 16, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
-__CI_TBL(CAI_ITLB, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
+__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
+__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
+__CI_TBL(CAI_DTLB, 0xa0, 0xff, 32, 4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
__CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0xb5, 8, 64, 4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0xb6, 8,128, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0xba, 4, 64, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \
+__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \
+__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "4K/2M: 16 entries"), \
+__CI_TBL(CAI_L2_STLB, 0xc3, 6,1536, 4 * 1024, NULL), \
+__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x09, 4, 32 * 1024, 64, NULL), \
-__CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \
__CI_TBL(CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL), \
-__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 32, NULL), \
+__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 64, NULL), \
+__CI_TBL(CAI_DCACHE, 0x0e, 6, 24 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x21, 8, 256 * 1024, 64, NULL), /* L2 (MLC) */ \
+__CI_TBL(CAI_L3CACHE, 0x22, 0xff, 512 * 1024, 64, "sectored, 4-way "), \
+__CI_TBL(CAI_L3CACHE, 0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_L2CACHE, 0x24, 16, 1 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_L3CACHE, 0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL), \
+__CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x3b, 2, 128 * 1024, 64, NULL), \
@@ -248,15 +276,21 @@ __CI_TBL(CAI_L2CACHE, 0x42, 4,
__CI_TBL(CAI_L2CACHE, 0x43, 4, 512 * 1024, 32, NULL), \
__CI_TBL(CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32, NULL), \
__CI_TBL(CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x46, 4, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x47, 8, 8 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x48, 12, 3 * 1024 * 1024, 64, NULL), \
\
/* 0x49 Is L2 on Xeon MP (Family 0f, Model 06), L3 otherwise */ \
__CI_TBL(CAI_L2CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4a, 12, 6 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4b, 16, 8 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4c, 12,12 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4d, 16,16 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x4e, 24, 6 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_DCACHE, 0x60, 8, 16 * 1024, 64, NULL), \
__CI_TBL(CAI_DCACHE, 0x66, 4, 8 * 1024, 64, NULL), \
__CI_TBL(CAI_DCACHE, 0x67, 4, 16 * 1024, 64, NULL), \
-__CI_TBL(CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL), \
__CI_TBL(CAI_DCACHE, 0x68, 4, 32 * 1024, 64, NULL), \
__CI_TBL(CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"), \
__CI_TBL(CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"), \
@@ -269,23 +303,13 @@ __CI_TBL(CAI_L2CACHE, 0x7b, 8,
__CI_TBL(CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x7d, 8, 2 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x7f, 2, 512 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x80, 8, 512 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x82, 8, 256 * 1024, 32, NULL), \
__CI_TBL(CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL), \
__CI_TBL(CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL), \
__CI_TBL(CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL), \
__CI_TBL(CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x87, 8, 1 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0x22, 0xff, 512 * 1024, 64, "sectored, 4-way "), \
-__CI_TBL(CAI_L3CACHE, 0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \
-__CI_TBL(CAI_L3CACHE, 0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \
-__CI_TBL(CAI_L3CACHE, 0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \
-__CI_TBL(CAI_L3CACHE, 0x46, 4, 4 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0x47, 8, 8 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0x4a, 12, 6 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0x4b, 16, 8 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0x4c, 12,12 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0x4d, 16,16 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xd0, 4, 512 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xd1, 4, 1 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xd2, 4, 2 * 1024 * 1024, 64, NULL), \
@@ -299,8 +323,11 @@ __CI_TBL(CAI_L3CACHE, 0xe2, 16, 2 * 1
__CI_TBL(CAI_L3CACHE, 0xe3, 16, 4 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0xeb, 24,24 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_PREFETCH, 0xf0, 0, 0, 64, NULL), \
+__CI_TBL(CAI_PREFETCH, 0xf1, 0, 0,128, NULL), \
+/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
__CI_TBL(0, 0, 0, 0, 0, NULL) \
}
