Module Name: src
Committed By: skrll
Date: Mon Dec 29 22:58:59 UTC 2014
Modified Files:
src/sys/arch/arm/samsung: exynos5_reg.h exynos_soc.c
Log Message:
Fixup USB Phy initialisation for Exynos5410.
odroid-xu now detects USB devices.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/samsung/exynos5_reg.h
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/samsung/exynos_soc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/samsung/exynos5_reg.h
diff -u src/sys/arch/arm/samsung/exynos5_reg.h:1.19 src/sys/arch/arm/samsung/exynos5_reg.h:1.20
--- src/sys/arch/arm/samsung/exynos5_reg.h:1.19 Thu Oct 2 16:17:33 2014
+++ src/sys/arch/arm/samsung/exynos5_reg.h Mon Dec 29 22:58:59 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5_reg.h,v 1.19 2014/10/02 16:17:33 skrll Exp $ */
+/* $NetBSD: exynos5_reg.h,v 1.20 2014/12/29 22:58:59 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -363,41 +363,42 @@
/* used Exynos5 USB PHY registers */
#define USB_PHY_HOST_CTRL0 0x00
-#define HOST_CTRL0_PHY_SWRST __BIT(0)
-#define HOST_CTRL0_LINK_SWRST __BIT(1)
-#define HOST_CTRL0_UTMI_SWRST __BIT(2)
-#define HOST_CTRL0_WORDINTERFACE __BIT(3)
-#define HOST_CTRL0_FORCESUSPEND __BIT(4)
-#define HOST_CTRL0_FORCESLEEP __BIT(5)
-#define HOST_CTRL0_SIDDQ __BIT(6)
-#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
-#define HOST_CTRL0_TESTBURNIN __BIT(11)
-#define HOST_CTRL0_RETENABLE __BIT(10)
-#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */
-#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)
-#define HOST_CTRL0_REFCLKSEL_XTAL __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 0)
-#define HOST_CTRL0_REFCLKSEL_EXTL __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 1)
-#define HOST_CTRL0_REFCLKSEL_CLKCORE __SHIFTIN(HOST_CRTL0_REFCLK_MASK, 2)
-#define HOST_CTRL0_PHY_SWRST_ALL __BIT(31)
+#define HOST_CTRL0_PHY_SWRST __BIT(0)
+#define HOST_CTRL0_LINK_SWRST __BIT(1)
+#define HOST_CTRL0_UTMI_SWRST __BIT(2)
+#define HOST_CTRL0_WORDINTERFACE __BIT(3)
+#define HOST_CTRL0_FORCESUSPEND __BIT(4)
+#define HOST_CTRL0_FORCESLEEP __BIT(5)
+#define HOST_CTRL0_SIDDQ __BIT(6)
+#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
+#define HOST_CTRL0_RETENABLE __BIT(10)
+#define HOST_CTRL0_TESTBURNIN __BIT(11)
+#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */
+#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)
+#define HOST_CTRL0_REFCLKSEL_XTAL 0
+#define HOST_CTRL0_REFCLKSEL_EXTL 1
+#define HOST_CTRL0_REFCLKSEL_CLKCORE 2
+#define HOST_CTRL0_PHY_SWRST_ALL __BIT(31)
#define USB_PHY_HSIC_CTRL1 0x10
#define USB_PHY_HSIC_TUNE1 0x14
#define USB_PHY_HSIC_CTRL2 0x20
#define USB_PHY_HSIC_TUNE2 0x24
-#define HSIC_CTRL_PHY_SWRST __BIT(0)
-#define HSIC_CTRL_UTMI_SWRST __BIT(2)
-#define HSIC_CTRL_WORDINTERFACE __BIT(3)
-#define HSIC_CTRL_FORCESUSPEND __BIT(4)
-#define HSIC_CTRL_FORCESLEEP __BIT(5)
-#define HSIC_CTRL_SIDDQ __BIT(6)
-#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)
-#define REFCLKDIV_12 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x24)
-#define REFCLKDIV_15 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x1c)
-#define REFCLKDIV_16 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x1a)
-#define REFCLKDIV_19_2 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x15)
-#define REFCLKDIV_20 __SHIFTIN(HSIC_CTRL_REFCLKDIV_MASK, 0x14)
-#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)
-#define REFCLKSEL_HSIC_DEFAULT __SHIFTIN(HSIC_CTRL_REFCLKSEL_MASK, 2)
+
+#define HSIC_CTRL_PHY_SWRST __BIT(0)
+#define HSIC_CTRL_UTMI_SWRST __BIT(2)
+#define HSIC_CTRL_WORDINTERFACE __BIT(3)
+#define HSIC_CTRL_FORCESUSPEND __BIT(4)
+#define HSIC_CTRL_FORCESLEEP __BIT(5)
+#define HSIC_CTRL_SIDDQ __BIT(6)
+#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)
+#define HSIC_CTRL_REFCLKDIV_12 0x24
+#define HSIC_CTRL_REFCLKDIV_15 0x1c
+#define HSIC_CTRL_REFCLKDIV_16 0x1a
+#define HSIC_CTRL_REFCLKDIV_19_2 0x15
+#define HSIC_CTRL_REFCLKDIV_20 0x14
+#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)
+#define HSIC_CTRL_REFCLKSEL_DEFAULT 2
#define USB_PHY_HOST_EHCICTRL 0x30
#define HOST_EHCICTRL_ENA_INCR16 __BIT(26)
Index: src/sys/arch/arm/samsung/exynos_soc.c
diff -u src/sys/arch/arm/samsung/exynos_soc.c:1.26 src/sys/arch/arm/samsung/exynos_soc.c:1.27
--- src/sys/arch/arm/samsung/exynos_soc.c:1.26 Mon Dec 29 22:34:08 2014
+++ src/sys/arch/arm/samsung/exynos_soc.c Mon Dec 29 22:58:59 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_soc.c,v 1.26 2014/12/29 22:34:08 skrll Exp $ */
+/* $NetBSD: exynos_soc.c,v 1.27 2014/12/29 22:58:59 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.26 2014/12/29 22:34:08 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.27 2014/12/29 22:58:59 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -878,34 +878,55 @@ static void
exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
{
uint32_t phyhost; //, phyotg;
- uint32_t phyhsic1, phyhsic2, hsic_ctrl;
- uint32_t ehcictrl; //, ohcictrl;
+ uint32_t phyhsic;
+ uint32_t ehcictrl, ohcictrl;
/* host configuration: */
phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HOST_CTRL0);
+ USB_PHY_HOST_CTRL0);
/* host phy reference clock; assumption its 24 MHz now */
phyhost &= ~HOST_CTRL0_FSEL_MASK;
- phyhost |= __SHIFTIN(HOST_CTRL0_FSEL_MASK, FSEL_CLKSEL_24M);
+ phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);
/* enable normal mode of operation */
phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
/* host phy reset */
phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL |
- HOST_CTRL0_SIDDQ | HOST_CTRL0_COMMONON_N);
+ HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND |
+ HOST_CTRL0_FORCESLEEP);
/* host link reset */
- phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST;
-
+ phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST |
+ HOST_CTRL0_COMMONON_N;
/* do the reset */
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HOST_CTRL0, phyhost);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
+ phyhost);
DELAY(10000);
+
phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HOST_CTRL0, phyhost);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
+ phyhost);
+
+ /* HSIC control */
+ phyhsic =
+ __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) |
+ __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) |
+ HSIC_CTRL_PHY_SWRST;
+
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
+ phyhsic);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
+ phyhsic);
+ DELAY(10);
+
+ phyhsic &= ~HSIC_CTRL_PHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
+ phyhsic);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
+ phyhsic);
+ DELAY(80);
#if 0
/* otg configuration: */
@@ -935,57 +956,21 @@ exynos5410_usb2phy_enable(bus_space_hand
USB_PHY_OTG_SYS, phyotg);
#endif
- /* HSIC phy configuration: */
- hsic_ctrl = HSIC_CTRL_FORCESUSPEND | HSIC_CTRL_FORCESLEEP |
- HSIC_CTRL_SIDDQ;
-
- phyhsic1 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL1);
- phyhsic2 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL1);
-
- phyhsic1 &= ~hsic_ctrl;
- phyhsic2 &= ~hsic_ctrl;
-
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL1, phyhsic1);
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL2, phyhsic2);
- DELAY(10000);
-
- hsic_ctrl = REFCLKDIV_12 | REFCLKSEL_HSIC_DEFAULT |
- HSIC_CTRL_UTMI_SWRST;
-
- phyhsic1 |= hsic_ctrl;
- phyhsic2 |= hsic_ctrl;
-
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL1, phyhsic1);
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL2, phyhsic2);
-
- DELAY(10000);
-
- hsic_ctrl = HSIC_CTRL_PHY_SWRST | HSIC_CTRL_UTMI_SWRST;
-
- phyhsic1 &= ~hsic_ctrl;
- phyhsic2 &= ~hsic_ctrl;
-
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL1, phyhsic1);
- bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HSIC_CTRL2, phyhsic2);
- DELAY(20000);
-
/* enable EHCI DMA burst: */
ehcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HOST_EHCICTRL);
+ USB_PHY_HOST_EHCICTRL);
ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN |
- HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
- HOST_EHCICTRL_ENA_INCR16;
+ HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
+ HOST_EHCICTRL_ENA_INCR16;
bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
- USB_PHY_HOST_EHCICTRL, ehcictrl);
- DELAY(10000);
+ USB_PHY_HOST_EHCICTRL, ehcictrl);
+
+ /* Set OHCI suspend */
+ ohcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_OHCICTRL);
+ ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_OHCICTRL, ohcictrl);
}
