Module Name: src
Committed By: palle
Date: Mon Jan 5 11:40:56 UTC 2015
Modified Files:
src/sys/arch/sparc64/sparc64: cache.c cache.h
Log Message:
cache_flush_phys(): Avoid run-time check for cpu type/implementation by
installing correct function pointer in cache_setup_funcs()
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/sparc64/sparc64/cache.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/sparc64/sparc64/cache.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/sparc64/cache.c
diff -u src/sys/arch/sparc64/sparc64/cache.c:1.9 src/sys/arch/sparc64/sparc64/cache.c:1.10
--- src/sys/arch/sparc64/sparc64/cache.c:1.9 Tue Dec 30 18:29:20 2014
+++ src/sys/arch/sparc64/sparc64/cache.c Mon Jan 5 11:40:56 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.9 2014/12/30 18:29:20 palle Exp $ */
+/* $NetBSD: cache.c,v 1.10 2015/01/05 11:40:56 palle Exp $ */
/*
* Copyright (c) 2011 Matthew R. Green
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.9 2014/12/30 18:29:20 palle Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.10 2015/01/05 11:40:56 palle Exp $");
#include "opt_multiprocessor.h"
@@ -78,6 +78,8 @@ void (*sp_dcache_flush_page)(paddr_t)
void (*sp_tlb_flush_pte)(vaddr_t, int) = sp_tlb_flush_pte_us;
void (*sp_tlb_flush_all)(void) = sp_tlb_flush_all_us;
+void (*cache_flush_phys)(paddr_t, psize_t, int) = cache_flush_phys_us;
+
static void
sp_tlb_flush_pte_sun4v(vaddr_t va, int ctx)
{
@@ -93,6 +95,13 @@ sp_tlb_flush_all_sun4v(void)
panic("sp_tlb_flush_all_sun4v() not implemented yet");
}
+
+static void
+cache_flush_phys_sun4v(paddr_t pa, psize_t size, int ecache)
+{
+ panic("cache_flush_phys_sun4v() not implemented yet");
+}
+
void
cache_setup_funcs(void)
{
@@ -122,14 +131,16 @@ cache_setup_funcs(void)
#endif
}
- /* Prepare sp_tlb_flush_* functions */
+ /* Prepare sp_tlb_flush_* and cache_flush_phys() functions */
if (CPU_ISSUN4V) {
sp_tlb_flush_pte = sp_tlb_flush_pte_sun4v;
sp_tlb_flush_all = sp_tlb_flush_all_sun4v;
+ cache_flush_phys = cache_flush_phys_sun4v;
} else {
if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP()) {
sp_tlb_flush_pte = sp_tlb_flush_pte_usiii;
sp_tlb_flush_all = sp_tlb_flush_all_usiii;
+ cache_flush_phys = cache_flush_phys_usiii;
}
}
Index: src/sys/arch/sparc64/sparc64/cache.h
diff -u src/sys/arch/sparc64/sparc64/cache.h:1.27 src/sys/arch/sparc64/sparc64/cache.h:1.28
--- src/sys/arch/sparc64/sparc64/cache.h:1.27 Tue Dec 30 18:29:20 2014
+++ src/sys/arch/sparc64/sparc64/cache.h Mon Jan 5 11:40:56 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.h,v 1.27 2014/12/30 18:29:20 palle Exp $ */
+/* $NetBSD: cache.h,v 1.28 2015/01/05 11:40:56 palle Exp $ */
/*
* Copyright (c) 2011 Matthew R. Green
@@ -101,15 +101,7 @@ void blast_icache_usiii(void); /* Clear
/* The following flush a range from the D$ and I$ but not E$. */
void cache_flush_phys_us(paddr_t, psize_t, int);
void cache_flush_phys_usiii(paddr_t, psize_t, int);
-
-static __inline__ void
-cache_flush_phys(paddr_t pa, psize_t size, int ecache)
-{
- if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
- cache_flush_phys_usiii(pa, size, ecache);
- else
- cache_flush_phys_us(pa, size, ecache);
-}
+extern void (*cache_flush_phys)(paddr_t, psize_t, int);
/* SPARC64 specific */
/* Assembly routines to flush TLB mappings */
