Module Name: src
Committed By: martin
Date: Fri Jan 9 10:33:07 UTC 2015
Modified Files:
src/sys/arch/x86/include [netbsd-7]: specialreg.h
src/sys/arch/x86/x86 [netbsd-7]: cpu_ucode_intel.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #396):
sys/arch/x86/x86/cpu_ucode_intel.c: revision 1.6
sys/arch/x86/include/specialreg.h: revision 1.81
Use specialreg.h's definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.78.4.1 -r1.78.4.2 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.5 -r1.5.4.1 src/sys/arch/x86/x86/cpu_ucode_intel.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.78.4.1 src/sys/arch/x86/include/specialreg.h:1.78.4.2
--- src/sys/arch/x86/include/specialreg.h:1.78.4.1 Fri Dec 12 16:44:35 2014
+++ src/sys/arch/x86/include/specialreg.h Fri Jan 9 10:33:07 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.78.4.1 2014/12/12 16:44:35 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.78.4.2 2015/01/09 10:33:07 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -506,6 +506,7 @@
#define MSR_CESR 0x011 /* P5 only (trap on P6) */
#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
+#define MSR_IA32_PLATFORM_ID 0x017
#define MSR_APICBASE 0x01b
#define MSR_EBL_CR_POWERON 0x02a
#define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
Index: src/sys/arch/x86/x86/cpu_ucode_intel.c
diff -u src/sys/arch/x86/x86/cpu_ucode_intel.c:1.5 src/sys/arch/x86/x86/cpu_ucode_intel.c:1.5.4.1
--- src/sys/arch/x86/x86/cpu_ucode_intel.c:1.5 Wed Mar 26 08:04:19 2014
+++ src/sys/arch/x86/x86/cpu_ucode_intel.c Fri Jan 9 10:33:07 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_ucode_intel.c,v 1.5 2014/03/26 08:04:19 christos Exp $ */
+/* $NetBSD: cpu_ucode_intel.c,v 1.5.4.1 2015/01/09 10:33:07 martin Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_ucode_intel.c,v 1.5 2014/03/26 08:04:19 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_ucode_intel.c,v 1.5.4.1 2015/01/09 10:33:07 martin Exp $");
#include "opt_xen.h"
#include "opt_cpu_ucode.h"
@@ -46,10 +46,6 @@ __KERNEL_RCSID(0, "$NetBSD: cpu_ucode_in
#include <machine/specialreg.h>
#include <x86/cpu_ucode.h>
-#define MSR_IA32_PLATFORM_ID 0x17
-#define MSR_IA32_BIOS_UPDT_TRIGGER 0x79
-#define MSR_IA32_BIOS_SIGN_ID 0x8b
-
static void
intel_getcurrentucode(uint32_t *ucodeversion, int *platformid)
{
@@ -58,9 +54,9 @@ intel_getcurrentucode(uint32_t *ucodever
kpreempt_disable();
- wrmsr(MSR_IA32_BIOS_SIGN_ID, 0);
+ wrmsr(MSR_BIOS_SIGN, 0);
x86_cpuid(0, unneeded_ids);
- msr = rdmsr(MSR_IA32_BIOS_SIGN_ID);
+ msr = rdmsr(MSR_BIOS_SIGN);
*ucodeversion = msr >> 32;
kpreempt_enable();
@@ -138,7 +134,7 @@ cpu_ucode_intel_apply(struct cpu_ucode_s
kpreempt_enable();
return EEXIST; /* ??? */
}
- wrmsr(MSR_IA32_BIOS_UPDT_TRIGGER, (uintptr_t)(sc->sc_blob) + 48);
+ wrmsr(MSR_BIOS_UPDT_TRIG, (uintptr_t)(sc->sc_blob) + 48);
intel_getcurrentucode(&nucodeversion, &platformid);
kpreempt_enable();
