Module Name: src
Committed By: jmcneill
Date: Sat Jan 17 15:05:25 UTC 2015
Modified Files:
src/sys/arch/arm/rockchip: files.rockchip obio.c rockchip_board.c
rockchip_cpufreq.c rockchip_crureg.h rockchip_emac.c rockchip_reg.h
rockchip_timer.c rockchip_var.h
src/sys/arch/evbarm/conf: ROCKCHIP
src/sys/arch/evbarm/rockchip: rockchip_machdep.c
Log Message:
Add Rockchip PX2 support, from FUKAUMI Naoki <[email protected]>
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/rockchip/files.rockchip
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/rockchip/obio.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/rockchip/rockchip_board.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rockchip_cpufreq.c \
src/sys/arch/arm/rockchip/rockchip_timer.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/rockchip/rockchip_crureg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/rockchip/rockchip_emac.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/rockchip_reg.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/rockchip/rockchip_var.h
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/evbarm/conf/ROCKCHIP
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/evbarm/rockchip/rockchip_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/files.rockchip
diff -u src/sys/arch/arm/rockchip/files.rockchip:1.9 src/sys/arch/arm/rockchip/files.rockchip:1.10
--- src/sys/arch/arm/rockchip/files.rockchip:1.9 Sun Jan 4 03:53:02 2015
+++ src/sys/arch/arm/rockchip/files.rockchip Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.9 2015/01/04 03:53:02 jmcneill Exp $
+# $NetBSD: files.rockchip,v 1.10 2015/01/17 15:05:24 jmcneill Exp $
#
# Configuration info for Rockchip ARM Peripherals
#
@@ -32,7 +32,11 @@ device rkiic: i2cbus, i2cexec
attach rkiic at obio
file arch/arm/rockchip/rockchip_i2c.c rkiic
-# Timer
+# RK3066 Timer (Synopsys DesignWare)
+attach dwctmr at obio with rkdwctmr
+file arch/arm/rockchip/rockchip_dwctmr.c rkdwctmr
+
+# RK3188 Timer
device rktimer
attach rktimer at obio
file arch/arm/rockchip/rockchip_timer.c rktimer
Index: src/sys/arch/arm/rockchip/obio.c
diff -u src/sys/arch/arm/rockchip/obio.c:1.16 src/sys/arch/arm/rockchip/obio.c:1.17
--- src/sys/arch/arm/rockchip/obio.c:1.16 Tue Jan 13 10:37:38 2015
+++ src/sys/arch/arm/rockchip/obio.c Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: obio.c,v 1.16 2015/01/13 10:37:38 jmcneill Exp $ */
+/* $NetBSD: obio.c,v 1.17 2015/01/17 15:05:24 jmcneill Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
@@ -38,7 +38,7 @@
#include "opt_rockchip.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.16 2015/01/13 10:37:38 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.17 2015/01/17 15:05:24 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -63,10 +63,10 @@ CFATTACH_DECL_NEW(obio, 0,
int obio_print(void *, const char *);
int obio_search(device_t, cfdata_t, const int *, void *);
-void obio_init_grf(void);
-void obio_iomux(int, int);
-void obio_init_gpio(void);
-void obio_swporta(int, int, int);
+static void obio_init_rk3066(void);
+static void obio_init_rk3188(void);
+static void obio_grf_set(uint32_t, uint32_t);
+static int obio_gpio_set_out(u_int, u_int, u_int);
#ifdef ROCKCHIP_CLOCK_DEBUG
static void obio_dump_clocks(void);
@@ -96,8 +96,17 @@ obio_attach(device_t parent, device_t se
obio_dump_clocks();
#endif
- obio_init_grf();
- obio_init_gpio();
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ obio_init_rk3066();
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ obio_init_rk3188();
+ break;
+ default:
+ break;
+ }
/*
* Attach all on-board devices as described in the kernel
@@ -178,125 +187,251 @@ obio_search(device_t parent, cfdata_t cf
return 0;
}
+#define GRF_GPIO0A_IOMUX_OFFSET 0x00a8
+#define GRF_GPIO0B_IOMUX_OFFSET 0x00ac
+#define GRF_GPIO0C_IOMUX_OFFSET 0x00b0
+#define GRF_GPIO0D_IOMUX_OFFSET 0x00b4
+
+#define GRF_GPIO1A_IOMUX_OFFSET 0x00b8
+#define GRF_GPIO1B_IOMUX_OFFSET 0x00bc
+#define GRF_GPIO1C_IOMUX_OFFSET 0x00c0
+#define GRF_GPIO1D_IOMUX_OFFSET 0x00c4
+
+#define GRF_GPIO2A_IOMUX_OFFSET 0x00c8
+#define GRF_GPIO2B_IOMUX_OFFSET 0x00cc
+#define GRF_GPIO2C_IOMUX_OFFSET 0x00d0
+#define GRF_GPIO2D_IOMUX_OFFSET 0x00d4
+
+#define GRF_GPIO3A_IOMUX_OFFSET 0x00d8
+#define GRF_GPIO3B_IOMUX_OFFSET 0x00dc
+#define GRF_GPIO3C_IOMUX_OFFSET 0x00e0
+#define GRF_GPIO3D_IOMUX_OFFSET 0x00e4
+
+#define GRF_GPIO4A_IOMUX_OFFSET 0x00e8
+#define GRF_GPIO4B_IOMUX_OFFSET 0x00ec
+#define GRF_GPIO4C_IOMUX_OFFSET 0x00f0
+#define GRF_GPIO4D_IOMUX_OFFSET 0x00f4
+
+#define GRF_GPIO6B_IOMUX_OFFSET 0x010c
+
+#define GRF_SOC_CON0_OFFSET 0x0150
+#define GRF_SOC_CON1_OFFSET 0x0154
+#define GRF_SOC_CON2_OFFSET 0x0158
+
+static void
+obio_init_rk3066(void)
+{
+ /* dwctwo[01] */
+ obio_grf_set(GRF_GPIO0A_IOMUX_OFFSET, 0x14001400);
+
+ /* com2 */
+ obio_grf_set(GRF_GPIO1B_IOMUX_OFFSET, 0x00050005);
+
+ /* rkemac0 */
+ obio_grf_set(GRF_GPIO1C_IOMUX_OFFSET, 0xffffaaaa);
+ obio_grf_set(GRF_GPIO1D_IOMUX_OFFSET, 0x000f000a);
+ obio_grf_set(GRF_SOC_CON1_OFFSET, 0x00030002);
+ obio_grf_set(GRF_SOC_CON2_OFFSET, 0x00400040);
+
+ /* rkiic[01234] */
+ obio_grf_set(GRF_GPIO2D_IOMUX_OFFSET, 0x55005500);
+ obio_grf_set(GRF_GPIO3A_IOMUX_OFFSET, 0x05550555);
+ obio_grf_set(GRF_SOC_CON1_OFFSET, 0xf800f800);
+
+ /* dwcmmc0 */
+ obio_grf_set(GRF_GPIO3A_IOMUX_OFFSET, 0x50004000);
+ obio_grf_set(GRF_GPIO3B_IOMUX_OFFSET, 0x55551555);
+
+ /* ChipSPARK Rayeager PX2: dwcmmc2 */
+ obio_grf_set(GRF_GPIO3D_IOMUX_OFFSET, 0xc0008000);
+ obio_grf_set(GRF_GPIO4B_IOMUX_OFFSET, 0x003c0008);
+ obio_grf_set(GRF_SOC_CON0_OFFSET, 0x08000800);
+
+ /* ChipSPARK Rayeager PX2: umass0 */
+ obio_grf_set(GRF_GPIO0B_IOMUX_OFFSET, 0x04000000);
+ obio_grf_set(GRF_GPIO4C_IOMUX_OFFSET, 0x30000000);
+ obio_gpio_set_out(0, 13, 1);
+ obio_gpio_set_out(4, 22, 1);
+
+ /* ChipSPARK Rayeager PX2: uhub2 */
+ obio_grf_set(GRF_GPIO1D_IOMUX_OFFSET, 0x40000000);
+ obio_gpio_set_out(1, 31, 1);
+
+ /* ChipSPARK Rayeager PX2: ukphy0 */
+ /* rtl8201f: clock must be configured before resetting */
+ rockchip_mac_set_rate(50000000);
+ obio_grf_set(GRF_GPIO1D_IOMUX_OFFSET, 0x10000000);
+ obio_gpio_set_out(1, 30, 1);
+ /* rtl8201f: need 1s delay here? */
+}
+
#define RK3188_GRF_GPIO0C_IOMUX_OFFSET 0x0068
-#define RK3188_GRF_GPIO0D_IOMUX_OFFSET 0x006C
+#define RK3188_GRF_GPIO0D_IOMUX_OFFSET 0x006c
#define RK3188_GRF_GPIO1A_IOMUX_OFFSET 0x0070
#define RK3188_GRF_GPIO1B_IOMUX_OFFSET 0x0074
#define RK3188_GRF_GPIO1C_IOMUX_OFFSET 0x0078
-#define RK3188_GRF_GPIO1D_IOMUX_OFFSET 0x007C
+#define RK3188_GRF_GPIO1D_IOMUX_OFFSET 0x007c
#define RK3188_GRF_GPIO2A_IOMUX_OFFSET 0x0080
#define RK3188_GRF_GPIO2B_IOMUX_OFFSET 0x0084
#define RK3188_GRF_GPIO2C_IOMUX_OFFSET 0x0088
-#define RK3188_GRF_GPIO2D_IOMUX_OFFSET 0x008C
+#define RK3188_GRF_GPIO2D_IOMUX_OFFSET 0x008c
#define RK3188_GRF_GPIO3A_IOMUX_OFFSET 0x0090
#define RK3188_GRF_GPIO3B_IOMUX_OFFSET 0x0094
#define RK3188_GRF_GPIO3C_IOMUX_OFFSET 0x0098
-#define RK3188_GRF_GPIO3D_IOMUX_OFFSET 0x009C
+#define RK3188_GRF_GPIO3D_IOMUX_OFFSET 0x009c
-#define RK3188_GRF_SOC_CON0_OFFSET 0x00A0
-#define RK3188_GRF_SOC_CON1_OFFSET 0x00A4
-#define RK3188_GRF_SOC_CON2_OFFSET 0x00A8
-#define RK3188_GRF_SOC_STATUS_OFFSET 0x00AC
+#define RK3188_GRF_SOC_CON0_OFFSET 0x00a0
+#define RK3188_GRF_SOC_CON1_OFFSET 0x00a4
+#define RK3188_GRF_SOC_CON2_OFFSET 0x00a8
-#define RK3188_GRF_IO_CON2_OFFSET 0x00FC
+#define RK3188_GRF_IO_CON2_OFFSET 0x00fc
#define RK3188_GRF_IO_CON3_OFFSET 0x0100
-#define GRF_GPIO0A_IOMUX_OFFSET 0x00a8
-#define GRF_GPIO3A_IOMUX_OFFSET 0x00d8
-#define GRF_GPIO3B_IOMUX_OFFSET 0x00dc
-
-void obio_init_grf(void)
+static void
+obio_init_rk3188(void)
{
-#if 1
- /* Radxa Rock */
- obio_iomux(RK3188_GRF_GPIO3A_IOMUX_OFFSET, 0x55555554); /* MMC0 */
- obio_iomux(RK3188_GRF_GPIO3B_IOMUX_OFFSET, 0x00050001); /* MMC0 */
- obio_iomux(RK3188_GRF_IO_CON2_OFFSET, 0x00c000c0); /* MMC0 */
- obio_iomux(RK3188_GRF_GPIO3D_IOMUX_OFFSET, 0x3c000000); /* VBUS */
- obio_iomux(RK3188_GRF_GPIO1D_IOMUX_OFFSET, 0x55555555); /* I2C[0124] */
- obio_iomux(RK3188_GRF_GPIO3B_IOMUX_OFFSET, 0xa000a000); /* I2C3 */
- obio_iomux(RK3188_GRF_SOC_CON1_OFFSET, 0xf800f800); /* I2C[01234] */
-
-// obio_iomux(RK3188_GRF_GPIO0C_IOMUX_OFFSET, 0x00030000); /* PHY */
- obio_iomux(RK3188_GRF_GPIO3C_IOMUX_OFFSET, 0xffffaaaa); /* PHY */
- obio_iomux(RK3188_GRF_GPIO3D_IOMUX_OFFSET, 0x003f000a); /* PHY */
- obio_iomux(RK3188_GRF_SOC_CON1_OFFSET, 0x00030002); /* VMAC */
- obio_iomux(RK3188_GRF_IO_CON3_OFFSET, 0x000f000f); /* VMAC */
-#else
- /* ChipSPARK Rayeager PX2 */
- obio_iomux(GRF_GPIO0A_IOMUX_OFFSET, 0x14000000); /* VBUS */
- obio_iomux(GRF_GPIO3A_IOMUX_OFFSET, 0x50004000); /* MMC0 */
- obio_iomux(GRF_GPIO3B_IOMUX_OFFSET, 0x55551555); /* MMC0 */
-#endif
+ /* com2 */
+ obio_grf_set(RK3188_GRF_GPIO1B_IOMUX_OFFSET, 0x000f0005);
+
+ /* rkiic[01234] */
+ obio_grf_set(RK3188_GRF_GPIO1D_IOMUX_OFFSET, 0x55555555);
+ obio_grf_set(RK3188_GRF_GPIO3B_IOMUX_OFFSET, 0xa000a000);
+ obio_grf_set(RK3188_GRF_SOC_CON1_OFFSET, 0xf800f800);
+
+ /* dwcmmc0 */
+ obio_grf_set(RK3188_GRF_GPIO3A_IOMUX_OFFSET, 0x55555554);
+ obio_grf_set(RK3188_GRF_GPIO3B_IOMUX_OFFSET, 0x00050001);
+ //obio_grf_set(RK3188_GRF_IO_CON2_OFFSET, 0x00c000c0);
+
+ /* rkemac0 */
+ obio_grf_set(RK3188_GRF_GPIO3C_IOMUX_OFFSET, 0xffffaaaa);
+ obio_grf_set(RK3188_GRF_GPIO3D_IOMUX_OFFSET, 0x000f000a);
+ obio_grf_set(RK3188_GRF_SOC_CON1_OFFSET, 0x00030002);
+ obio_grf_set(RK3188_GRF_SOC_CON2_OFFSET, 0x00400040);
+ obio_grf_set(RK3188_GRF_IO_CON3_OFFSET, 0x000f000f);
+
+ /* dwcotg[01] */
+ obio_grf_set(RK3188_GRF_GPIO3D_IOMUX_OFFSET, 0x3c003c00);
+
+ /* Radxa Rock: dwcotg[01] */
+ //obio_grf_set(RK3188_GRF_GPIO3D_IOMUX_OFFSET, 0x3c000000);
+ obio_grf_set(RK3188_GRF_GPIO2D_IOMUX_OFFSET, 0x40000000);
+ obio_gpio_set_out(0, 3, 1);
+ obio_gpio_set_out(2, 31, 1);
+
+ /* Radxa Rock: IT66121 HDMI */
+ obio_gpio_set_out(3, 10, 1);
+
+ /* Radxa Rock: ukphy0 */
+ obio_gpio_set_out(3, 26, 1); /* XXX: RMII_INT, input, active low */
+
+ /* Minix Neo X7: cdce0 */
+ obio_gpio_set_out(0, 30, 1);
}
-void obio_iomux(int offset, int new)
+static void
+obio_grf_set(uint32_t offset, uint32_t value)
{
bus_space_handle_t bh;
bus_space_tag_t bt = &rockchip_bs_tag;
- int old, renew;
+ uint32_t old, new;
bus_space_subregion(bt, rockchip_core1_bsh, ROCKCHIP_GRF_OFFSET,
ROCKCHIP_GRF_SIZE, &bh);
old = bus_space_read_4(bt, bh, offset);
- bus_space_write_4(bt, bh, offset, new);
- renew = bus_space_read_4(bt, bh, offset);
+ bus_space_write_4(bt, bh, offset, value);
+ new = bus_space_read_4(bt, bh, offset);
- printf("grf iomux: old %08x, new %08x, renew %08x\n", old, new, renew);
+ printf("grf: %04x: 0x%08x 0x%08x -> 0x%08x\n", offset, old, value, new);
}
#define GPIO_SWPORTA_DR_OFFSET 0x00
-#define GPIO_SWPORTA_DD_OFFSET 0x04
+#define GPIO_SWPORTA_DDR_OFFSET 0x04
-void obio_init_gpio(void)
-{
-#if 1
- /* Radxa Rock */
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
- obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
- obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
-
- /* PHY */
- obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(26));
- obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(26));
-
- /* Minix Neo X7 USB ethernet */
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(30));
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(30));
-
- /* IT66121 HDMI */
- obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(10));
- obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(10));
-#else
- /* ChipSPARK Rayeager PX2 */
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(5));
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(5));
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(6));
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(6));
- obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
- obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
-#endif
-}
-
-void obio_swporta(int gpio_base, int offset, int new)
+static int
+obio_gpio_set_out(u_int unit, u_int pin, u_int value)
{
bus_space_handle_t bh;
bus_space_tag_t bt = &rockchip_bs_tag;
- int old, renew;
- int gpio_size = 0x100; /* XXX */
+ uint32_t gpio_base = 0, gpio_size = 0;
+ uint32_t old, new;
+
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ switch (unit) {
+ case 0:
+ gpio_base = ROCKCHIP_GPIO0_OFFSET;
+ gpio_size = ROCKCHIP_GPIO0_SIZE;
+ break;
+ case 1:
+ gpio_base = ROCKCHIP_GPIO1_OFFSET;
+ gpio_size = ROCKCHIP_GPIO1_SIZE;
+ break;
+ case 2:
+ gpio_base = ROCKCHIP_GPIO2_OFFSET;
+ gpio_size = ROCKCHIP_GPIO2_SIZE;
+ break;
+ case 3:
+ gpio_base = ROCKCHIP_GPIO3_OFFSET;
+ gpio_size = ROCKCHIP_GPIO3_SIZE;
+ break;
+ case 4:
+ gpio_base = ROCKCHIP_GPIO4_OFFSET;
+ gpio_size = ROCKCHIP_GPIO4_SIZE;
+ break;
+ case 6:
+ gpio_base = ROCKCHIP_GPIO6_OFFSET;
+ gpio_size = ROCKCHIP_GPIO6_SIZE;
+ break;
+ }
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ switch (unit) {
+ case 0:
+ gpio_base = ROCKCHIP_RK3188_GPIO0_OFFSET;
+ gpio_size = ROCKCHIP_RK3188_GPIO0_SIZE;
+ break;
+ case 1:
+ gpio_base = ROCKCHIP_GPIO1_OFFSET;
+ gpio_size = ROCKCHIP_GPIO1_SIZE;
+ break;
+ case 2:
+ gpio_base = ROCKCHIP_GPIO2_OFFSET;
+ gpio_size = ROCKCHIP_GPIO2_SIZE;
+ break;
+ case 3:
+ gpio_base = ROCKCHIP_GPIO3_OFFSET;
+ gpio_size = ROCKCHIP_GPIO3_SIZE;
+ break;
+ }
+ break;
+ }
+
+ if (gpio_base == 0 || gpio_size == 0 || pin > 31)
+ return EINVAL;
bus_space_subregion(bt, rockchip_core1_bsh, gpio_base, gpio_size, &bh);
- old = bus_space_read_4(bt, bh, offset);
- bus_space_write_4(bt, bh, offset, old | new);
- renew = bus_space_read_4(bt, bh, offset);
+ old = bus_space_read_4(bt, bh, GPIO_SWPORTA_DR_OFFSET);
+ if (value)
+ new = old | __BIT(pin);
+ else
+ new = old & ~__BIT(pin);
+ bus_space_write_4(bt, bh, GPIO_SWPORTA_DR_OFFSET, new);
+ new = bus_space_read_4(bt, bh, GPIO_SWPORTA_DR_OFFSET);
+ printf("gpio%d: dr 0x%08x -> 0x%08x\n", unit, old, new);
+
+ old = bus_space_read_4(bt, bh, GPIO_SWPORTA_DDR_OFFSET);
+ bus_space_write_4(bt, bh, GPIO_SWPORTA_DDR_OFFSET, old | __BIT(pin));
+ new = bus_space_read_4(bt, bh, GPIO_SWPORTA_DDR_OFFSET);
+ printf("gpio%d: ddr 0x%08x -> 0x%08x\n", unit, old, new);
- printf("gpio: 0x%08x 0x%08x -> 0x%08x\n", gpio_base + offset, old, renew);
+ return 0;
}
#ifdef ROCKCHIP_CLOCK_DEBUG
Index: src/sys/arch/arm/rockchip/rockchip_board.c
diff -u src/sys/arch/arm/rockchip/rockchip_board.c:1.12 src/sys/arch/arm/rockchip/rockchip_board.c:1.13
--- src/sys/arch/arm/rockchip/rockchip_board.c:1.12 Sun Jan 4 11:52:45 2015
+++ src/sys/arch/arm/rockchip/rockchip_board.c Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_board.c,v 1.12 2015/01/04 11:52:45 jmcneill Exp $ */
+/* $NetBSD: rockchip_board.c,v 1.13 2015/01/17 15:05:24 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_rockchip.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.12 2015/01/04 11:52:45 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.13 2015/01/17 15:05:24 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -62,18 +62,39 @@ rockchip_bootstrap(void)
panic("%s: failed to map CORE1 registers: %d", __func__, error);
}
-bool
-rockchip_is_chip(const char *chipver)
+uint32_t
+rockchip_chip_id(void)
{
- const size_t chipver_len = 16;
- char *env_chipver;
+ static uint32_t chip_id = 0;
+ char *chipver;
- if (get_bootconf_option(boot_args, "chipver",
- BOOTOPT_TYPE_STRING, &env_chipver) == 0) {
- return false;
+ if (!chip_id) {
+ if (get_bootconf_option(boot_args, "chipver",
+ BOOTOPT_TYPE_STRING, &chipver) == 0) {
+ return 0;
+ } else if (strncmp(chipver, "300A20111111V101", 16) == 0) {
+ chip_id = ROCKCHIP_CHIP_ID_RK3066;
+ } else if (strncmp(chipver, "310B20121130V100", 16) == 0) {
+ chip_id = ROCKCHIP_CHIP_ID_RK3188;
+ } else if (strncmp(chipver, "310B20130131V101", 16) == 0) {
+ chip_id = ROCKCHIP_CHIP_ID_RK3188PLUS;
+ }
}
- return strncmp(env_chipver, chipver, chipver_len) == 0;
+ return chip_id;
+}
+
+const char *
+rockchip_chip_name(void)
+{
+ uint32_t chip_id = rockchip_chip_id();
+
+ switch (chip_id) {
+ case ROCKCHIP_CHIP_ID_RK3066: return "RK3066";
+ case ROCKCHIP_CHIP_ID_RK3188: return "RK3188";
+ case ROCKCHIP_CHIP_ID_RK3188PLUS: return "RK3188+";
+ default: return "Rockchip";
+ }
}
static void
@@ -97,8 +118,20 @@ rockchip_pll_get_rate(bus_size_t con0_re
pll_con1 = bus_space_read_4(bst, bsh, con1_reg);
nr = __SHIFTOUT(pll_con0, CRU_PLL_CON0_CLKR) + 1;
- no = __SHIFTOUT(pll_con0, CRU_PLL_CON0_CLKOD) + 1;
- nf = __SHIFTOUT(pll_con1, CRU_PLL_CON1_CLKF) + 1;
+
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ no = __SHIFTOUT(pll_con0, CRU_PLL_CON0_CLKOD) + 1;
+ nf = __SHIFTOUT(pll_con1, CRU_PLL_CON1_CLKF) + 1;
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ no = __SHIFTOUT(pll_con0, RK3188_CRU_PLL_CON0_CLKOD) + 1;
+ nf = __SHIFTOUT(pll_con1, RK3188_CRU_PLL_CON1_CLKF) + 1;
+ break;
+ default:
+ return EINVAL;
+ }
#ifdef ROCKCHIP_CLOCK_DEBUG
printf("%s: %#x %#x: nr=%d no=%d nf=%d\n", __func__,
@@ -106,7 +139,7 @@ rockchip_pll_get_rate(bus_size_t con0_re
nr, no, nf);
#endif
- return (ROCKCHIP_REF_FREQ * nf) / (nr * no);
+ return ((uint64_t)ROCKCHIP_REF_FREQ * nf) / (nr * no);
}
u_int
@@ -139,31 +172,34 @@ rockchip_cpu_get_rate(void)
bus_space_tag_t bst = &rockchip_bs_tag;
bus_space_handle_t bsh;
uint32_t clksel_con0;
- uint32_t a9_core_div_con;
- u_int rate;
+ u_int a9_core_div;
rockchip_get_cru_bsh(&bsh);
clksel_con0 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(0));
- if (clksel_con0 & CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL) {
- rate = rockchip_gpll_get_rate();
- } else {
- rate = rockchip_apll_get_rate();
- }
-
- if (rockchip_is_chip(ROCKCHIP_CHIPVER_RK3066)) {
- a9_core_div_con = __SHIFTOUT(clksel_con0,
- CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
- } else {
- a9_core_div_con = __SHIFTOUT(clksel_con0,
- RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ a9_core_div = __SHIFTOUT(clksel_con0,
+ CRU_CLKSEL_CON0_A9_CORE_DIV_CON) + 1;
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ a9_core_div = __SHIFTOUT(clksel_con0,
+ RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON) + 1;
+ break;
+ default:
+ return EINVAL;
}
#ifdef ROCKCHIP_CLOCK_DEBUG
printf("%s: clksel_con0=%#x\n", __func__, clksel_con0);
#endif
- return rate / (a9_core_div_con + 1);
+ if (clksel_con0 & CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL) {
+ return rockchip_gpll_get_rate() / a9_core_div;
+ } else {
+ return rockchip_apll_get_rate() / a9_core_div;
+ }
}
u_int
@@ -172,17 +208,15 @@ rockchip_a9periph_get_rate(void)
bus_space_tag_t bst = &rockchip_bs_tag;
bus_space_handle_t bsh;
uint32_t clksel_con0;
- uint32_t core_peri_div_con;
- u_int rate;
+ u_int core_peri_div;
rockchip_get_cru_bsh(&bsh);
clksel_con0 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(0));
- rate = rockchip_cpu_get_rate();
- core_peri_div_con = __SHIFTOUT(clksel_con0,
- CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
+ core_peri_div = 1 << (__SHIFTOUT(clksel_con0,
+ CRU_CLKSEL_CON0_CORE_PERI_DIV_CON) + 1);
- return rate / ((1 << core_peri_div_con) * 2);
+ return rockchip_cpu_get_rate() / core_peri_div;
}
u_int
@@ -191,13 +225,25 @@ rockchip_pclk_cpu_get_rate(void)
bus_space_tag_t bst = &rockchip_bs_tag;
bus_space_handle_t bsh;
uint32_t clksel_con1;
- u_int core_axi_div, pclk_div;
+ u_int aclk_div, core_axi_div, pclk_div;
rockchip_get_cru_bsh(&bsh);
clksel_con1 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(1));
- switch (__SHIFTOUT(clksel_con1,
- RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON)) {
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ aclk_div = __SHIFTOUT(clksel_con1,
+ CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ aclk_div = __SHIFTOUT(clksel_con1,
+ RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
+ break;
+ default:
+ return EINVAL;
+ }
+ switch (aclk_div) {
case 0: core_axi_div = 1; break;
case 1: core_axi_div = 2; break;
case 2: core_axi_div = 3; break;
@@ -218,17 +264,39 @@ rockchip_ahb_get_rate(void)
bus_space_handle_t bsh;
uint32_t clksel_con10;
uint32_t hclk_div, aclk_div;
+ u_int rate;
rockchip_get_cru_bsh(&bsh);
clksel_con10 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(10));
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ if (clksel_con10 & CRU_CLKSEL_CON10_PERI_PLL_SEL) {
+ rate = rockchip_cpll_get_rate();
+ } else {
+ rate = rockchip_gpll_get_rate();
+ }
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ if (clksel_con10 & CRU_CLKSEL_CON10_PERI_PLL_SEL) {
+ rate = rockchip_gpll_get_rate();
+ } else {
+ rate = rockchip_cpll_get_rate();
+ }
+ break;
+ default:
+ return EINVAL;
+ }
+ aclk_div = __SHIFTOUT(clksel_con10,
+ CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON) + 1;
+ hclk_div = 1 << __SHIFTOUT(clksel_con10,
+ CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON);
- hclk_div = __SHIFTOUT(clksel_con10,
- CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON) + 1;
- aclk_div = 1 << __SHIFTOUT(clksel_con10,
- CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON);
+ if (hclk_div > 4)
+ return EINVAL;
- return rockchip_gpll_get_rate() / (hclk_div * aclk_div);
+ return rate / (aclk_div * hclk_div);
}
u_int
@@ -238,17 +306,37 @@ rockchip_apb_get_rate(void)
bus_space_handle_t bsh;
uint32_t clksel_con10;
uint32_t pclk_div, aclk_div;
+ u_int rate;
rockchip_get_cru_bsh(&bsh);
clksel_con10 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(10));
- pclk_div = __SHIFTOUT(clksel_con10,
- CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON) + 1;
- aclk_div = 1 << __SHIFTOUT(clksel_con10,
- CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON);
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ if (clksel_con10 & CRU_CLKSEL_CON10_PERI_PLL_SEL) {
+ rate = rockchip_cpll_get_rate();
+ } else {
+ rate = rockchip_gpll_get_rate();
+ }
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ if (clksel_con10 & CRU_CLKSEL_CON10_PERI_PLL_SEL) {
+ rate = rockchip_gpll_get_rate();
+ } else {
+ rate = rockchip_cpll_get_rate();
+ }
+ break;
+ default:
+ return EINVAL;
+ }
+ aclk_div = __SHIFTOUT(clksel_con10,
+ CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON) + 1;
+ pclk_div = 1 << __SHIFTOUT(clksel_con10,
+ CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON);
- return rockchip_gpll_get_rate() / (pclk_div * aclk_div);
+ return rate / (aclk_div * pclk_div);
}
u_int
@@ -257,16 +345,16 @@ rockchip_mmc0_get_rate(void)
bus_space_tag_t bst = &rockchip_bs_tag;
bus_space_handle_t bsh;
uint32_t clksel_con11;
- uint32_t mmc0_div_con;
+ u_int mmc0_div;
rockchip_get_cru_bsh(&bsh);
clksel_con11 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(11));
- mmc0_div_con = __SHIFTOUT(clksel_con11,
- CRU_CLKSEL_CON11_MMC0_DIV_CON);
+ mmc0_div = __SHIFTOUT(clksel_con11,
+ CRU_CLKSEL_CON11_MMC0_DIV_CON) + 1;
- return rockchip_ahb_get_rate() / (mmc0_div_con + 1);
+ return rockchip_ahb_get_rate() / mmc0_div;
}
u_int
@@ -281,9 +369,7 @@ rockchip_mmc0_set_div(u_int div)
rockchip_get_cru_bsh(&bsh);
- clksel_con11 = CRU_CLKSEL_CON11_MMC0_PLL_SEL_MASK |
- CRU_CLKSEL_CON11_MMC0_DIV_CON_MASK;
- clksel_con11 |= CRU_CLKSEL_CON11_MMC0_PLL_SEL; /* GPLL */
+ clksel_con11 = CRU_CLKSEL_CON11_MMC0_DIV_CON_MASK;
clksel_con11 |= __SHIFTIN(div - 1, CRU_CLKSEL_CON11_MMC0_DIV_CON);
#ifdef ROCKCHIP_CLOCK_DEBUG
@@ -321,19 +407,18 @@ rockchip_mac_get_rate(void)
bus_space_tag_t bst = &rockchip_bs_tag;
bus_space_handle_t bsh;
uint32_t clksel_con21;
- uint32_t mac_div_con;
+ u_int mac_div;
rockchip_get_cru_bsh(&bsh);
clksel_con21 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(21));
-
- mac_div_con = __SHIFTOUT(clksel_con21,
- CRU_CLKSEL_CON21_MAC_DIV_CON);
+ mac_div = __SHIFTOUT(clksel_con21,
+ CRU_CLKSEL_CON21_MAC_DIV_CON) + 1;
if (clksel_con21 & CRU_CLKSEL_CON21_MAC_PLL_SEL) {
- return rockchip_dpll_get_rate() / (mac_div_con + 1);
+ return rockchip_dpll_get_rate() / mac_div;
} else {
- return rockchip_gpll_get_rate() / (mac_div_con + 1);
+ return rockchip_gpll_get_rate() / mac_div;
}
}
Index: src/sys/arch/arm/rockchip/rockchip_cpufreq.c
diff -u src/sys/arch/arm/rockchip/rockchip_cpufreq.c:1.1 src/sys/arch/arm/rockchip/rockchip_cpufreq.c:1.2
--- src/sys/arch/arm/rockchip/rockchip_cpufreq.c:1.1 Fri Jan 2 21:59:29 2015
+++ src/sys/arch/arm/rockchip/rockchip_cpufreq.c Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_cpufreq.c,v 1.1 2015/01/02 21:59:29 jmcneill Exp $ */
+/* $NetBSD: rockchip_cpufreq.c,v 1.2 2015/01/17 15:05:24 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -30,7 +30,7 @@
#include "act8846pm.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rockchip_cpufreq.c,v 1.1 2015/01/02 21:59:29 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rockchip_cpufreq.c,v 1.2 2015/01/17 15:05:24 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -85,17 +85,17 @@ rockchip_cpufreq_init(void)
bus_space_subregion(bst, rockchip_core1_bsh, ROCKCHIP_GRF_OFFSET,
ROCKCHIP_GRF_SIZE, &grf_bsh);
- if (rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188) ||
- rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188PLUS)) {
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066: /* XXX */
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
cpufreq_set_rate = &rk3188_cpu_set_rate;
cpufreq_get_rate = &rk3188_cpu_get_rate;
cpufreq_get_available = &rk3188_cpu_get_available;
- }
-
- if (cpufreq_set_rate == NULL ||
- cpufreq_get_rate == NULL ||
- cpufreq_get_available == NULL)
+ break;
+ default:
return;
+ }
nfreq = cpufreq_get_available(availfreq, ROCKCHIP_CPUFREQ_MAX);
if (nfreq == 0)
@@ -227,8 +227,10 @@ static const struct rk3188_apll_rate rk3
RK3188_RATE( 600, 50, 2, 4, 4, 3, 2, 4, 2, 1000),
};
-#define RK3188_GRF_STATUS0_REG 0x00ac
-#define RK3188_GRF_STATUS0_APLL_LOCK __BIT(6)
+#define GRF_STATUS0_REG 0x015c
+#define GRF_STATUS0_APLL_LOCK __BIT(5)
+#define RK3188_GRF_STATUS0_REG 0x00ac
+#define RK3188_GRF_STATUS0_APLL_LOCK __BIT(6)
static size_t
rk3188_cpu_get_available(u_int *pavail, size_t maxavail)
@@ -255,25 +257,26 @@ rk3188_cpu_set_rate(u_int rate)
{
const struct rk3188_apll_rate *r = NULL;
uint32_t apll_con0, apll_con1, apll_con2, clksel0_con, clksel1_con;
- uint32_t reset_mask, reset;
+ uint32_t reset_mask, reset, status0_reg, status0_apll_lock;
u_int cpu_aclk_div_con;
- const bool rk3188plus_p = rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188PLUS);
- device_t pmic;
u_int old_rate = rk3188_cpu_get_rate();
u_int new_rate;
#if NACT8846PM > 0
+ device_t pmic;
struct act8846_ctrl *dcdc3;
-#endif
-
-#ifdef ROCKCHIP_CLOCK_DEBUG
- printf("%s: rate=%u rk3188plus_p=%d\n", __func__, rate, rk3188plus_p);
-#endif
pmic = device_find_by_driver_unit("act8846pm", 0);
if (pmic == NULL) {
printf("%s: no PMIC driver found\n", __func__);
return ENXIO;
}
+ dcdc3 = act8846_lookup(pmic, "DCDC3");
+ KASSERT(dcdc3 != NULL);
+#endif
+
+#ifdef ROCKCHIP_CLOCK_DEBUG
+ printf("%s: rate=%u\n", __func__, rate);
+#endif
/* Pick the closest rate (nearest 100MHz increment) */
for (int i = 0; i < __arraycount(rk3188_apll_rates); i++) {
@@ -291,59 +294,34 @@ rk3188_cpu_set_rate(u_int rate)
return EINVAL;
}
-#if NACT8846PM > 0
- dcdc3 = act8846_lookup(pmic, "DCDC3");
- KASSERT(dcdc3 != NULL);
-#endif
-
-#ifdef ROCKCHIP_CLOCK_DEBUG
- printf("%s: Set frequency to %u MHz...\n", __func__, r->rate);
-#endif
-
- new_rate = r->rate / 1000000;
- if (new_rate > old_rate) {
-#if NACT8846PM > 0
- act8846_set_voltage(dcdc3, r->voltage, r->voltage);
-#endif
- }
-
- if (rk3188plus_p) {
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
reset_mask = CRU_PLL_CON3_RESET_MASK;
reset = CRU_PLL_CON3_RESET;
- } else {
- reset_mask = CRU_PLL_CON3_POWER_DOWN_MASK;
- reset = CRU_PLL_CON3_POWER_DOWN;
- }
-
- apll_con0 = CRU_PLL_CON0_CLKR_MASK | CRU_PLL_CON0_CLKOD_MASK;
- apll_con0 |= __SHIFTIN(r->no - 1, CRU_PLL_CON0_CLKOD);
- apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
-
- apll_con1 = CRU_PLL_CON1_CLKF_MASK;
- apll_con1 |= __SHIFTIN(r->nf - 1, CRU_PLL_CON1_CLKF);
-
- if (rk3188plus_p) {
+ apll_con0 = CRU_PLL_CON0_CLKR_MASK | CRU_PLL_CON0_CLKOD_MASK;
+ apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
+ apll_con0 |= __SHIFTIN(r->no - 1, CRU_PLL_CON0_CLKOD);
+ apll_con1 = CRU_PLL_CON1_CLKF_MASK;
+ apll_con1 |= __SHIFTIN(r->nf - 1, CRU_PLL_CON1_CLKF);
apll_con2 = CRU_PLL_CON2_BWADJ_MASK;
apll_con2 |= __SHIFTIN(r->nf >> 1, CRU_PLL_CON2_BWADJ);
- } else {
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ reset_mask = CRU_PLL_CON3_POWER_DOWN_MASK;
+ reset = CRU_PLL_CON3_POWER_DOWN;
+ apll_con0 =
+ CRU_PLL_CON0_CLKR_MASK | RK3188_CRU_PLL_CON0_CLKOD_MASK;
+ apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
+ apll_con0 |= __SHIFTIN(r->no - 1, RK3188_CRU_PLL_CON0_CLKOD);
+ apll_con1 = RK3188_CRU_PLL_CON1_CLKF_MASK;
+ apll_con1 |= __SHIFTIN(r->nf - 1, RK3188_CRU_PLL_CON1_CLKF);
apll_con2 = 0;
+ break;
+ default:
+ return EINVAL;
}
- clksel0_con = RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
- CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK |
- CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK;
- clksel0_con |= __SHIFTIN(r->core_div - 1,
- RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
- clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
- CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
- clksel0_con |= __SHIFTIN(r->aclk_div - 1,
- CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
-
- clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
- CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
- CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
- RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
-
switch (r->core_axi_div) {
case 1: cpu_aclk_div_con = 0; break;
case 2: cpu_aclk_div_con = 1; break;
@@ -352,16 +330,59 @@ rk3188_cpu_set_rate(u_int rate)
case 8: cpu_aclk_div_con = 4; break;
default: panic("bad core_axi_div");
}
- clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
- CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
- clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
- CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
- clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
- CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
- clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
- RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
+
+ switch (rockchip_chip_id()) {
+ case ROCKCHIP_CHIP_ID_RK3066:
+ clksel0_con = CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
+ CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK;
+ clksel0_con |= __SHIFTIN(r->core_div - 1,
+ CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
+ clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
+ CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
+ clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
+ CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
+ CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
+ CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
+ clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
+ CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
+ clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
+ CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
+ clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
+ CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
+ clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
+ CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
+ status0_reg = GRF_STATUS0_REG;
+ status0_apll_lock = GRF_STATUS0_APLL_LOCK;
+ break;
+ case ROCKCHIP_CHIP_ID_RK3188:
+ case ROCKCHIP_CHIP_ID_RK3188PLUS:
+ clksel0_con = RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
+ CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK;
+ clksel0_con |= __SHIFTIN(r->core_div - 1,
+ RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
+ clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
+ CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
+ clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
+ CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
+ CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
+ RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
+ clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
+ CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
+ clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
+ CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
+ clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
+ CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
+ clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
+ RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
+ status0_reg = RK3188_GRF_STATUS0_REG;
+ status0_apll_lock = RK3188_GRF_STATUS0_APLL_LOCK;
+ break;
+ default:
+ return EINVAL;
+ }
#ifdef ROCKCHIP_CLOCK_DEBUG
+ printf("%s: Set frequency to %u MHz...\n", __func__, r->rate);
printf("before: APLL_CON0: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_APLL_CON0_REG));
printf("before: APLL_CON1: %#x\n",
@@ -372,6 +393,13 @@ rk3188_cpu_set_rate(u_int rate)
bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(1)));
#endif
+ new_rate = r->rate / 1000000;
+ if (new_rate > old_rate) {
+#if NACT8846PM > 0
+ act8846_set_voltage(dcdc3, r->voltage, r->voltage);
+#endif
+ }
+
bus_space_write_4(bst, cru_bsh, CRU_MODE_CON_REG,
CRU_MODE_CON_APLL_WORK_MODE_MASK |
__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_SLOW,
@@ -400,12 +428,9 @@ rk3188_cpu_set_rate(u_int rate)
;
int retry = ROCKCHIP_REF_FREQ;
while (--retry > 0) {
- uint32_t status = bus_space_read_4(bst, grf_bsh,
- RK3188_GRF_STATUS0_REG);
- if (status & RK3188_GRF_STATUS0_APLL_LOCK)
+ uint32_t status = bus_space_read_4(bst, grf_bsh, status0_reg);
+ if (status & status0_apll_lock)
break;
- for (volatile int i = 1000; i >= 0; i--)
- ;
}
if (retry == 0)
printf("%s: PLL lock timeout\n", __func__);
Index: src/sys/arch/arm/rockchip/rockchip_timer.c
diff -u src/sys/arch/arm/rockchip/rockchip_timer.c:1.1 src/sys/arch/arm/rockchip/rockchip_timer.c:1.2
--- src/sys/arch/arm/rockchip/rockchip_timer.c:1.1 Fri Jan 2 23:20:18 2015
+++ src/sys/arch/arm/rockchip/rockchip_timer.c Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_timer.c,v 1.1 2015/01/02 23:20:18 jmcneill Exp $ */
+/* $NetBSD: rockchip_timer.c,v 1.2 2015/01/17 15:05:24 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rockchip_timer.c,v 1.1 2015/01/02 23:20:18 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rockchip_timer.c,v 1.2 2015/01/17 15:05:24 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -65,6 +65,10 @@ CFATTACH_DECL_NEW(rktimer, sizeof(struct
static int
rktimer_match(device_t parent, cfdata_t cf, void *aux)
{
+
+ if (rockchip_chip_id() == ROCKCHIP_CHIP_ID_RK3066)
+ return 0;
+
return 1;
}
Index: src/sys/arch/arm/rockchip/rockchip_crureg.h
diff -u src/sys/arch/arm/rockchip/rockchip_crureg.h:1.7 src/sys/arch/arm/rockchip/rockchip_crureg.h:1.8
--- src/sys/arch/arm/rockchip/rockchip_crureg.h:1.7 Sun Jan 4 11:54:05 2015
+++ src/sys/arch/arm/rockchip/rockchip_crureg.h Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_crureg.h,v 1.7 2015/01/04 11:54:05 jmcneill Exp $ */
+/* $NetBSD: rockchip_crureg.h,v 1.8 2015/01/17 15:05:24 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <[email protected]>
@@ -54,21 +54,25 @@
#define CRU_MISC_CON_REG 0x0134
#define CRU_GLB_CNT_TH_REG 0x0140
-#define CRU_PLL_CON0_CLKR_MASK __BITS(29,24)
-#define CRU_PLL_CON0_CLKOD_MASK __BITS(21,16)
-#define CRU_PLL_CON0_CLKR __BITS(13,8)
-#define CRU_PLL_CON0_CLKOD __BITS(5,0)
-
-#define CRU_PLL_CON1_CLKF_MASK __BITS(31,16)
-#define CRU_PLL_CON1_CLKF __BITS(15,0)
-
-#define CRU_PLL_CON2_BWADJ_MASK __BITS(27,16)
-#define CRU_PLL_CON2_BWADJ __BITS(11,0)
-
-#define CRU_PLL_CON3_RESET_MASK __BIT(21)
-#define CRU_PLL_CON3_POWER_DOWN_MASK __BIT(17)
-#define CRU_PLL_CON3_RESET __BIT(5)
-#define CRU_PLL_CON3_POWER_DOWN __BIT(1)
+#define CRU_PLL_CON0_CLKR_MASK __BITS(29,24)
+#define CRU_PLL_CON0_CLKOD_MASK __BITS(18,16)
+#define CRU_PLL_CON0_CLKR __BITS(13,8)
+#define CRU_PLL_CON0_CLKOD __BITS(3,0)
+#define RK3188_CRU_PLL_CON0_CLKOD_MASK __BITS(21,16)
+#define RK3188_CRU_PLL_CON0_CLKOD __BITS(5,0)
+
+#define CRU_PLL_CON1_CLKF_MASK __BITS(28,16)
+#define CRU_PLL_CON1_CLKF __BITS(12,0)
+#define RK3188_CRU_PLL_CON1_CLKF_MASK __BITS(31,16)
+#define RK3188_CRU_PLL_CON1_CLKF __BITS(15,0)
+
+#define CRU_PLL_CON2_BWADJ_MASK __BITS(27,16)
+#define CRU_PLL_CON2_BWADJ __BITS(11,0)
+
+#define CRU_PLL_CON3_RESET_MASK __BIT(21)
+#define CRU_PLL_CON3_POWER_DOWN_MASK __BIT(17)
+#define CRU_PLL_CON3_RESET __BIT(5)
+#define CRU_PLL_CON3_POWER_DOWN __BIT(1)
#define CRU_MODE_CON_APLL_WORK_MODE_MASK __BITS(17,16)
#define CRU_MODE_CON_APLL_WORK_MODE __BITS(1,0)
@@ -76,38 +80,36 @@
#define CRU_MODE_CON_APLL_WORK_MODE_NORMAL 1
#define CRU_MODE_CON_APLL_WORK_MODE_DEEP_SLOW 2
-#define RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK __BITS(29,25)
#define CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL_MASK __BIT(24)
#define CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK __BITS(23,22)
#define CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK __BITS(20,16)
-#define RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON __BITS(13,9)
#define CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL __BIT(8)
#define CRU_CLKSEL_CON0_CORE_PERI_DIV_CON __BITS(7,6)
#define CRU_CLKSEL_CON0_A9_CORE_DIV_CON __BITS(4,0)
+#define RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK __BITS(29,25)
+#define RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON __BITS(13,9)
#define CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK __BITS(31,30)
#define CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK __BITS(29,28)
#define CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK __BITS(25,24)
-#define RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK __BITS(21,19)
#define CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK __BITS(18,16)
#define CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON __BITS(15,14)
#define CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON __BITS(13,12)
#define CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON __BITS(9,8)
-#define RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON __BITS(5,3)
#define CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON __BITS(2,0)
+#define RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK __BITS(21,19)
+#define RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON __BITS(5,3)
#define CRU_CLKSEL_CON10_PERI_PLL_SEL_MASK __BIT(31)
#define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON_MASK __BITS(29,28)
-#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON_MASK __BITS(26,24)
+#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON_MASK __BITS(25,24)
#define CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON_MASK __BITS(20,16)
#define CRU_CLKSEL_CON10_PERI_PLL_SEL __BIT(15)
#define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON __BITS(13,12)
-#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON __BITS(10,8)
+#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON __BITS(9,8)
#define CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON __BITS(4,0)
-#define CRU_CLKSEL_CON11_MMC0_PLL_SEL_MASK __BIT(22)
#define CRU_CLKSEL_CON11_MMC0_DIV_CON_MASK __BITS(21,16)
-#define CRU_CLKSEL_CON11_MMC0_PLL_SEL __BIT(6)
#define CRU_CLKSEL_CON11_MMC0_DIV_CON __BITS(5,0)
#define CRU_CLKSEL_CON13_UART0_CLK_SEL_MASK __BITS(25,24)
Index: src/sys/arch/arm/rockchip/rockchip_emac.c
diff -u src/sys/arch/arm/rockchip/rockchip_emac.c:1.10 src/sys/arch/arm/rockchip/rockchip_emac.c:1.11
--- src/sys/arch/arm/rockchip/rockchip_emac.c:1.10 Tue Jan 13 10:36:15 2015
+++ src/sys/arch/arm/rockchip/rockchip_emac.c Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_emac.c,v 1.10 2015/01/13 10:36:15 jmcneill Exp $ */
+/* $NetBSD: rockchip_emac.c,v 1.11 2015/01/17 15:05:24 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_rkemac.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rockchip_emac.c,v 1.10 2015/01/13 10:36:15 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rockchip_emac.c,v 1.11 2015/01/17 15:05:24 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -182,8 +182,8 @@ rkemac_attach(device_t parent, device_t
callout_init(&sc->sc_mii_tick, 0);
callout_setfunc(&sc->sc_mii_tick, rkemac_tick, sc);
- if (rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188) ||
- rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188PLUS)) {
+ if (rockchip_chip_id() == ROCKCHIP_CHIP_ID_RK3188 ||
+ rockchip_chip_id() == ROCKCHIP_CHIP_ID_RK3188PLUS) {
soc_con1_reg = 0x00a4;
} else {
soc_con1_reg = 0x0154;
@@ -264,7 +264,7 @@ rkemac_attach(device_t parent, device_t
mii->mii_readreg = rkemac_mii_readreg;
mii->mii_writereg = rkemac_mii_writereg;
mii->mii_statchg = rkemac_mii_statchg;
- mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
+ mii_attach(sc->sc_dev, mii, 0xffffffff, 0/* XXX */, MII_OFFSET_ANY, 0);
if (LIST_EMPTY(&mii->mii_phys)) {
aprint_error_dev(sc->sc_dev, "no PHY found!\n");
Index: src/sys/arch/arm/rockchip/rockchip_reg.h
diff -u src/sys/arch/arm/rockchip/rockchip_reg.h:1.4 src/sys/arch/arm/rockchip/rockchip_reg.h:1.5
--- src/sys/arch/arm/rockchip/rockchip_reg.h:1.4 Sun Dec 28 16:03:09 2014
+++ src/sys/arch/arm/rockchip/rockchip_reg.h Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_reg.h,v 1.4 2014/12/28 16:03:09 jmcneill Exp $ */
+/* $NetBSD: rockchip_reg.h,v 1.5 2015/01/17 15:05:24 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -81,10 +81,14 @@
#define ROCKCHIP_UART2_SIZE 0x400
#define ROCKCHIP_UART3_OFFSET 0x00068000
#define ROCKCHIP_UART3_SIZE 0x400
-#define ROCKCHIP_GPIO0_OFFSET 0x0000A000
-#define ROCKCHIP_GPIO0_SIZE 0x100
+#define ROCKCHIP_GPIO6_OFFSET 0x0000A000
+#define ROCKCHIP_GPIO6_SIZE 0x100
+#define ROCKCHIP_RK3188_GPIO0_OFFSET 0x0000A000
+#define ROCKCHIP_RK3188_GPIO0_SIZE 0x100
#define ROCKCHIP_DDR_PCTL_OFFSET 0x00020000
#define ROCKCHIP_DDR_PCTL_SIZE 0x4000
+#define ROCKCHIP_GPIO0_OFFSET 0x00034000
+#define ROCKCHIP_GPIO0_SIZE 0x100
#define ROCKCHIP_GPIO1_OFFSET 0x0003C000
#define ROCKCHIP_GPIO1_SIZE 0x100
#define ROCKCHIP_GPIO2_OFFSET 0x0003E000
@@ -93,5 +97,7 @@
#define ROCKCHIP_DDR_PUBL_SIZE 0x4000
#define ROCKCHIP_GPIO3_OFFSET 0x00080000
#define ROCKCHIP_GPIO3_SIZE 0x100
+#define ROCKCHIP_GPIO4_OFFSET 0x00084000
+#define ROCKCHIP_GPIO4_SIZE 0x100
#endif /* _ARM_ROCKCHIP_ROCKCHIP_REG_H_ */
Index: src/sys/arch/arm/rockchip/rockchip_var.h
diff -u src/sys/arch/arm/rockchip/rockchip_var.h:1.11 src/sys/arch/arm/rockchip/rockchip_var.h:1.12
--- src/sys/arch/arm/rockchip/rockchip_var.h:1.11 Mon Jan 5 21:35:53 2015
+++ src/sys/arch/arm/rockchip/rockchip_var.h Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_var.h,v 1.11 2015/01/05 21:35:53 jmcneill Exp $ */
+/* $NetBSD: rockchip_var.h,v 1.12 2015/01/17 15:05:24 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -62,10 +62,11 @@ void rockchip_bootstrap(void);
void rockchip_cpufreq_init(void);
-bool rockchip_is_chip(const char *);
-#define ROCKCHIP_CHIPVER_RK3066 "300A20111111V101"
-#define ROCKCHIP_CHIPVER_RK3188 "310B20121130V100"
-#define ROCKCHIP_CHIPVER_RK3188PLUS "310B20130131V101"
+uint32_t rockchip_chip_id(void);
+#define ROCKCHIP_CHIP_ID_RK3066 0x30660000
+#define ROCKCHIP_CHIP_ID_RK3188 0x31880000
+#define ROCKCHIP_CHIP_ID_RK3188PLUS 0x31880001
+const char *rockchip_chip_name(void);
u_int rockchip_apll_get_rate(void);
u_int rockchip_cpll_get_rate(void);
Index: src/sys/arch/evbarm/conf/ROCKCHIP
diff -u src/sys/arch/evbarm/conf/ROCKCHIP:1.17 src/sys/arch/evbarm/conf/ROCKCHIP:1.18
--- src/sys/arch/evbarm/conf/ROCKCHIP:1.17 Sun Jan 11 16:53:42 2015
+++ src/sys/arch/evbarm/conf/ROCKCHIP Sat Jan 17 15:05:24 2015
@@ -1,5 +1,5 @@
#
-# $NetBSD: ROCKCHIP,v 1.17 2015/01/11 16:53:42 jmcneill Exp $
+# $NetBSD: ROCKCHIP,v 1.18 2015/01/17 15:05:24 jmcneill Exp $
#
# Rockchip RK3066/RK3188 based SBC (Single Board Computer)
#
@@ -179,6 +179,7 @@ com0 at obio0 addr 0x20064000 size 0x40
options CONSADDR=0x20064000, CONSPEED=115200
# Timer
+dwctmr2 at obio0 addr 0x2000e000 size 0x2000 crit 1
rktimer0 at obio0 addr 0x20038000 size 0x2000 crit 1
# I2C controllers
Index: src/sys/arch/evbarm/rockchip/rockchip_machdep.c
diff -u src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.19 src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.20
--- src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.19 Tue Jan 6 00:45:45 2015
+++ src/sys/arch/evbarm/rockchip/rockchip_machdep.c Sat Jan 17 15:05:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_machdep.c,v 1.19 2015/01/06 00:45:45 jmcneill Exp $ */
+/* $NetBSD: rockchip_machdep.c,v 1.20 2015/01/17 15:05:24 jmcneill Exp $ */
/*
* Machine dependent functions for kernel setup for TI OSK5912 board.
@@ -125,7 +125,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.19 2015/01/06 00:45:45 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.20 2015/01/17 15:05:24 jmcneill Exp $");
#include "opt_machdep.h"
#include "opt_ddb.h"
@@ -520,7 +520,7 @@ initarm(void *arg)
#ifdef VERBOSE_INIT_ARM
/* Talk to the user */
- printf("\nNetBSD/evbarm (rockchip) booting ...\n");
+ printf("\nNetBSD/evbarm (%s) booting ...\n", rockchip_chip_name());
#endif
#ifdef BOOT_ARGS
@@ -530,13 +530,13 @@ initarm(void *arg)
#ifdef VERBOSE_INIT_ARM
printf("initarm: Configuring system ...\n");
-#endif
#if !defined(CPU_CORTEXA8)
printf("initarm: cbar=%#x\n", armreg_cbar_read());
printf("KERNEL_BASE=0x%x, KERNEL_VM_BASE=0x%x, KERNEL_VM_BASE - KERNEL_BASE=0x%x, KERNEL_BASE_VOFFSET=0x%x\n",
KERNEL_BASE, KERNEL_VM_BASE, KERNEL_VM_BASE - KERNEL_BASE, KERNEL_BASE_VOFFSET);
#endif
+#endif
ram_size = rockchip_get_memsize();
