Module Name: src
Committed By: bouyer
Date: Tue Feb 3 08:11:22 UTC 2015
Modified Files:
src/sys/dev/ic [netbsd-7]: dwc_gmac.c dwc_gmac_reg.h dwc_gmac_var.h
Log Message:
Pull up following revision(s) (requested by snj in ticket #481):
sys/dev/ic/dwc_gmac_var.h: revision 1.6
sys/dev/ic/dwc_gmac_reg.h: revision 1.13
sys/dev/ic/dwc_gmac.c: revision 1.25
sys/dev/ic/dwc_gmac.c: revision 1.26
sys/dev/ic/dwc_gmac.c: revision 1.28
sys/dev/ic/dwc_gmac.c: revision 1.31
- Add MII flow control support
- Set "disable jabber" and "auto padding/CRC stripping" bits in MAC conf
- Write intr mask to intr mask register, not status
- Setup both TX and RX burst modes
- Setup both TX and RX store & forward modes
- Correct an issue with the "end" descriptor passed to dwc_gmac_txdesc_sync
in dwc_gmac_tx_intr
ok martin@
Revert previous change to dwc_gmac_txintr() - while it looks strange at
first sight (and sorry I didn't spot it when reviewing), it is a small
optimization and actually correct.
Add a comment explaining it.
After handling an interrupt, try to handle more packets as we may have
space in the descriptor ring now.
Pointed out by Jared.
fix a couple txq fencepost issues, from FUKAUMI Naoki <f...@naobsd.org>
To generate a diff of this commit:
cvs rdiff -u -r1.24.2.5 -r1.24.2.6 src/sys/dev/ic/dwc_gmac.c
cvs rdiff -u -r1.12.2.2 -r1.12.2.3 src/sys/dev/ic/dwc_gmac_reg.h
cvs rdiff -u -r1.5.2.2 -r1.5.2.3 src/sys/dev/ic/dwc_gmac_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/dwc_gmac.c
diff -u src/sys/dev/ic/dwc_gmac.c:1.24.2.5 src/sys/dev/ic/dwc_gmac.c:1.24.2.6
--- src/sys/dev/ic/dwc_gmac.c:1.24.2.5 Wed Jan 7 21:12:04 2015
+++ src/sys/dev/ic/dwc_gmac.c Tue Feb 3 08:11:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_gmac.c,v 1.24.2.5 2015/01/07 21:12:04 msaitoh Exp $ */
+/* $NetBSD: dwc_gmac.c,v 1.24.2.6 2015/02/03 08:11:21 bouyer Exp $ */
/*-
* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
@@ -41,7 +41,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.24.2.5 2015/01/07 21:12:04 msaitoh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.24.2.6 2015/02/03 08:11:21 bouyer Exp $");
/* #define DWC_GMAC_DEBUG 1 */
@@ -226,7 +226,8 @@ dwc_gmac_attach(struct dwc_gmac_softc *s
mii->mii_readreg = dwc_gmac_miibus_read_reg;
mii->mii_writereg = dwc_gmac_miibus_write_reg;
mii->mii_statchg = dwc_gmac_miibus_statchg;
- mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
+ mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
+ MIIF_DOPAUSE);
if (LIST_EMPTY(&mii->mii_phys)) {
aprint_error_dev(sc->sc_dev, "no PHY found!\n");
@@ -247,7 +248,7 @@ dwc_gmac_attach(struct dwc_gmac_softc *s
* Enable interrupts
*/
s = splnet();
- bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTR,
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTMASK,
AWIN_DEF_MAC_INTRMASK);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_INTENABLE,
GMAC_DEF_DMA_INT_MASK);
@@ -597,7 +598,7 @@ dwc_gmac_txdesc_sync(struct dwc_gmac_sof
/* sync from 'start' to end of ring */
bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
TX_DESC_OFFSET(start),
- TX_DESC_OFFSET(AWGE_TX_RING_COUNT+1)-TX_DESC_OFFSET(start),
+ TX_DESC_OFFSET(AWGE_TX_RING_COUNT)-TX_DESC_OFFSET(start),
ops);
/* sync from start of ring to 'end' */
bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
@@ -669,7 +670,7 @@ dwc_gmac_miibus_statchg(struct ifnet *if
{
struct dwc_gmac_softc * const sc = ifp->if_softc;
struct mii_data * const mii = &sc->sc_mii;
- uint32_t conf;
+ uint32_t conf, flow;
/*
* Set MII or GMII interface based on the speed
@@ -680,6 +681,8 @@ dwc_gmac_miibus_statchg(struct ifnet *if
|AWIN_GMAC_MAC_CONF_FULLDPLX);
conf |= AWIN_GMAC_MAC_CONF_FRAMEBURST
| AWIN_GMAC_MAC_CONF_DISABLERXOWN
+ | AWIN_GMAC_MAC_CONF_DISABLEJABBER
+ | AWIN_GMAC_MAC_CONF_ACS
| AWIN_GMAC_MAC_CONF_RXENABLE
| AWIN_GMAC_MAC_CONF_TXENABLE;
switch (IFM_SUBTYPE(mii->mii_media_active)) {
@@ -693,8 +696,20 @@ dwc_gmac_miibus_statchg(struct ifnet *if
case IFM_1000_T:
break;
}
- if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX)
+
+ flow = 0;
+ if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
conf |= AWIN_GMAC_MAC_CONF_FULLDPLX;
+ flow |= __SHIFTIN(0x200, AWIN_GMAC_MAC_FLOWCTRL_PAUSE);
+ }
+ if (mii->mii_media_active & IFM_ETH_TXPAUSE) {
+ flow |= AWIN_GMAC_MAC_FLOWCTRL_TFE;
+ }
+ if (mii->mii_media_active & IFM_ETH_RXPAUSE) {
+ flow |= AWIN_GMAC_MAC_FLOWCTRL_RFE;
+ }
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_MAC_FLOWCTRL, flow);
#ifdef DWC_GMAC_DEBUG
aprint_normal_dev(sc->sc_dev,
@@ -721,9 +736,9 @@ dwc_gmac_init(struct ifnet *ifp)
* XXX - the GMAC_BUSMODE_PRIORXTX bits are undocumented.
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
- GMAC_BUSMODE_FIXEDBURST |
- __SHIFTIN(GMAC_BUSMODE_PRIORXTX_41, GMAC_BUSMODE_PRIORXTX) |
- __SHIFTIN(8, GMCA_BUSMODE_PBL));
+ GMAC_BUSMODE_FIXEDBURST | GMAC_BUSMODE_4PBL |
+ __SHIFTIN(2, GMAC_BUSMODE_RPBL) |
+ __SHIFTIN(2, GMAC_BUSMODE_PBL));
/*
* Set up address filter
@@ -759,7 +774,7 @@ dwc_gmac_init(struct ifnet *ifp)
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
AWIN_GMAC_DMA_OPMODE, GMAC_DMA_OP_RXSTART | GMAC_DMA_OP_TXSTART |
- GMAC_DMA_OP_STOREFORWARD);
+ GMAC_DMA_OP_RXSTOREFORWARD | GMAC_DMA_OP_TXSTOREFORWARD);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
@@ -852,7 +867,7 @@ dwc_gmac_queue(struct dwc_gmac_softc *sc
return error;
}
- if (sc->sc_txq.t_queued + map->dm_nsegs >= AWGE_TX_RING_COUNT - 1) {
+ if (sc->sc_txq.t_queued + map->dm_nsegs >= AWGE_TX_RING_COUNT) {
bus_dmamap_unload(sc->sc_dmat, map);
return ENOBUFS;
}
@@ -969,6 +984,11 @@ dwc_gmac_tx_intr(struct dwc_gmac_softc *
#endif
desc = &sc->sc_txq.t_desc[i];
+ /*
+ * i+1 does not need to be a valid descriptor,
+ * this is just a special notion to just sync
+ * a single tx descriptor (i)
+ */
dwc_gmac_txdesc_sync(sc, i, i+1,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
flags = le32toh(desc->ddesc_status);
@@ -1248,6 +1268,12 @@ dwc_gmac_intr(struct dwc_gmac_softc *sc)
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
AWIN_GMAC_DMA_STATUS, dma_status & GMAC_DMA_INT_MASK);
+ /*
+ * Get more packets
+ */
+ if (rv)
+ sc->sc_ec.ec_if.if_start(&sc->sc_ec.ec_if);
+
return rv;
}
Index: src/sys/dev/ic/dwc_gmac_reg.h
diff -u src/sys/dev/ic/dwc_gmac_reg.h:1.12.2.2 src/sys/dev/ic/dwc_gmac_reg.h:1.12.2.3
--- src/sys/dev/ic/dwc_gmac_reg.h:1.12.2.2 Sun Nov 9 19:06:57 2014
+++ src/sys/dev/ic/dwc_gmac_reg.h Tue Feb 3 08:11:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_gmac_reg.h,v 1.12.2.2 2014/11/09 19:06:57 snj Exp $ */
+/* $NetBSD: dwc_gmac_reg.h,v 1.12.2.3 2015/02/03 08:11:21 bouyer Exp $ */
/*-
* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
@@ -44,6 +44,7 @@
#define AWIN_GMAC_MAC_ADDR0LO 0x0044
#define AWIN_GMAC_MII_STATUS 0x00D8
+#define AWIN_GMAC_MAC_CONF_DISABLEJABBER __BIT(22) /* jabber disable */
#define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when
in half duplex mode */
#define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */
@@ -52,6 +53,7 @@
TX frames in half duplex
mode */
#define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */
+#define AWIN_GMAC_MAC_CONF_ACS __BIT(7) /* auto pad/CRC stripping */
#define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */
#define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */
@@ -72,6 +74,11 @@
#define AWIN_GMAC_MAC_INT_LINKCHG __BIT(1)
#define AWIN_GMAC_MAC_INT_RGSMII __BIT(0)
+#define AWIN_GMAC_MAC_FLOWCTRL_PAUSE __BITS(31,16)
+#define AWIN_GMAC_MAC_FLOWCTRL_RFE __BIT(2)
+#define AWIN_GMAC_MAC_FLOWCTRL_TFE __BIT(1)
+#define AWIN_GMAC_MAC_FLOWCTRL_BUSY __BIT(0)
+
#define AWIN_GMAC_DMA_BUSMODE 0x1000
#define AWIN_GMAC_DMA_TXPOLL 0x1004
#define AWIN_GMAC_DMA_RXPOLL 0x1008
@@ -109,20 +116,24 @@
#define GMAC_MII_CLK_DIV18 0xf
#define GMAC_MII_CLKMASK __BITS(5,2)
+#define GMAC_BUSMODE_4PBL __BIT(24)
+#define GMAC_BUSMODE_RPBL __BITS(22,17)
#define GMAC_BUSMODE_FIXEDBURST __BIT(16)
#define GMAC_BUSMODE_PRIORXTX __BITS(15,14)
#define GMAC_BUSMODE_PRIORXTX_41 3
#define GMAC_BUSMODE_PRIORXTX_31 2
#define GMAC_BUSMODE_PRIORXTX_21 1
#define GMAC_BUSMODE_PRIORXTX_11 0
-#define GMCA_BUSMODE_PBL __BITS(13,8) /* possible DMA
+#define GMAC_BUSMODE_PBL __BITS(13,8) /* possible DMA
burst len */
#define GMAC_BUSMODE_RESET __BIT(0)
#define AWIN_GMAC_MII_IRQ __BIT(0)
-#define GMAC_DMA_OP_STOREFORWARD __BIT(21) /* start TX when a
+#define GMAC_DMA_OP_RXSTOREFORWARD __BIT(24) /* start RX when a
+ full frame is available */
+#define GMAC_DMA_OP_TXSTOREFORWARD __BIT(21) /* start TX when a
full frame is available */
#define GMAC_DMA_OP_FLUSHTX __BIT(20) /* flush TX fifo */
#define GMAC_DMA_OP_TXSTART __BIT(13) /* start TX DMA engine */
Index: src/sys/dev/ic/dwc_gmac_var.h
diff -u src/sys/dev/ic/dwc_gmac_var.h:1.5.2.2 src/sys/dev/ic/dwc_gmac_var.h:1.5.2.3
--- src/sys/dev/ic/dwc_gmac_var.h:1.5.2.2 Sun Nov 9 19:06:57 2014
+++ src/sys/dev/ic/dwc_gmac_var.h Tue Feb 3 08:11:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_gmac_var.h,v 1.5.2.2 2014/11/09 19:06:57 snj Exp $ */
+/* $NetBSD: dwc_gmac_var.h,v 1.5.2.3 2015/02/03 08:11:21 bouyer Exp $ */
/*-
* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
@@ -44,7 +44,7 @@
#define AWGE_TOTAL_RING_COUNT \
(AWGE_RX_RING_COUNT + AWGE_TX_RING_COUNT)
-#define AWGE_MAX_PACKET (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
+#define AWGE_MAX_PACKET 0x7ff
