Module Name: src
Committed By: jmcneill
Date: Sat Feb 7 17:14:32 UTC 2015
Modified Files:
src/sys/arch/arm/conf: files.arm
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.
To generate a diff of this commit:
cvs rdiff -u -r1.129 -r1.130 src/sys/arch/arm/conf/files.arm
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/a9_mpsubr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/conf/files.arm
diff -u src/sys/arch/arm/conf/files.arm:1.129 src/sys/arch/arm/conf/files.arm:1.130
--- src/sys/arch/arm/conf/files.arm:1.129 Mon Dec 1 08:39:43 2014
+++ src/sys/arch/arm/conf/files.arm Sat Feb 7 17:14:32 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.arm,v 1.129 2014/12/01 08:39:43 matt Exp $
+# $NetBSD: files.arm,v 1.130 2015/02/07 17:14:32 jmcneill Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@@ -68,6 +68,8 @@ defflag opt_cpuoptions.h ARM_HAS_LPAE
# use extended small page in compatible MMU mode for ARMv6
defflag opt_cpuoptions.h SHEEVA_L2_CACHE
defflag opt_cpuoptions.h SHEEVA_L2_CACHE_WT: SHEEVA_L2_CACHE
+# override configuration base address register
+defparam opt_cpuoptions.h ARM_CBAR
# Interrupt implementation header definition.
defparam opt_arm_intr_impl.h ARM_INTR_IMPL
Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.27 src/sys/arch/arm/cortex/a9_mpsubr.S:1.28
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.27 Sat Feb 7 02:39:56 2015
+++ src/sys/arch/arm/cortex/a9_mpsubr.S Sat Feb 7 17:14:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: a9_mpsubr.S,v 1.27 2015/02/07 02:39:56 jmcneill Exp $ */
+/* $NetBSD: a9_mpsubr.S,v 1.28 2015/02/07 17:14:32 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -365,7 +365,12 @@ cortex_init:
// Step 1a, invalidate the all cache tags in all ways on the SCU.
//
XPUTC(#65)
+#if defined(ARM_CBAR)
+ movw r3, #:lower16:ARM_CBAR
+ movt r3, #:upper16:ARM_CBAR
+#else
mrc p15, 4, r3, c15, c0, 0 // read cbar
+#endif
#ifdef __ARMEB__
setend le
#endif
@@ -419,7 +424,12 @@ cortex_init:
//
// Step 3, enable the SCU
//
+#if defined(ARM_CBAR)
+ movw r3, #:lower16:ARM_CBAR
+ movt r3, #:upper16:ARM_CBAR
+#else
mrc p15, 4, r3, c15, c0, 0 // read cbar
+#endif
#ifdef __ARMEB__
setend le
#endif
