Module Name: src
Committed By: macallan
Date: Mon Mar 9 13:22:37 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
moar registers
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.7 src/sys/arch/mips/ingenic/ingenic_regs.h:1.8
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.7 Sat Mar 7 15:36:16 2015
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Mon Mar 9 13:22:37 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.7 2015/03/07 15:36:16 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.8 2015/03/09 13:22:37 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -221,7 +221,7 @@ MFC0(uint32_t r, uint32_t s)
#define PCR_TXPREEMPH 0x00000080 /* HS transm. pre-emphasis */
#define PCR_TXHSXVTUNE1 0x00000060 /* dp/dm voltage adj. */
#define PCR_TXVREFTUNE1 0x00000017 /* HS DC voltage adj. */
- #define PCR_TXRISETUNE1 0x00000001 /* risa/fall wave adj. */
+ #define PCR_TXRISETUNE1 0x00000001 /* rise/fall wave adj. */
#define JZ_UHCCDR 0x1000006c /* UHC Clock Divider Register */
#define JZ_SPCR0 0x100000b8 /* SRAM Power Control Registers */
@@ -255,5 +255,14 @@ MFC0(uint32_t r, uint32_t s)
#define DMMAP_BASE 0x0000ff00 /* base PADDR of memory chunk */
#define DMMAP_MASK 0x000000ff /* mask which bits of PADDR are
* constant */
+/* USB controllers */
+#define JZ_EHCI_BASE 0x13490000
+#define JZ_OHCI_BASE 0x134a0000
+#define JZ_DWC2_BASE 0x13500000
+
+/* Ethernet */
+#define JZ_DME_BASE 0x16000000
+#define JZ_DME_IO JZ_DME_BASE
+#define JZ_DME_ADDR (JZ_DME_BASE + 2)
#endif /* INGENIC_REGS_H */
