Module Name: src
Committed By: matt
Date: Tue Mar 31 17:57:40 UTC 2015
Modified Files:
src/external/gpl3/gcc/dist/gcc: configure configure.ac
Log Message:
Update RISCV tls assembly tests
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/external/gpl3/gcc/dist/gcc/configure
cvs rdiff -u -r1.9 -r1.10 src/external/gpl3/gcc/dist/gcc/configure.ac
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/external/gpl3/gcc/dist/gcc/configure
diff -u src/external/gpl3/gcc/dist/gcc/configure:1.11 src/external/gpl3/gcc/dist/gcc/configure:1.12
--- src/external/gpl3/gcc/dist/gcc/configure:1.11 Sat Jan 10 01:06:41 2015
+++ src/external/gpl3/gcc/dist/gcc/configure Tue Mar 31 17:57:40 2015
@@ -23368,13 +23368,13 @@ x:
.text
la.tls.gd a0,x
la.tls.ie a1,x
- lui v0,%tls_ie_hi(x)
- lw v0,%tls_ie_lo(x)(v0)
- add v0,v0,tp,%tls_ie_add(x)
- lw v0,%tls_ie_off(x)(v0)
- lui v0,%tprel_hi(x)
- add v0,v0,tp,%tprel_add(x)
- lw v0,%tprel_lo(x)(v0)'
+ lui a0,%tls_ie_pcrel_hi(x)
+ lw a0,%pcrel_lo(x)(a0)
+ add a0,a0,tp
+ lw a0,(a0)
+ lui a0,%tprel_hi(x)
+ add a0,a0,tp,%tprel_add(x)
+ lw a0,%tprel_lo(x)(a0)'
tls_first_major=2
tls_first_minor=21
tls_as_opt='-m32 --fatal-warnings'
Index: src/external/gpl3/gcc/dist/gcc/configure.ac
diff -u src/external/gpl3/gcc/dist/gcc/configure.ac:1.9 src/external/gpl3/gcc/dist/gcc/configure.ac:1.10
--- src/external/gpl3/gcc/dist/gcc/configure.ac:1.9 Sat Jan 10 01:06:41 2015
+++ src/external/gpl3/gcc/dist/gcc/configure.ac Tue Mar 31 17:57:40 2015
@@ -3116,13 +3116,13 @@ x:
.text
la.tls.gd a0,x
la.tls.ie a1,x
- lui v0,%tls_ie_hi(x)
- lw v0,%tls_ie_lo(x)(v0)
- add v0,v0,tp,%tls_ie_add(x)
- lw v0,%tls_ie_off(x)(v0)
- lui v0,%tprel_hi(x)
- add v0,v0,tp,%tprel_add(x)
- lw v0,%tprel_lo(x)(v0)'
+ lui a0,%tls_ie_pcrel_hi(x)
+ lw a0,%pcrel_lo(x)(a0)
+ add a0,a0,tp
+ lw a0,0(a0)
+ lui a0,%tprel_hi(x)
+ add a0,a0,tp,%tprel_add(x)
+ lw a0,%tprel_lo(x)(a0)'
tls_first_major=2
tls_first_minor=21
tls_as_opt='-m32 --fatal-warnings'
