Module Name: src
Committed By: msaitoh
Date: Fri Apr 17 08:44:54 UTC 2015
Modified Files:
src/sys/arch/arm/omap [netbsd-7]: if_cpsw.c if_cpswreg.h
Log Message:
Pull up following revision(s) (requested by jmcneill in ticket #696):
sys/arch/arm/omap/if_cpsw.c: revision 1.12
sys/arch/arm/omap/if_cpswreg.h: revision 1.5
Disable flow control with CPSW_SS FLOW_CONTROL register (cherry-picked
from FreeBSD driver). Resolves device timeout / watchdog issues for me.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.6.2.1 src/sys/arch/arm/omap/if_cpsw.c
cvs rdiff -u -r1.2 -r1.2.4.1 src/sys/arch/arm/omap/if_cpswreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/if_cpsw.c
diff -u src/sys/arch/arm/omap/if_cpsw.c:1.6 src/sys/arch/arm/omap/if_cpsw.c:1.6.2.1
--- src/sys/arch/arm/omap/if_cpsw.c:1.6 Wed Apr 9 20:52:14 2014
+++ src/sys/arch/arm/omap/if_cpsw.c Fri Apr 17 08:44:54 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: if_cpsw.c,v 1.6 2014/04/09 20:52:14 hans Exp $ */
+/* $NetBSD: if_cpsw.c,v 1.6.2.1 2015/04/17 08:44:54 msaitoh Exp $ */
/*
* Copyright (c) 2013 Jonathan A. Kollasch
@@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.6 2014/04/09 20:52:14 hans Exp $");
+__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.6.2.1 2015/04/17 08:44:54 msaitoh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -891,6 +891,9 @@ cpsw_init(struct ifnet *ifp)
}
sc->sc_rxhead = 0;
+ /* turn off flow control */
+ cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
+
/* align layer 3 header to 32-bit */
cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN);
Index: src/sys/arch/arm/omap/if_cpswreg.h
diff -u src/sys/arch/arm/omap/if_cpswreg.h:1.2 src/sys/arch/arm/omap/if_cpswreg.h:1.2.4.1
--- src/sys/arch/arm/omap/if_cpswreg.h:1.2 Wed Feb 26 03:58:33 2014
+++ src/sys/arch/arm/omap/if_cpswreg.h Fri Apr 17 08:44:54 2015
@@ -34,6 +34,7 @@
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
+#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
#define CPSW_SS_RGMII_CTL (CPSW_SS_OFFSET + 0x88)
#define CPSW_PORT_OFFSET 0x0100
