Module Name: src
Committed By: matt
Date: Thu Jun 4 02:27:25 UTC 2015
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Use ei/di on mipsNNr2 where possible.
To generate a diff of this commit:
cvs rdiff -u -r1.57 -r1.58 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.57 src/sys/arch/mips/mips/mipsX_subr.S:1.58
--- src/sys/arch/mips/mips/mipsX_subr.S:1.57 Tue May 26 02:18:20 2015
+++ src/sys/arch/mips/mips/mipsX_subr.S Thu Jun 4 02:27:25 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.57 2015/05/26 02:18:20 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.58 2015/06/04 02:27:25 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -997,9 +997,13 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
* Interrupts handled, restore registers and return from the interrupt.
* First, clear interrupt enable
*/
+#if __mips_isa_rev >= 2
+ di v0 # disable interrupts
+#else
mfc0 v0, MIPS_COP_0_STATUS # read it
xor v0, MIPS_SR_INT_IE # disable interrupts
mtc0 v0, MIPS_COP_0_STATUS # write it
+#endif
COP0_SYNC
or v0, MIPS_SR_EXL # set exception mode
@@ -1348,10 +1352,14 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
/*
* Disable interrupts
*/
+#if __mips_isa_rev >= 2
+ di # disable interrupts
+#else
mfc0 v1, MIPS_COP_0_STATUS
and v0, v1, MIPS_SR_INT_IE # clear interrupt enable
xor v0, v1
mtc0 v0, MIPS_COP_0_STATUS # interrupts are disabled
+#endif
COP0_SYNC
/*
@@ -1382,10 +1390,14 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
REG_S s6, CALLFRAME_SIZ+TF_REG_S6(sp) # $22
REG_S s7, CALLFRAME_SIZ+TF_REG_S7(sp) # $23
REG_S s8, CALLFRAME_SIZ+TF_REG_S8(sp) # $30
+#if !defined(MIPS_DYNAMIC_STATUS_MASK) && __mips_isa_rev > 2
+ ei # enable interrupts
+#else
mfc0 t0, MIPS_COP_0_STATUS #
or t0, MIPS_SR_INT_IE # enable interrupts
DYNAMIC_STATUS_MASK(t0, t1) # machine dependent masking
mtc0 t0, MIPS_COP_0_STATUS # enable interrupts (spl0)
+#endif
COP0_SYNC
PTR_LA ra, MIPSX(user_return)
@@ -2181,6 +2193,9 @@ LEAF_NOPROFILE(MIPSX(tlb_record_asids))
li ta3, 1
move v0, zero # start at zero ASIDs
+#if __mips_isa_rev >= 2
+ di v1 # disable interrupts
+#else
mfc0 v1, MIPS_COP_0_STATUS # save status register
#ifdef _LP64
and t0, v1, MIPS_SR_INT_IE
@@ -2189,6 +2204,7 @@ LEAF_NOPROFILE(MIPSX(tlb_record_asids))
#else
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
#endif
+#endif
COP0_SYNC
# do {} while (ta0 < ta1)
