Module Name: src
Committed By: matt
Date: Sat Jun 6 04:31:10 UTC 2015
Modified Files:
src/sys/arch/mips/include: trap.h
Log Message:
Add missing but now defined trap types. (use define<tab> consistently)
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/trap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/trap.h
diff -u src/sys/arch/mips/include/trap.h:1.18 src/sys/arch/mips/include/trap.h:1.19
--- src/sys/arch/mips/include/trap.h:1.18 Tue Aug 16 06:58:15 2011
+++ src/sys/arch/mips/include/trap.h Sat Jun 6 04:31:10 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.h,v 1.18 2011/08/16 06:58:15 matt Exp $ */
+/* $NetBSD: trap.h,v 1.19 2015/06/06 04:31:10 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -43,21 +43,21 @@
* also known in trap.c for name strings
*/
#ifndef _MIPS_TRAP_H_
-#define _MIPS_TRAP_H_
+#define _MIPS_TRAP_H_
-#define T_INT 0 /* Interrupt pending */
-#define T_TLB_MOD 1 /* TLB modified fault */
-#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
-#define T_TLB_ST_MISS 3 /* TLB miss on a store */
-#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
-#define T_ADDR_ERR_ST 5 /* Address error on a store */
-#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
-#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
-#define T_SYSCALL 8 /* System call */
-#define T_BREAK 9 /* Breakpoint */
-#define T_RES_INST 10 /* Reserved instruction exception */
-#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
-#define T_OVFLOW 12 /* Arithmetic overflow */
+#define T_INT 0 /* Interrupt pending */
+#define T_TLB_MOD 1 /* TLB modified fault */
+#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
+#define T_TLB_ST_MISS 3 /* TLB miss on a store */
+#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
+#define T_ADDR_ERR_ST 5 /* Address error on a store */
+#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
+#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
+#define T_SYSCALL 8 /* System call */
+#define T_BREAK 9 /* Breakpoint */
+#define T_RES_INST 10 /* Reserved instruction exception */
+#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
+#define T_OVFLOW 12 /* Arithmetic overflow */
/*
* Trap definitions added for r4000 port.
@@ -65,9 +65,16 @@
#define T_TRAP 13 /* Trap instruction */
#define T_VCEI 14 /* Virtual coherency exception */
#define T_FPE 15 /* Floating point exception */
+#define T_NMI 16 /* Reserved so put NMI here */
+#define T_TLBRI 19 /* TLB Read-Inhibit */
+#define T_TLBXI 20 /* TLB Execute-Inhibit */
+#define T_MDMX 22 /* MDMX Unusable exception */
#define T_WATCH 23 /* Watch address reference */
+#define T_MCHECK 24 /* Machine Check exception */
+#define T_THREAD 25 /* Thread exception */
#define T_DSP 26 /* DSP exception */
-#define T_VCED 31 /* Virtual coherency data */
+#define T_CACHE 30 /* Cache Error */
+#define T_VCED 31 /* Virtual coherency data */
#define T_USER 0x20 /* user-mode flag or'ed with type */
