Module Name: src
Committed By: matt
Date: Sat Jun 6 20:52:16 UTC 2015
Modified Files:
src/sys/arch/mips/cavium: octeon_cpunode.c octeon_intr.c octeonvar.h
Log Message:
Add wdog support
cleanup IPI and MP support
Add NMI support.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/cavium/octeon_cpunode.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/cavium/octeon_intr.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/cavium/octeonvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/octeon_cpunode.c
diff -u src/sys/arch/mips/cavium/octeon_cpunode.c:1.1 src/sys/arch/mips/cavium/octeon_cpunode.c:1.2
--- src/sys/arch/mips/cavium/octeon_cpunode.c:1.1 Mon Jun 1 22:55:12 2015
+++ src/sys/arch/mips/cavium/octeon_cpunode.c Sat Jun 6 20:52:16 2015
@@ -32,15 +32,24 @@
__KERNEL_RCSID(0, "$NetBSD");
#include "locators.h"
+#include "cpunode.h"
+#include "opt_multiprocessor.h"
+#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/device.h>
#include <sys/lwp.h>
#include <sys/cpu.h>
+#include <sys/wdog.h>
+
+#include <uvm/uvm.h>
+
+#include <dev/sysmon/sysmonvar.h>
#include <mips/cache.h>
#include <mips/cpuset.h>
#include <mips/mips_opcode.h>
+#include <mips/mips3_clock.h>
#include <mips/cavium/octeonvar.h>
#include <mips/cavium/dev/octeon_ciureg.h>
@@ -51,26 +60,35 @@ struct cpunode_attach_args {
int cnaa_cpunum;
};
+struct cpunode_softc {
+ device_t sc_dev;
+ device_t sc_wdog_dev;
+ uint64_t sc_fuse;
+};
+
static int cpunode_mainbus_match(device_t, cfdata_t, void *);
static void cpunode_mainbus_attach(device_t, device_t, void *);
static int cpu_cpunode_match(device_t, cfdata_t, void *);
static void cpu_cpunode_attach(device_t, device_t, void *);
-CFATTACH_DECL_NEW(cpunode, 0,
+CFATTACH_DECL_NEW(cpunode, sizeof(struct cpunode_softc),
cpunode_mainbus_match, cpunode_mainbus_attach, NULL, NULL);
-CFATTACH_DECL_NEW(cpunode_cpu, 0,
+CFATTACH_DECL_NEW(cpu_cpunode, 0,
cpu_cpunode_match, cpu_cpunode_attach, NULL, NULL);
volatile __cpuset_t cpus_booted = 1;
+void octeon_reset_vector(void);
+
static int
cpunode_mainbus_print(void *aux, const char *pnp)
{
struct cpunode_attach_args * const cnaa = aux;
- aprint_normal(" core %d", cnaa->cnaa_cpunum);
+ if (cnaa->cnaa_cpunum != CPUNODECF_CORE_DEFAULT)
+ aprint_normal(" core %d", cnaa->cnaa_cpunum);
return UNCONF;
}
@@ -85,31 +103,44 @@ cpunode_mainbus_match(device_t parent, c
void
cpunode_mainbus_attach(device_t parent, device_t self, void *aux)
{
- uint64_t fuse = octeon_xkphys_read_8(CIU_FUSE);
+ struct cpunode_softc * const sc = device_private(self);
int cpunum = 0;
+ sc->sc_dev = self;
+ sc->sc_fuse = octeon_xkphys_read_8(CIU_FUSE);
+
aprint_naive(": %u core%s\n",
- popcount32((uint32_t)fuse),
- fuse == 1 ? "" : "s");
+ popcount32((uint32_t)sc->sc_fuse),
+ sc->sc_fuse == 1 ? "" : "s");
aprint_normal(": %u core%s",
- popcount32((uint32_t)fuse),
- fuse == 1 ? "" : "s");
+ popcount32((uint32_t)sc->sc_fuse),
+ sc->sc_fuse == 1 ? "" : "s");
const uint64_t cvmctl = mips_cp0_cvmctl_read();
aprint_normal(", %scrypto", (cvmctl & CP0_CVMCTL_NOCRYPTO) ? "no " : "");
aprint_normal((cvmctl & CP0_CVMCTL_KASUMI) ? "+kasumi" : "");
aprint_normal(", %s64bit-mul", (cvmctl & CP0_CVMCTL_NOMUL) ? "no " : "");
if (cvmctl & CP0_CVMCTL_REPUN)
aprint_normal(", unaligned-access ok");
+#ifdef MULTIPROCESSOR
+ aprint_normal(", booted %#" PRIx64, cpus_booted);
+#endif
aprint_normal("\n");
- for (; fuse != 0; fuse >>= 1, cpunum++) {
+ for (uint64_t fuse = sc->sc_fuse; fuse != 0; fuse >>= 1, cpunum++) {
struct cpunode_attach_args cnaa = {
.cnaa_name = "cpu",
.cnaa_cpunum = cpunum,
};
config_found(self, &cnaa, cpunode_mainbus_print);
}
+#if NWDOG > 0
+ struct cpunode_attach_args cnaa = {
+ .cnaa_name = "wdog",
+ .cnaa_cpunum = CPUNODECF_CORE_DEFAULT,
+ };
+ config_found(self, &cnaa, cpunode_mainbus_print);
+#endif
}
int
@@ -118,8 +149,8 @@ cpu_cpunode_match(device_t parent, cfdat
struct cpunode_attach_args * const cnaa = aux;
const int cpunum = cf->cf_loc[CPUNODECF_CORE];
- return cpunum == CPUNODECF_CORE_DEFAULT
- || cpunum == cnaa->cnaa_cpunum;
+ return strcmp(cnaa->cnaa_name, cf->cf_name) == 0
+ && (cpunum == CPUNODECF_CORE_DEFAULT || cpunum == cnaa->cnaa_cpunum);
}
#if defined(MULTIPROCESSOR)
@@ -129,8 +160,9 @@ octeon_fixup_cpu_info_references(int32_t
{
struct cpu_info * const ci = arg;
+ atomic_or_64(&curcpu()->ci_flags, CPUF_PRESENT);
+
KASSERT(MIPS_KSEG0_P(load_addr));
- KASSERT(!MIPS_CACHE_VIRTUAL_ALIAS);
#ifdef MULTIPROCESSOR
KASSERT(!CPU_IS_PRIMARY(curcpu()));
#endif
@@ -178,34 +210,68 @@ octeon_cpu_init(struct cpu_info *ci)
ok = mips_fixup_exceptions(octeon_fixup_cpu_info_references, ci);
KASSERT(ok);
- (void) splhigh();
+ (void) splhigh(); // make sure interrupts are masked
-#ifdef DEBUG
KASSERT((mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM) == ci->ci_cpuid);
KASSERT(curcpu() == ci);
-#endif
+ KASSERT(ci->ci_cpl == IPL_HIGH);
+ KASSERT((mips_cp0_status_read() & MIPS_INT_MASK) == 0);
}
static void
octeon_cpu_run(struct cpu_info *ci)
{
+ octeon_intr_init(ci);
+
+ mips3_initclocks();
+ KASSERTMSG(ci->ci_cpl == IPL_NONE, "cpl %d", ci->ci_cpl);
+ KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
+
+ aprint_normal("%s: ", device_xname(ci->ci_dev));
+ cpu_identify(ci->ci_dev);
}
#endif /* MULTIPROCESSOR */
static void
cpu_cpunode_attach_common(device_t self, struct cpu_info *ci)
{
+ struct cpu_softc * const cpu __diagused = ci->ci_softc;
+
ci->ci_dev = self;
self->dv_private = ci;
+ KASSERTMSG(cpu != NULL, "ci %p index %d", ci, cpu_index(ci));
+
+#if NWDOG > 0 || defined(DDB)
+ void **nmi_vector = (void *)MIPS_PHYS_TO_KSEG0(0x800 + 32*ci->ci_cpuid);
+ *nmi_vector = octeon_reset_vector;
+
+ struct vm_page * const pg = mips_pmap_alloc_poolpage(UVM_PGA_ZERO);
+ KASSERT(pg != NULL);
+ const vaddr_t kva = mips_pmap_map_poolpage(VM_PAGE_TO_PHYS(pg));
+ KASSERT(kva != 0);
+ ci->ci_xnext = (void *)(kva + PAGE_SIZE - sizeof(struct kernframe));
+#endif
+
+#ifdef WDOG
+ cpu->cpu_wdog_sih = softint_establish(SOFTINT_CLOCK|SOFTINT_MPSAFE,
+ wdog_cpunode_poke, cpu);
+ KASSERT(cpu->cpu_wdog_sih != NULL);
+#endif
+
aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n",
ci->ci_cpu_freq / 1000000,
(ci->ci_cpu_freq % 1000000) / 10000,
ci->ci_cycles_per_hz, ci->ci_divisor_delay);
- aprint_normal("%s: ", device_xname(self));
- cpu_identify(self);
+ if (CPU_IS_PRIMARY(ci)) {
+ aprint_normal("%s: ", device_xname(self));
+ cpu_identify(self);
+ }
cpu_attach_common(self, ci);
+#ifdef MULTIPROCESSOR
+ KASSERT(cpuid_infos[ci->ci_cpuid] == ci);
+#endif
}
void
@@ -235,8 +301,169 @@ cpu_cpunode_attach(device_t parent, devi
ci->ci_softc->cpu_ci = ci;
cpu_cpunode_attach_common(self, ci);
+
+ KASSERT(ci->ci_data.cpu_idlelwp != NULL);
+ for (int i = 0; i < 100 && !CPUSET_HAS_P(cpus_hatched, cpunum); i++) {
+ delay(10000);
+ }
+ if (!CPUSET_HAS_P(cpus_hatched, cpunum)) {
+#ifdef DDB
+ aprint_verbose_dev(self, "hatch failed ci=%p flags=%#"PRIx64"\n", ci, ci->ci_flags);
+ cpu_Debugger();
+#endif
+ panic("%s failed to hatch: ci=%p flags=%#"PRIx64,
+ cpu_name(ci), ci, ci->ci_flags);
+ }
#else
aprint_naive(": disabled\n");
aprint_normal(": disabled (uniprocessor kernel)\n");
#endif
}
+
+#if NWDOG > 0
+struct wdog_softc {
+ struct sysmon_wdog sc_smw;
+ device_t sc_dev;
+ u_int sc_wdog_period;
+ bool sc_wdog_armed;
+};
+
+#ifndef OCTEON_WDOG_PERIOD_DEFAULT
+#define OCTEON_WDOG_PERIOD_DEFAULT 4
+#endif
+
+static int wdog_cpunode_match(device_t, cfdata_t, void *);
+static void wdog_cpunode_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(wdog_cpunode, sizeof(struct wdog_softc),
+ wdog_cpunode_match, wdog_cpunode_attach, NULL, NULL);
+
+static int
+wdog_cpunode_setmode(struct sysmon_wdog *smw)
+{
+ struct wdog_softc * const sc = smw->smw_cookie;
+
+ if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
+ if (sc->sc_wdog_armed) {
+ CPU_INFO_ITERATOR cii;
+ struct cpu_info *ci;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ struct cpu_softc * const cpu = ci->ci_softc;
+ uint64_t wdog = mips64_ld_a64(cpu->cpu_wdog);
+ wdog &= ~CIU_WDOGX_MODE;
+ mips64_sd_a64(cpu->cpu_pp_poke, wdog);
+ aprint_verbose_dev(sc->sc_dev,
+ "%s: disable wdog=%#"PRIx64"\n",
+ cpu_name(ci), wdog);
+ mips64_sd_a64(cpu->cpu_wdog, wdog);
+ mips64_sd_a64(cpu->cpu_pp_poke, wdog);
+ }
+ sc->sc_wdog_armed = false;
+ }
+ } else if (!sc->sc_wdog_armed) {
+ kpreempt_disable();
+ struct cpu_info *ci = curcpu();
+ if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
+ smw->smw_period = OCTEON_WDOG_PERIOD_DEFAULT;
+ }
+ uint64_t wdog_len = smw->smw_period * ci->ci_cpu_freq;
+ //
+ // This wdog is a 24-bit counter that decrements every 256
+ // cycles. This is then a 32-bit counter so as long wdog_len
+ // doesn't overflow a 32-bit value, we are fine. We write the
+ // 16-bits of the 32-bit period.
+ if ((wdog_len >> 32) != 0) {
+ return EINVAL;
+ }
+ sc->sc_wdog_period = smw->smw_period;
+ CPU_INFO_ITERATOR cii;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ struct cpu_softc * const cpu = ci->ci_softc;
+ uint64_t wdog = mips64_ld_a64(cpu->cpu_wdog);
+ wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN);
+ wdog |= __SHIFTIN(3, CIU_WDOGX_MODE);
+ wdog |= __SHIFTIN(wdog_len >> 16, CIU_WDOGX_LEN);
+ aprint_verbose_dev(sc->sc_dev,
+ "%s: enable wdog=%#"PRIx64" (%#"PRIx64")\n",
+ cpu_name(ci), wdog, wdog_len);
+ mips64_sd_a64(cpu->cpu_wdog, wdog);
+ }
+ sc->sc_wdog_armed = true;
+ kpreempt_enable();
+ }
+ return 0;
+}
+
+static void
+wdog_cpunode_poke(void *arg)
+{
+ struct cpu_softc *cpu = arg;
+ mips64_sd_a64(cpu->cpu_pp_poke, 0);
+}
+
+static int
+wdog_cpunode_tickle(struct sysmon_wdog *smw)
+{
+ wdog_cpunode_poke(curcpu()->ci_softc);
+#ifdef MULTIPROCESSOR
+ // We need to send IPIs to the other CPUs to poke their wdog.
+ cpu_send_ipi(NULL, IPI_WDOG);
+#endif
+ return 0;
+}
+
+int
+wdog_cpunode_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct cpunode_softc * const sc = device_private(parent);
+ struct cpunode_attach_args * const cnaa = aux;
+ const int cpunum = cf->cf_loc[CPUNODECF_CORE];
+
+ return sc->sc_wdog_dev == NULL
+ && strcmp(cnaa->cnaa_name, cf->cf_name) == 0
+ && cpunum == CPUNODECF_CORE_DEFAULT;
+}
+
+void
+wdog_cpunode_attach(device_t parent, device_t self, void *aux)
+{
+ struct cpunode_softc * const psc = device_private(parent);
+ struct wdog_softc * const sc = device_private(self);
+ cfdata_t const cf = device_cfdata(self);
+
+ psc->sc_wdog_dev = self;
+
+ sc->sc_dev = self;
+ sc->sc_smw.smw_name = device_xname(self);
+ sc->sc_smw.smw_cookie = sc;
+ sc->sc_smw.smw_setmode = wdog_cpunode_setmode;
+ sc->sc_smw.smw_tickle = wdog_cpunode_tickle;
+ sc->sc_smw.smw_period = OCTEON_WDOG_PERIOD_DEFAULT;
+ sc->sc_wdog_period = sc->sc_smw.smw_period;
+
+ /*
+ * We need one softint per cpu. It's to tickle the softints on
+ * other CPUs.
+ */
+ CPU_INFO_ITERATOR cii;
+ struct cpu_info *ci;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ }
+
+ aprint_normal(": default period is %u seconds%s\n",
+ sc->sc_wdog_period, sc->sc_wdog_period == 1 ? "" : "s");
+
+ if (sysmon_wdog_register(&sc->sc_smw) != 0) {
+ aprint_error_dev(self, "unable to register with sysmon\n");
+ return;
+ }
+
+ if (cf->cf_flags & 1) {
+ int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE,
+ sc->sc_wdog_period);
+ if (error)
+ aprint_error_dev(self,
+ "failed to start kernel tickler: %d\n", error);
+ }
+}
+#endif /* NWDOG > 0 */
Index: src/sys/arch/mips/cavium/octeon_intr.c
diff -u src/sys/arch/mips/cavium/octeon_intr.c:1.3 src/sys/arch/mips/cavium/octeon_intr.c:1.4
--- src/sys/arch/mips/cavium/octeon_intr.c:1.3 Mon Jun 1 22:55:12 2015
+++ src/sys/arch/mips/cavium/octeon_intr.c Sat Jun 6 20:52:16 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_intr.c,v 1.3 2015/06/01 22:55:12 matt Exp $ */
+/* $NetBSD: octeon_intr.c,v 1.4 2015/06/06 20:52:16 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
@@ -39,10 +39,11 @@
*/
#include "opt_octeon.h"
+#include "cpunode.h"
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.3 2015/06/01 22:55:12 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.4 2015/06/06 20:52:16 matt Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -199,6 +200,9 @@ struct cpu_softc octeon_cpu0_softc = {
.cpu_int32_en = X(CIU_INT32_EN0),
+ .cpu_wdog = X(CIU_WDOG0),
+ .cpu_pp_poke = X(CIU_PP_POKE0),
+
#ifdef MULTIPROCESSOR
.cpu_mbox_set = X(CIU_MBOX_SET0),
.cpu_mbox_clr = X(CIU_MBOX_CLR0),
@@ -221,11 +225,76 @@ struct cpu_softc octeon_cpu1_softc = {
.cpu_int32_en = X(CIU_INT32_EN1),
+ .cpu_wdog = X(CIU_WDOG1),
+ .cpu_pp_poke = X(CIU_PP_POKE1),
+
.cpu_mbox_set = X(CIU_MBOX_SET1),
.cpu_mbox_clr = X(CIU_MBOX_CLR1),
};
#endif
+#ifdef DEBUG
+static void
+octeon_mbox_test(void)
+{
+ const uint64_t mbox_clr0 = X(CIU_MBOX_CLR0);
+ const uint64_t mbox_clr1 = X(CIU_MBOX_CLR1);
+ const uint64_t mbox_set0 = X(CIU_MBOX_SET0);
+ const uint64_t mbox_set1 = X(CIU_MBOX_SET1);
+ const uint64_t int_sum0 = X(CIU_INT0_SUM0);
+ const uint64_t int_sum1 = X(CIU_INT2_SUM0);
+ const uint64_t sum_mbox_lo = __BIT(_CIU_INT_MBOX_15_0_SHIFT);
+ const uint64_t sum_mbox_hi = __BIT(_CIU_INT_MBOX_31_16_SHIFT);
+
+ mips64_sd_a64(mbox_clr0, ~0ULL);
+ mips64_sd_a64(mbox_clr1, ~0ULL);
+
+ uint32_t mbox0 = mips64_ld_a64(mbox_set0);
+ uint32_t mbox1 = mips64_ld_a64(mbox_set1);
+
+ KDASSERTMSG(mbox0 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
+ KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
+
+ mips64_sd_a64(mbox_set0, __BIT(0));
+
+ mbox0 = mips64_ld_a64(mbox_set0);
+ mbox1 = mips64_ld_a64(mbox_set1);
+
+ KDASSERTMSG(mbox0 == 1, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
+ KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
+
+ uint64_t sum0 = mips64_ld_a64(int_sum0);
+ uint64_t sum1 = mips64_ld_a64(int_sum1);
+
+ KDASSERTMSG((sum0 & sum_mbox_lo) != 0, "sum0 %#"PRIx64, sum0);
+ KDASSERTMSG((sum0 & sum_mbox_hi) == 0, "sum0 %#"PRIx64, sum0);
+
+ KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1);
+ KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1);
+
+ mips64_sd_a64(mbox_clr0, mbox0);
+ mbox0 = mips64_ld_a64(mbox_set0);
+ KDASSERTMSG(mbox0 == 0, "mbox0 %#x", mbox0);
+
+ mips64_sd_a64(mbox_set0, __BIT(16));
+
+ mbox0 = mips64_ld_a64(mbox_set0);
+ mbox1 = mips64_ld_a64(mbox_set1);
+
+ KDASSERTMSG(mbox0 == __BIT(16), "mbox0 %#x", mbox0);
+ KDASSERTMSG(mbox1 == 0, "mbox1 %#x", mbox1);
+
+ sum0 = mips64_ld_a64(int_sum0);
+ sum1 = mips64_ld_a64(int_sum1);
+
+ KDASSERTMSG((sum0 & sum_mbox_lo) == 0, "sum0 %#"PRIx64, sum0);
+ KDASSERTMSG((sum0 & sum_mbox_hi) != 0, "sum0 %#"PRIx64, sum0);
+
+ KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1);
+ KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1);
+}
+#endif
+
#undef X
void
@@ -233,25 +302,25 @@ octeon_intr_init(struct cpu_info *ci)
{
const int cpunum = cpu_index(ci);
const char * const xname = cpu_name(ci);
- struct cpu_softc *cpu;
+ struct cpu_softc *cpu = ci->ci_softc;
- ipl_sr_map = octeon_ipl_sr_map;
if (ci->ci_cpuid == 0) {
+ KASSERT(ci->ci_softc == &octeon_cpu0_softc);
+ ipl_sr_map = octeon_ipl_sr_map;
mutex_init(&octeon_intr_lock, MUTEX_DEFAULT, IPL_HIGH);
- cpu = &octeon_cpu0_softc;
#ifdef MULTIPROCESSOR
mips_locoresw.lsw_send_ipi = octeon_send_ipi;
#endif
+#ifdef DEBUG
+ octeon_mbox_test();
+#endif
} else {
KASSERT(cpunum == 1);
#ifdef MULTIPROCESSOR
- cpu = &octeon_cpu1_softc;
-#else
- cpu = NULL;
+ KASSERT(ci->ci_softc == &octeon_cpu1_softc);
#endif
}
- ci->ci_softc = cpu;
#ifdef MULTIPROCESSOR
// Enable the IPIs
@@ -259,6 +328,11 @@ octeon_intr_init(struct cpu_info *ci)
cpu->cpu_int2_enable0 |= __BIT(_CIU_INT_MBOX_31_16_SHIFT);
#endif
+ if (ci->ci_dev)
+ aprint_verbose_dev(ci->ci_dev,
+ "enabling intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
+ cpu->cpu_int0_enable0, cpu->cpu_int1_enable0, cpu->cpu_int2_enable0);
+
mips64_sd_a64(cpu->cpu_int0_en0, cpu->cpu_int0_enable0);
mips64_sd_a64(cpu->cpu_int1_en0, cpu->cpu_int1_enable0);
mips64_sd_a64(cpu->cpu_int2_en0, cpu->cpu_int2_enable0);
@@ -429,6 +503,7 @@ octeon_iointr(int ipl, vaddr_t pc, uint3
struct cpu_info * const ci = curcpu();
struct cpu_softc * const cpu = ci->ci_softc;
+ KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
KASSERT((ipending & ~MIPS_INT_MASK) == 0);
KASSERT(ipending & MIPS_HARD_INT_MASK);
uint64_t hwpend = 0;
@@ -463,8 +538,10 @@ octeon_iointr(int ipl, vaddr_t pc, uint3
(*ih->ih_func)(ih->ih_arg);
}
#endif
+ KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
}
}
+ KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
}
#ifdef MULTIPROCESSOR
@@ -475,17 +552,34 @@ octeon_ipi_intr(void *arg)
{
struct cpu_info * const ci = curcpu();
struct cpu_softc * const cpu = ci->ci_softc;
- uint64_t ipi_mask = (uintptr_t) arg;
+ uint32_t ipi_mask = (uintptr_t) arg;
+
+ KASSERTMSG((ipi_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
+ "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
ipi_mask &= mips64_ld_a64(cpu->cpu_mbox_set);
+ if (ipi_mask == 0)
+ return 0;
+
mips64_sd_a64(cpu->cpu_mbox_clr, ipi_mask);
ipi_mask |= (ipi_mask >> 16);
ipi_mask &= __BITS(15,0);
- KASSERT(ci->ci_cpl >= IPL_SCHED);
KASSERT(ipi_mask < __BIT(NIPIS));
+#if NWDOG > 0
+ // Handle WDOG requests ourselves.
+ if (ipi_mask & __BIT(IPI_WDOG)) {
+ softint_schedule(cpu->cpu_wdog_sih);
+ atomic_and_64(&ci->ci_request_ipis, ~__BIT(IPI_WDOG));
+ ipi_mask &= ~__BIT(IPI_WDOG);
+ ci->ci_evcnt_per_ipi[IPI_WDOG].ev_count++;
+ if (__predict_true(ipi_mask == 0))
+ return 1;
+ }
+#endif
+
/* if the request is clear, it was previously processed */
if ((ci->ci_request_ipis & ipi_mask) == 0)
return 0;
@@ -503,17 +597,24 @@ octeon_ipi_intr(void *arg)
int
octeon_send_ipi(struct cpu_info *ci, int req)
{
-
KASSERT(req < NIPIS);
if (ci == NULL) {
- // only deals with 2 CPUs
- ci = cpuid_infos[(cpu_number() == 0) ? 1 : 0];
+ CPU_INFO_ITERATOR cii;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ if (ci != curcpu()) {
+ octeon_send_ipi(ci, req);
+ }
+ }
+ return 0;
}
+ KASSERT(cold || ci->ci_softc != NULL);
+ if (ci->ci_softc == NULL)
+ return -1;
struct cpu_softc * const cpu = ci->ci_softc;
uint64_t ipi_mask = __BIT(req);
- if (req == IPI_SUSPEND) {
+ if (__BIT(req) == (__BIT(IPI_SUSPEND)|__BIT(IPI_WDOG))) {
ipi_mask <<= 16;
}
Index: src/sys/arch/mips/cavium/octeonvar.h
diff -u src/sys/arch/mips/cavium/octeonvar.h:1.2 src/sys/arch/mips/cavium/octeonvar.h:1.3
--- src/sys/arch/mips/cavium/octeonvar.h:1.2 Mon Jun 1 22:55:12 2015
+++ src/sys/arch/mips/cavium/octeonvar.h Sat Jun 6 20:52:16 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: octeonvar.h,v 1.2 2015/06/01 22:55:12 matt Exp $ */
+/* $NetBSD: octeonvar.h,v 1.3 2015/06/06 20:52:16 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -81,6 +81,7 @@ struct octeon_config {
struct cpu_softc {
struct cpu_info *cpu_ci;
+
uint64_t cpu_int0_sum0;
uint64_t cpu_int1_sum0;
uint64_t cpu_int2_sum0;
@@ -101,6 +102,10 @@ struct cpu_softc {
uint64_t cpu_int1_enable0;
uint64_t cpu_int2_enable0;
+ void *cpu_wdog_sih; // wdog softint handler
+ uint64_t cpu_wdog;
+ uint64_t cpu_pp_poke;
+
#ifdef MULTIPROCESSOR
uint64_t cpu_mbox_set;
uint64_t cpu_mbox_clr;
