Module Name: src
Committed By: macallan
Date: Tue Jun 30 04:10:10 UTC 2015
Modified Files:
src/sys/arch/evbmips/ingenic: clock.c
Log Message:
don't mess with the cycle counter event counter, out timer interrupt comes
from elsewhere and is counted there
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/clock.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.5 src/sys/arch/evbmips/ingenic/clock.c:1.6
--- src/sys/arch/evbmips/ingenic/clock.c:1.5 Wed Dec 31 15:25:08 2014
+++ src/sys/arch/evbmips/ingenic/clock.c Tue Jun 30 04:10:10 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $ */
+/* $NetBSD: clock.c,v 1.6 2015/06/30 04:10:10 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.6 2015/06/30 04:10:10 macallan Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -194,7 +194,6 @@ ingenic_clockintr(uint32_t id)
#ifdef USE_OST
uint32_t new_cnt;
#endif
- ci->ci_ev_count_compare.ev_count++;
/* clear flags */
writereg(JZ_TC_TFCR, TFR_OSTFLAG);
