Module Name: src
Committed By: knakahara
Date: Tue Oct 13 08:23:32 UTC 2015
Modified Files:
src/sys/dev/pci: if_wm.c if_wmreg.h
Log Message:
change const value register macros to macro expressions to support multiqueue.
To generate a diff of this commit:
cvs rdiff -u -r1.360 -r1.361 src/sys/dev/pci/if_wm.c
cvs rdiff -u -r1.82 -r1.83 src/sys/dev/pci/if_wmreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.360 src/sys/dev/pci/if_wm.c:1.361
--- src/sys/dev/pci/if_wm.c:1.360 Tue Oct 13 08:20:02 2015
+++ src/sys/dev/pci/if_wm.c Tue Oct 13 08:23:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.360 2015/10/13 08:20:02 knakahara Exp $ */
+/* $NetBSD: if_wm.c,v 1.361 2015/10/13 08:23:31 knakahara Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.360 2015/10/13 08:20:02 knakahara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.361 2015/10/13 08:23:31 knakahara Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -4364,10 +4364,10 @@ wm_init_locked(struct ifnet *ifp)
/* TX */
CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_TXINTR_IDX),
- EITR_TX_QUEUE0);
+ EITR_TX_QUEUE(0));
/* RX */
CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_RXINTR_IDX),
- EITR_RX_QUEUE0);
+ EITR_RX_QUEUE(0));
/* Link status */
CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_LINKINTR_IDX),
EITR_OTHER);
@@ -4457,7 +4457,7 @@ wm_init_locked(struct ifnet *ifp)
break;
default:
if (sc->sc_type == WM_T_82575)
- mask = EITR_RX_QUEUE0 |EITR_TX_QUEUE0
+ mask = EITR_RX_QUEUE(0) |EITR_TX_QUEUE(0)
| EITR_OTHER;
else
mask = (1 << WM_MSIX_RXINTR_IDX)
@@ -4523,7 +4523,7 @@ wm_init_locked(struct ifnet *ifp)
if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
/* Write TDT after TCTL.EN is set. See the document. */
- CSR_WRITE(sc, WMREG_TDT, 0);
+ CSR_WRITE(sc, WMREG_TDT(0), 0);
}
if (sc->sc_type == WM_T_80003) {
@@ -4961,7 +4961,7 @@ wm_82547_txfifo_stall(void *arg)
goto out;
if (txq->txq_fifo_stall) {
- if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
+ if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) &&
CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
/*
@@ -5418,10 +5418,10 @@ wm_init_tx_regs(struct wm_softc *sc)
CSR_WRITE(sc, WMREG_OLD_TDT, 0);
CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
} else {
- CSR_WRITE(sc, WMREG_TDBAH, WM_CDTXADDR_HI(txq, 0));
- CSR_WRITE(sc, WMREG_TDBAL, WM_CDTXADDR_LO(txq, 0));
- CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(txq));
- CSR_WRITE(sc, WMREG_TDH, 0);
+ CSR_WRITE(sc, WMREG_TDBAH(0), WM_CDTXADDR_HI(txq, 0));
+ CSR_WRITE(sc, WMREG_TDBAL(0), WM_CDTXADDR_LO(txq, 0));
+ CSR_WRITE(sc, WMREG_TDLEN(0), WM_TXDESCSIZE(txq));
+ CSR_WRITE(sc, WMREG_TDH(0), 0);
if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
/*
@@ -5439,7 +5439,7 @@ wm_init_tx_regs(struct wm_softc *sc)
CSR_WRITE(sc, WMREG_TADV, sc->sc_itr / 4);
}
- CSR_WRITE(sc, WMREG_TDT, 0);
+ CSR_WRITE(sc, WMREG_TDT(0), 0);
CSR_WRITE(sc, WMREG_TXDCTL(0), TXDCTL_PTHRESH(0) |
TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
}
@@ -5476,7 +5476,7 @@ wm_init_tx_queue(struct wm_softc *sc)
if (sc->sc_type < WM_T_82543) {
txq->txq_tdt_reg = WMREG_OLD_TDT;
} else {
- txq->txq_tdt_reg = WMREG_TDT;
+ txq->txq_tdt_reg = WMREG_TDT(0);
}
wm_init_tx_descs(sc);
@@ -5511,25 +5511,25 @@ wm_init_rx_regs(struct wm_softc *sc)
CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
} else {
- CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(rxq, 0));
- CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(rxq, 0));
- CSR_WRITE(sc, WMREG_RDLEN,
+ CSR_WRITE(sc, WMREG_RDBAH(0), WM_CDRXADDR_HI(rxq, 0));
+ CSR_WRITE(sc, WMREG_RDBAL(0), WM_CDRXADDR_LO(rxq, 0));
+ CSR_WRITE(sc, WMREG_RDLEN(0),
sizeof(wiseman_rxdesc_t) * WM_NRXDESC);
if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
panic("%s: MCLBYTES %d unsupported for i2575 or higher\n", __func__, MCLBYTES);
- CSR_WRITE(sc, WMREG_SRRCTL, SRRCTL_DESCTYPE_LEGACY
+ CSR_WRITE(sc, WMREG_SRRCTL(0), SRRCTL_DESCTYPE_LEGACY
| (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
- CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_QUEUE_ENABLE
+ CSR_WRITE(sc, WMREG_RXDCTL(0), RXDCTL_QUEUE_ENABLE
| RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
| RXDCTL_WTHRESH(1));
} else {
- CSR_WRITE(sc, WMREG_RDH, 0);
- CSR_WRITE(sc, WMREG_RDT, 0);
+ CSR_WRITE(sc, WMREG_RDH(0), 0);
+ CSR_WRITE(sc, WMREG_RDT(0), 0);
CSR_WRITE(sc, WMREG_RDTR, 375 | RDTR_FPD); /* ITR/4 */
CSR_WRITE(sc, WMREG_RADV, 375); /* MUST be same */
- CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
+ CSR_WRITE(sc, WMREG_RXDCTL(0), RXDCTL_PTHRESH(0) |
RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
}
}
@@ -5589,7 +5589,7 @@ wm_init_rx_queue(struct wm_softc *sc)
if (sc->sc_type < WM_T_82543) {
rxq->rxq_rdt_reg = WMREG_OLD_RDT0;
} else {
- rxq->rxq_rdt_reg = WMREG_RDT;
+ rxq->rxq_rdt_reg = WMREG_RDT(0);
}
wm_init_rx_regs(sc);
@@ -7079,9 +7079,9 @@ wm_txintr_msix(void *arg)
("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
if (sc->sc_type == WM_T_82574)
- CSR_WRITE(sc, WMREG_IMC, ICR_TXQ0); /* 82574 only */
+ CSR_WRITE(sc, WMREG_IMC, ICR_TXQ(0)); /* 82574 only */
else if (sc->sc_type == WM_T_82575)
- CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE0);
+ CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE(0));
else
CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_TXINTR_IDX);
@@ -7097,9 +7097,9 @@ out:
WM_TX_UNLOCK(txq);
if (sc->sc_type == WM_T_82574)
- CSR_WRITE(sc, WMREG_IMS, ICR_TXQ0); /* 82574 only */
+ CSR_WRITE(sc, WMREG_IMS, ICR_TXQ(0)); /* 82574 only */
else if (sc->sc_type == WM_T_82575)
- CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE0);
+ CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE(0));
else
CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_TXINTR_IDX);
@@ -7126,9 +7126,9 @@ wm_rxintr_msix(void *arg)
("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
if (sc->sc_type == WM_T_82574)
- CSR_WRITE(sc, WMREG_IMC, ICR_RXQ0); /* 82574 only */
+ CSR_WRITE(sc, WMREG_IMC, ICR_RXQ(0)); /* 82574 only */
else if (sc->sc_type == WM_T_82575)
- CSR_WRITE(sc, WMREG_EIMC, EITR_RX_QUEUE0);
+ CSR_WRITE(sc, WMREG_EIMC, EITR_RX_QUEUE(0));
else
CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_RXINTR_IDX);
@@ -7144,9 +7144,9 @@ out:
WM_RX_UNLOCK(rxq);
if (sc->sc_type == WM_T_82574)
- CSR_WRITE(sc, WMREG_IMS, ICR_RXQ0);
+ CSR_WRITE(sc, WMREG_IMS, ICR_RXQ(0));
else if (sc->sc_type == WM_T_82575)
- CSR_WRITE(sc, WMREG_EIMS, EITR_RX_QUEUE0);
+ CSR_WRITE(sc, WMREG_EIMS, EITR_RX_QUEUE(0));
else
CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_RXINTR_IDX);
Index: src/sys/dev/pci/if_wmreg.h
diff -u src/sys/dev/pci/if_wmreg.h:1.82 src/sys/dev/pci/if_wmreg.h:1.83
--- src/sys/dev/pci/if_wmreg.h:1.82 Thu Oct 8 04:30:25 2015
+++ src/sys/dev/pci/if_wmreg.h Tue Oct 13 08:23:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.82 2015/10/08 04:30:25 msaitoh Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.83 2015/10/13 08:23:31 knakahara Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -433,10 +433,8 @@ struct livengood_tcpip_ctxdesc {
#define ICR_MDAC (1U << 9) /* MDIO access complete */
#define ICR_RXCFG (1U << 10) /* Receiving /C/ */
#define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */
-#define ICR_RXQ0 __BIT(20) /* 82574: Rx queue 0 interrupt */
-#define ICR_RXQ1 __BIT(21) /* 82574: Rx queue 1 interrupt */
-#define ICR_TXQ0 __BIT(22) /* 82574: Tx queue 0 interrupt */
-#define ICR_TXQ1 __BIT(23) /* 82574: Tx queue 1 interrupt */
+#define ICR_RXQ(x) __BIT(20+(x)) /* 82574: Rx queue x interrupt x=0,1 */
+#define ICR_TXQ(x) __BIT(22+(x)) /* 82574: Tx queue x interrupt x=0,1 */
#define ICR_OTHER __BIT(24) /* 82574: Other interrupt */
#define ICR_INT (1U << 31) /* device generated an interrupt */
@@ -478,8 +476,8 @@ struct livengood_tcpip_ctxdesc {
/* See ICR bits. */
#define WMREG_EIAC_82574 0x00dc /* Interrupt Auto Clear Register */
-#define WMREG_EIAC_82574_MSIX_MASK (ICR_RXQ0 | ICR_RXQ1 \
- | ICR_TXQ0 | ICR_TXQ1 | ICR_OTHER)
+#define WMREG_EIAC_82574_MSIX_MASK (ICR_RXQ(0) | ICR_RXQ(1) \
+ | ICR_TXQ(0) | ICR_TXQ(1) | ICR_OTHER)
#define WMREG_RCTL 0x0100 /* Receive Control */
#define RCTL_EN (1U << 1) /* receiver enable */
@@ -516,19 +514,23 @@ struct livengood_tcpip_ctxdesc {
#define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */
#define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */
-#define WMREG_RDBAL 0x2800
-#define WMREG_RDBAL_2 0x0c00 /* for 82576 ... */
+#define WMREG_RDBAL(x) \
+ ((x) < 4 ? (0x02800 + ((x) * 0x100)) : \
+ (0x0C000 + ((x) * 0x40)))
#define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */
-#define WMREG_RDBAH 0x2804
-#define WMREG_RDBAH_2 0x0c04 /* for 82576 ... */
+#define WMREG_RDBAH(x) \
+ ((x) < 4 ? (0x02804 + ((x) * 0x100)) : \
+ (0x0c004 + ((x) * 0x40)))
#define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */
-#define WMREG_RDLEN 0x2808
-#define WMREG_RDLEN_2 0x0c08 /* for 82576 ... */
-
-#define WMREG_SRRCTL 0x280c /* additional recv control used in 82575 ... */
-#define WMREG_SRRCTL_2 0x0c0c /* for 82576 ... */
+#define WMREG_RDLEN(x) \
+ ((x) < 4 ? (0x02808 + ((x) * 0x100)) : \
+ (0x0c008 + ((x) * 0x40)))
+
+#define WMREG_SRRCTL(x) \
+ ((x) < 4 ? (0x0280c + ((x) * 0x100)) : \
+ (0x0c00c + ((x) * 0x40))) /* additional recv control used in 82575 ... */
#define SRRCTL_BSIZEPKT_MASK 0x0000007f
#define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
#define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00
@@ -543,15 +545,18 @@ struct livengood_tcpip_ctxdesc {
#define SRRCTL_DROP_EN 0x80000000
#define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */
-#define WMREG_RDH 0x2810
-#define WMREG_RDH_2 0x0c10 /* for 82576 ... */
+#define WMREG_RDH(x) \
+ ((x) < 4 ? (0x02810 + ((x) * 0x100)) : \
+ (0x0C010 + ((x) * 0x40)))
#define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */
-#define WMREG_RDT 0x2818
-#define WMREG_RDT_2 0x0c18 /* for 82576 ... */
-
-#define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */
-#define WMREG_RXDCTL_2 0x0c28 /* for 82576 ... */
+#define WMREG_RDT(x) \
+ ((x) < 4 ? (0x02818 + ((x) * 0x100)) : \
+ (0x0C018 + ((x) * 0x40)))
+
+#define WMREG_RXDCTL(x) \
+ ((x) < 4 ? (0x02828 + ((x) * 0x100)) : \
+ (0x0c028 + ((x) * 0x40))) /* Receive Descriptor Control */
#define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */
#define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */
#define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */
@@ -634,19 +639,29 @@ struct livengood_tcpip_ctxdesc {
#define WMREG_TQC 0x0418
#define WMREG_OLD_TDBAL 0x0420 /* Transmit Descriptor Base Lo */
-#define WMREG_TDBAL 0x3800
+#define WMREG_TDBAL(x) \
+ ((x) < 4 ? (0x03800 + ((x) * 0x100)) : \
+ (0x0E000 + ((x) * 0x40)))
#define WMREG_OLD_TDBAH 0x0424 /* Transmit Descriptor Base Hi */
-#define WMREG_TDBAH 0x3804
+#define WMREG_TDBAH(x)\
+ ((x) < 4 ? (0x03804 + ((x) * 0x100)) : \
+ (0x0E004 + ((x) * 0x40)))
#define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */
-#define WMREG_TDLEN 0x3808
+#define WMREG_TDLEN(x) \
+ ((x) < 4 ? (0x03808 + ((x) * 0x100)) : \
+ (0x0E008 + ((x) * 0x40)))
#define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */
-#define WMREG_TDH 0x3810
+#define WMREG_TDH(x) \
+ ((x) < 4 ? (0x03810 + ((x) * 0x100)) : \
+ (0x0E010 + ((x) * 0x40)))
#define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */
-#define WMREG_TDT 0x3818
+#define WMREG_TDT(x) \
+ ((x) < 4 ? (0x03818 + ((x) * 0x100)) : \
+ (0x0E018 + ((x) * 0x40)))
#define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */
#define WMREG_TIDV 0x3820
@@ -768,14 +783,8 @@ struct livengood_tcpip_ctxdesc {
#define WMREG_MSIXBM(x) (0x1600 + (x) * 4) /* MSI-X Allocation */
-#define EITR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
-#define EITR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
-#define EITR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
-#define EITR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
-#define EITR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
-#define EITR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
-#define EITR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
-#define EITR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
+#define EITR_RX_QUEUE(x) __BIT(0+(x)) /* Rx Queue x Interrupt x=[0-3] */
+#define EITR_TX_QUEUE(x) __BIT(8+(x)) /* Tx Queue x Interrupt x=[0-3] */
#define EITR_TCP_TIMER 0x40000000 /* TCP Timer */
#define EITR_OTHER 0x80000000 /* Interrupt Cause Active */
