Module Name: src Committed By: msaitoh Date: Fri Oct 30 20:03:45 UTC 2015
Modified Files: src/sys/dev/pci: pci_subr.c pcireg.h pcivar.h Log Message: - Move PCI_INTRSTR_LEN from pcireg.h to pcivar.h. - In PCI-X cap, print 2nd bus's PCI-X mode, error protection type, Max clock frequency and Max clock period. - In SATA cap, print register location correctly. - In Virtual Channel cap, print reference clock with "ns". - In Root Complex Link Declaration, print Link Entry number. To generate a diff of this commit: cvs rdiff -u -r1.139 -r1.140 src/sys/dev/pci/pci_subr.c cvs rdiff -u -r1.105 -r1.106 src/sys/dev/pci/pcireg.h cvs rdiff -u -r1.106 -r1.107 src/sys/dev/pci/pcivar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/pci/pci_subr.c diff -u src/sys/dev/pci/pci_subr.c:1.139 src/sys/dev/pci/pci_subr.c:1.140 --- src/sys/dev/pci/pci_subr.c:1.139 Wed Oct 21 15:01:01 2015 +++ src/sys/dev/pci/pci_subr.c Fri Oct 30 20:03:45 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: pci_subr.c,v 1.139 2015/10/21 15:01:01 msaitoh Exp $ */ +/* $NetBSD: pci_subr.c,v 1.140 2015/10/30 20:03:45 msaitoh Exp $ */ /* * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. @@ -40,7 +40,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.139 2015/10/21 15:01:01 msaitoh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.140 2015/10/30 20:03:45 msaitoh Exp $"); #ifdef _KERNEL_OPT #include "opt_pci.h" @@ -1111,6 +1111,43 @@ pcix_split_trans(unsigned int idx) } static void +pci_conf_print_pcix_cap_2ndbusmode(int num) +{ + const char *maxfreq, *maxperiod; + + printf(" Mode: "); + if (num <= 0x07) + printf("PCI-X Mode 1\n"); + else if (num <= 0x0b) + printf("PCI-X 266 (Mode 2)\n"); + else + printf("PCI-X 533 (Mode 2)\n"); + + printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); + switch (num & 0x03) { + default: + case 0: + maxfreq = "N/A"; + maxperiod = "N/A"; + break; + case 1: + maxfreq = "66MHz"; + maxperiod = "15ns"; + break; + case 2: + maxfreq = "100MHz"; + maxperiod = "10ns"; + break; + case 3: + maxfreq = "133MHz"; + maxperiod = "7.5ns"; + break; + } + printf(" Max Clock Freq: %s\n", maxfreq); + printf(" Min Clock Period: %s\n", maxperiod); +} + +static void pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) { pcireg_t reg; @@ -1132,9 +1169,8 @@ pci_conf_print_pcix_cap(const pcireg_t * onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); - printf(" Secondary clock frequency: 0x%x\n", - (reg & PCIX_BRIDGE_2NDST_CLKF) - >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); + pci_conf_print_pcix_cap_2ndbusmode( + __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); printf(" Version: 0x%x\n", (reg & PCIX_BRIDGE_2NDST_VER_MASK) >> PCIX_BRIDGE_2NDST_VER_SHIFT); @@ -1807,9 +1843,14 @@ pci_conf_print_sata_cap(const pcireg_t * reg = regs[o2i(capoff + PCI_SATA_BAR)]; printf(" BAR Register: 0x%08x\n", reg); - printf(" BAR number: %d\n", (int)(reg & PCI_SATA_BAR_NUM)); - printf(" BAR offset: 0x%08x\n", - (pcireg_t)(reg & PCI_SATA_BAR_OFFSET)); + printf(" Register location: "); + if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) + printf("in config space\n"); + else { + printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); + printf(" BAR offset: 0x%08x\n", + (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); + } } static void @@ -2149,7 +2190,7 @@ pci_conf_print_vc_cap(const pcireg_t *re printf(" Low Priority Extended VC Count: %u\n", n); n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); printf(" Reference Clock: %s\n", - (n == PCI_VC_CAP1_REFCLK_100NS) ? "100" : "unknown"); + (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); @@ -2378,17 +2419,18 @@ pci_conf_print_rclink_dcl_cap(const pcir (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); for (i = 0; i < nent; i++) { reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; - printf(" Link Description Register: 0x%08x\n", reg); - onoff("Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); + printf(" Link Entry %d:\n", i + 1); + printf(" Link Description Register: 0x%08x\n", reg); + onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; - onoff2("Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, + onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, "Configuration Space", "Memory-Mapped Space"); - onoff("Associated RCRB Header", reg, + onoff(" Associated RCRB Header", reg, PCI_RCLINK_DCL_LINKDESC_ARCRBH); - printf(" Target Component ID: %hhu\n", + printf(" Target Component ID: %hhu\n", (unsigned char)__SHIFTOUT(reg, PCI_RCLINK_DCL_LINKDESC_TCOMPID)); - printf(" Target Port Number: %hhu\n", + printf(" Target Port Number: %hhu\n", (unsigned char)__SHIFTOUT(reg, PCI_RCLINK_DCL_LINKDESC_TPNUM)); @@ -2396,10 +2438,12 @@ pci_conf_print_rclink_dcl_cap(const pcir /* Memory-Mapped Space */ reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; - printf(" Link Address Low Register: 0x%08x\n", reg); + printf(" Link Address Low Register: 0x%08x\n", + reg); reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; - printf(" Link Address High Register: 0x%08x\n",reg); + printf(" Link Address High Register: 0x%08x\n", + reg); } else { unsigned int nb; pcireg_t lo, hi; @@ -2407,26 +2451,26 @@ pci_conf_print_rclink_dcl_cap(const pcir /* Configuration Space */ lo = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; - printf(" Configuration Space Low Register: 0x%08x" - "\n", lo); + printf(" Configuration Space Low Register: " + "0x%08x\n", lo); hi = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; - printf(" Configuration Space High Register: 0x%08x" - "\n", hi); + printf(" Configuration Space High Register: " + "0x%08x\n", hi); nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); - printf(" N: %u\n", nb); - printf(" Func: %hhu\n", + printf(" N: %u\n", nb); + printf(" Func: %hhu\n", (unsigned char)__SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); - printf(" Dev: %hhu\n", + printf(" Dev: %hhu\n", (unsigned char)__SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); - printf(" Bus: %hhu\n", + printf(" Bus: %hhu\n", (unsigned char)__SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); - printf(" Configuration Space Base Address: 0x%016" - PRIx64 "\n", ((uint64_t)hi << 32) + lo); + printf(" Configuration Space Base Address: " + "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); } } } Index: src/sys/dev/pci/pcireg.h diff -u src/sys/dev/pci/pcireg.h:1.105 src/sys/dev/pci/pcireg.h:1.106 --- src/sys/dev/pci/pcireg.h:1.105 Wed Oct 21 12:54:59 2015 +++ src/sys/dev/pci/pcireg.h Fri Oct 30 20:03:45 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: pcireg.h,v 1.105 2015/10/21 12:54:59 msaitoh Exp $ */ +/* $NetBSD: pcireg.h,v 1.106 2015/10/30 20:03:45 msaitoh Exp $ */ /* * Copyright (c) 1995, 1996, 1999, 2000 @@ -1084,7 +1084,9 @@ struct pci_msix_table_entry { #define PCI_SATA_REV_MINOR __BITS(19, 16) /* Minor Revision */ #define PCI_SATA_REV_MAJOR __BITS(23, 20) /* Major Revision */ #define PCI_SATA_BAR 0x04 /* BAR Register */ -#define PCI_SATA_BAR_NUM __BITS(3, 0) /* BAR Specifier */ +#define PCI_SATA_BAR_SPEC __BITS(3, 0) /* BAR Specifier */ +#define PCI_SATA_BAR_INCONF __BITS(3, 0) /* All 1 = in config space */ +#define PCI_SATA_BAR_NUM(x) (__SHIFTOUT((x), PCI_SATA_BAR_SPEC) - 4) #define PCI_SATA_BAR_OFFSET __BITS(23, 4) /* BAR Offset */ /* @@ -1851,9 +1853,4 @@ struct pci_rom { #define PCI_L1PM_CTL2_TPOSCALE __BITS(1, 0) /* T_POWER_ON Scale */ #define PCI_L1PM_CTL2_TPOVAL __BITS(7, 3) /* T_POWER_ON Value */ -/* - * Local constants - */ -#define PCI_INTRSTR_LEN 64 - #endif /* _DEV_PCI_PCIREG_H_ */ Index: src/sys/dev/pci/pcivar.h diff -u src/sys/dev/pci/pcivar.h:1.106 src/sys/dev/pci/pcivar.h:1.107 --- src/sys/dev/pci/pcivar.h:1.106 Thu Oct 22 09:45:32 2015 +++ src/sys/dev/pci/pcivar.h Fri Oct 30 20:03:45 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: pcivar.h,v 1.106 2015/10/22 09:45:32 knakahara Exp $ */ +/* $NetBSD: pcivar.h,v 1.107 2015/10/30 20:03:45 msaitoh Exp $ */ /* * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. @@ -381,6 +381,11 @@ int pcirescan(device_t, const char *, co int pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t); +/* + * Local constants + */ +#define PCI_INTRSTR_LEN 64 + #endif /* _KERNEL */ #endif /* _DEV_PCI_PCIVAR_H_ */