Module Name: src
Committed By: sborrill
Date: Mon Nov 9 12:35:32 UTC 2015
Added Files:
src/sys/dev/pci [netbsd-5]: if_bnxvar.h
Log Message:
Pull up the following revisions(s) (requested by msaitoh in ticket #1983):
sys/dev/pci/pcidevs: revisions 1.1079, 1.1134,
1.1148-1.1149, 1.1151
sys/dev/pci/pcidevs.h: regen
sys/dev/pci/pcidevs_data.h: regen
sys/dev/pci/if_bge.c: revisions 1.183-1.185, 1.187,
1.189-1.193, 1.195-1.199, 1.202-1.226, 1.228-1.237, 1.240-1.264, 1.267-1.276,
1.278-1.280, 1.283-1.287 via patch
sys/dev/pci/if_bgereg.h: revisions 1.57-1.74, 1.76-1.90 via patch
sys/dev/pci/if_bgevar.h: revisions 1.6, 1.10-1.13, 1.15-1.17 via
patch
sys/dev/pci/if_bnx.c: revisions 1.32, 1.34-1.43, 1.48-1.49,
1.52
sys/dev/pci/if_bnxreg.h: revisions 1.8, 1.11-1.14
sys/dev/pci/if_bnxvar.h: revisions 1.1-1.3
sys/dev/mii/brgphy.c: revisions 1.53-1.63, 1.65-69, 1.72-1.74
via patch
sys/dev/mii/brgphyreg.h: revisions 1.5-1.8
sys/dev/mii/miivar.h: revisions 1.61
sys/dev/pci/pcireg.h: patch
Sync bge(4) up to if_bge.c rev. 1.287. Sync brgphy(4) up to 1.74.
Fix some bugs on bnx(4).
Common:
- Add device IDs for Broadcom BCM57710, BCM57711(E), BCM57712(E) and
BCM57766 (pcidevs only).
- Fix BCM5709 PHY detection.
- Fix detection of BGEPHYF_FIBER_{MII|TBI}
- Add BCM5708S support in brgphy(4).
- Don't use the WIRESPEED function for fiber devices.
bge(4):
- Add some Fujitsu's device support from Michael Moll.
- Add BCM57762 support (PR#46961 from Ryo Onodera).
- Add Altima AC1003, APPLE BCM5701, Broadcom BCM5785F. BCM5785G,
BCM5787F, BCM5719, BCM5720, BCM57766, BCM57782 and BCM57786.
- Fix DMA setting for read/write on conventional PCI bus devices.
This bug was added in rev. 1.166.
- Fix printing "discarding oversize frame (len=-4)" message and
crash by NULL pointer dereferencing.
- The BCM5785 is a PCIe chip but does not report PCIe capabilities.
Check for this chip explicitely and enable PCIe. Fixes
'firmware handshake timeout'.
- Allow disabling interrupt mitigation.
- Workaround for BCM5906 silicon bug. When auto-negotiation results
in half-duplex operation, excess collision on the ethernet link may
cause internal chip delays that may result in subsequent valid
frames being dropped due to insufficient receive buffer resources.
(FreeBSD: r214219, r214251, r214292).
- Allow write DMA to request larger DMA burst size to get better
performance on BCM5785. (FreeBSD r213333: OpenBSD 1.294)
- Enable TX MAC state machine lockup fix for both BCM5755 or higher
and BCM5906. Publicly available data sheet just says it may happen
due to corrupted TxMbuf. (FreeBSD r214216)
- Follow Broadcom datasheet:
Delay 100 microseconds after enabling transmit MAC.
Delay 10 microseconds after enabling receive MAC. (FreeBSD
r241220)
- Insert the completion barrier between register write and the
consecutive delay(). It will fix some device timeout problems we have
seen before.
- Add DELAY(40) after turning on write DMA state machine.
- Add some workarounds for 5717 A0 and 5776[56] to be stable.
- Check BGE_RXBDFLAG_IPV6 flag for 5717_PLUS case. Note that
{tcp,udp}6csum flag is currently not added in the capability.
- Add delay after clearing BGE_MACMODE_TBI_SEND_CFGS for the link
checking.
- Do not touch the jumbo replenish threshold register on chips that do
not have jumbo support.
- Wait for the bootcode to complete initialization for 5717 and newer
devices.
- 5718 and 57785 document say we should wait 100us in init.
- Fix a bug that chips which have BCM5906 ASIC touch GPIO wrongly.
- Fix the setting of Tx Random Backoff Register.
- Check the hardware config words and print them.
- Set BGE_MISC_CTL's byte/word swap options before using
bge_readmem_ind(). Fixes PR#47716.
- For BGE_IS_575X_PLUS() devices, don't set
BGE_RXLPSTATCONTROL_DACK_FIX bits because these bits are reserved.
- Document says 5717 and newer chips have no
BGE_PCISTATE_INTR_NOT_ACTIVE bit, so don't use the bit on those
chips. Same as OpenBSD.
- Fix a bug that the PHY address bits in MI_MODE register is wrongly
cleard. Set the PHY address correctly.
- Use BGE_SETBIT() instead of CSR_WRITE_4() for the BGE_MISC_LOCAL_CTL
register to not to modify some GPIO bits.
- Set DMA watermark depend on the PCI max payload size.
- Set BGE_JUMBO_CAPABLE correctly.
- Fix a link detect bug on non-autopoll systems.
- Change the TX ring size for 5717 series and 57764 series.
- Set maximum read byte count to 2048 for PCI-X BCM5703/5704 devices.
- For PCI-X BCM5704, set maximum outstanding split transactions to 0.
- Add 40bit DMA bug workaround(BGEF_40BIT_BUG) from FreeBSD.
This workaround is for 5714/5715 controllers and is not actually a
MAC controller bug but an issue with the embedded PCIe to PCI-X
bridge in the device. This change uses bus_dmatag_subregion(),
so this workaround won't work on some archs which doesn't support
bus_dmatag_subregion().
- Add 2500SX support (not tested).
- Don't use the PHY Auto Poll Mode on many chips. This fixes a bug
that MII Fiber NIC drop packet about 50%. Tested on HP Moonshot.
- Add workaround for PR#48451. Some BCM5717-5720 based systems getNMI
on boot. This problem doesn't occur when we don't use prefetchable
memory in the APE area. Tested with HP MicroServer Gen8.
- In the BCM5703, the DMA read watermark should be set to less than
or equal to the maximum memory read byte count of the PCI-X command
register.
- Fix a bug that BGE_PHY_TEST_CTRL_REG isn't set correctly on some
PCIe devices.
- Use another firmware command in bge_asf_driver_up(). Same as Linux.
This change fixes a bug that watchdog timeout occurs every 25-30
minutes on HP ML110 G6 reported enami@ in PR#49657.
- Fix mbuf leak on failure.
- Remove PCI_PRODUCT_BROADCOM_BCM5724 and
PCI_PRODUCT_BROADCOM_BCM5750M. These devices have not released to
public.
- Add some workaround code for BGE_ASICREV_BCM5784 from Linux.
- Change some printf() to aprint_*().
- Fix typo in comments.
- Cleanup.
brgphy(4):
- Fix bit definition of BRGPHY_MRBE_MSG_PG5_NP_T2 from FreeBSD.
- Add BCM5481, BCM5709S, BCM5756, BCM5717C, BCM5720C, BCM5785,
BCM57765(PR#46961), BCM57780
- In brgphyattach(), set sc_isbge, sc_isbnx and sc_phyflags before
PHY_RESET() because brgphy_reset() refers those flags.
- Call brgpy specific autonego function in MII_TICK. Before this
commit, only MII_MEDIACHG calls brgphy_mii_phy_auto() and MII_TICK
calls MI mii_phy_auto(). That was not intended.
- Remove extra delay in brgphy_mii_phy_auto. Same as {Free,Open}BSD.
bnx(4):
- Add missing ifmedia_delete_instance() in bnx_detach().
- Fix a bug that BNX_NO_WOL_FLAG isn't correctly set on some chips.
Reported by From Henning Petersen in PR#44151.
- Fix SERDES initialization.
- Get out of the interrupt handler early if !IFF_RUNNING.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.6.8.2 src/sys/dev/pci/if_bnxvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/dev/pci/if_bnxvar.h
diff -u /dev/null src/sys/dev/pci/if_bnxvar.h:1.6.8.2
--- /dev/null Mon Nov 9 12:35:32 2015
+++ src/sys/dev/pci/if_bnxvar.h Mon Nov 9 12:35:32 2015
@@ -0,0 +1,1329 @@
+/* $NetBSD */
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jean-Yves Migeon <j...@netbsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $
+ */
+
+#ifndef _DEV_PCI_IF_BNXVAR_H_
+#define _DEV_PCI_IF_BNXVAR_H_
+
+#ifdef _KERNEL_OPT
+#include "bpfilter.h"
+#include "opt_inet.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/sysctl.h>
+//#include <sys/workqueue.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_ether.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_inarp.h>
+#endif
+
+#include <net/if_vlanvar.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+#include <dev/mii/brgphyreg.h>
+
+/*
+ * PCI registers defined in the PCI 2.2 spec.
+ */
+#define BNX_PCI_BAR0 0x10
+#define BNX_PCI_PCIX_CMD 0x40
+
+/****************************************************************************/
+/* Convenience definitions. */
+/****************************************************************************/
+#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
+#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
+#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
+#define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset)
+#define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val)
+#define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val)
+#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
+#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
+#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
+#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
+
+/****************************************************************************/
+/* BNX Device State Data Structure */
+/****************************************************************************/
+
+#define BNX_STATUS_BLK_SZ sizeof(struct status_block)
+#define BNX_STATS_BLK_SZ sizeof(struct statistics_block)
+#define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
+#define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
+
+struct bnx_pkt {
+ TAILQ_ENTRY(bnx_pkt) pkt_entry;
+ bus_dmamap_t pkt_dmamap;
+ struct mbuf *pkt_mbuf;
+ u_int16_t pkt_end_desc;
+};
+
+TAILQ_HEAD(bnx_pkt_list, bnx_pkt);
+
+struct bnx_softc
+{
+ device_t bnx_dev;
+ struct ethercom bnx_ec;
+ struct pci_attach_args bnx_pa;
+
+ struct ifmedia bnx_ifmedia; /* TBI media info */
+
+ bus_space_tag_t bnx_btag; /* Device bus tag */
+ bus_space_handle_t bnx_bhandle; /* Device bus handle */
+ bus_size_t bnx_size;
+
+ void *bnx_intrhand; /* Interrupt handler */
+
+ /* ASIC Chip ID. */
+ u_int32_t bnx_chipid;
+
+ /* General controller flags. */
+ u_int32_t bnx_flags;
+
+ /* PHY specific flags. */
+ u_int32_t bnx_phy_flags;
+
+ /* Values that need to be shared with the PHY driver. */
+ u_int32_t bnx_shared_hw_cfg;
+ u_int32_t bnx_port_hw_cfg;
+
+ u_int16_t bus_speed_mhz; /* PCI bus speed */
+ struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */
+ u_int32_t bnx_flash_size; /* Flash NVRAM size */
+ u_int32_t bnx_shmem_base; /* Shared Memory base address */
+ char * bnx_name; /* Name string */
+
+ /* Tracks the version of bootcode firmware. */
+ u_int32_t bnx_fw_ver;
+
+ /* Tracks the state of the firmware. 0 = Running while any */
+ /* other value indicates that the firmware is not responding. */
+ u_int16_t bnx_fw_timed_out;
+
+ /* An incrementing sequence used to coordinate messages passed */
+ /* from the driver to the firmware. */
+ u_int16_t bnx_fw_wr_seq;
+
+ /* An incrementing sequence used to let the firmware know that */
+ /* the driver is still operating. Without the pulse, management */
+ /* firmware such as IPMI or UMP will operate in OS absent state. */
+ u_int16_t bnx_fw_drv_pulse_wr_seq;
+
+ /* Ethernet MAC address. */
+ u_char eaddr[6];
+
+ /* These setting are used by the host coalescing (HC) block to */
+ /* to control how often the status block, statistics block and */
+ /* interrupts are generated. */
+ u_int16_t bnx_tx_quick_cons_trip_int;
+ u_int16_t bnx_tx_quick_cons_trip;
+ u_int16_t bnx_rx_quick_cons_trip_int;
+ u_int16_t bnx_rx_quick_cons_trip;
+ u_int16_t bnx_comp_prod_trip_int;
+ u_int16_t bnx_comp_prod_trip;
+ u_int16_t bnx_tx_ticks_int;
+ u_int16_t bnx_tx_ticks;
+ u_int16_t bnx_rx_ticks_int;
+ u_int16_t bnx_rx_ticks;
+ u_int16_t bnx_com_ticks_int;
+ u_int16_t bnx_com_ticks;
+ u_int16_t bnx_cmd_ticks_int;
+ u_int16_t bnx_cmd_ticks;
+ u_int32_t bnx_stats_ticks;
+
+ /* The address of the integrated PHY on the MII bus. */
+ int bnx_phy_addr;
+
+ /* The device handle for the MII bus child device. */
+ struct mii_data bnx_mii;
+
+ /* Driver maintained TX chain pointers and byte counter. */
+ u_int16_t rx_prod;
+ u_int16_t rx_cons;
+ u_int32_t rx_prod_bseq; /* Counts the bytes used. */
+ u_int16_t tx_prod;
+ u_int16_t tx_cons;
+ u_int32_t tx_prod_bseq; /* Counts the bytes used. */
+
+ struct callout bnx_timeout;
+
+ /* Frame size and mbuf allocation size for RX frames. */
+ u_int32_t max_frame_size;
+ int mbuf_alloc_size;
+
+ /* Receive mode settings (i.e promiscuous, multicast, etc.). */
+ u_int32_t rx_mode;
+
+ /* Bus tag for the bnx controller. */
+ bus_dma_tag_t bnx_dmatag;
+
+ /* H/W maintained TX buffer descriptor chain structure. */
+ bus_dma_segment_t tx_bd_chain_seg[TX_PAGES];
+ int tx_bd_chain_rseg[TX_PAGES];
+ bus_dmamap_t tx_bd_chain_map[TX_PAGES];
+ struct tx_bd *tx_bd_chain[TX_PAGES];
+ bus_addr_t tx_bd_chain_paddr[TX_PAGES];
+
+ /* H/W maintained RX buffer descriptor chain structure. */
+ bus_dma_segment_t rx_bd_chain_seg[RX_PAGES];
+ int rx_bd_chain_rseg[RX_PAGES];
+ bus_dmamap_t rx_bd_chain_map[RX_PAGES];
+ struct rx_bd *rx_bd_chain[RX_PAGES];
+ bus_addr_t rx_bd_chain_paddr[RX_PAGES];
+
+ /* H/W maintained status block. */
+ bus_dma_segment_t status_seg;
+ int status_rseg;
+ bus_dmamap_t status_map;
+ struct status_block *status_block; /* virtual address */
+ bus_addr_t status_block_paddr; /* Physical address */
+
+ /* H/W maintained context block */
+ int ctx_pages;
+ bus_dma_segment_t ctx_segs[4];
+ int ctx_rsegs[4];
+ bus_dmamap_t ctx_map[4];
+ void *ctx_block[4];
+
+ /* Driver maintained status block values. */
+ u_int16_t last_status_idx;
+ u_int16_t hw_rx_cons;
+ u_int16_t hw_tx_cons;
+
+ /* H/W maintained statistics block. */
+ bus_dma_segment_t stats_seg;
+ int stats_rseg;
+ bus_dmamap_t stats_map;
+ struct statistics_block *stats_block; /* Virtual address */
+ bus_addr_t stats_block_paddr; /* Physical address */
+
+ /* Bus tag for RX/TX mbufs. */
+ bus_dma_segment_t rx_mbuf_seg;
+ int rx_mbuf_rseg;
+ bus_dma_segment_t tx_mbuf_seg;
+ int tx_mbuf_rseg;
+
+ /* S/W maintained mbuf TX chain structure. */
+ kmutex_t tx_pkt_mtx;
+ u_int tx_pkt_count;
+ struct bnx_pkt_list tx_free_pkts;
+ struct bnx_pkt_list tx_used_pkts;
+
+ /* S/W maintained mbuf RX chain structure. */
+ bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
+ struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
+
+ /* Track the number of rx_bd and tx_bd's in use. */
+ u_int16_t free_rx_bd;
+ u_int16_t max_rx_bd;
+ u_int16_t used_tx_bd;
+ u_int16_t max_tx_bd;
+
+ /* Provides access to hardware statistics through sysctl. */
+ u_int64_t stat_IfHCInOctets;
+ u_int64_t stat_IfHCInBadOctets;
+ u_int64_t stat_IfHCOutOctets;
+ u_int64_t stat_IfHCOutBadOctets;
+ u_int64_t stat_IfHCInUcastPkts;
+ u_int64_t stat_IfHCInMulticastPkts;
+ u_int64_t stat_IfHCInBroadcastPkts;
+ u_int64_t stat_IfHCOutUcastPkts;
+ u_int64_t stat_IfHCOutMulticastPkts;
+ u_int64_t stat_IfHCOutBroadcastPkts;
+
+ u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
+ u_int32_t stat_Dot3StatsCarrierSenseErrors;
+ u_int32_t stat_Dot3StatsFCSErrors;
+ u_int32_t stat_Dot3StatsAlignmentErrors;
+ u_int32_t stat_Dot3StatsSingleCollisionFrames;
+ u_int32_t stat_Dot3StatsMultipleCollisionFrames;
+ u_int32_t stat_Dot3StatsDeferredTransmissions;
+ u_int32_t stat_Dot3StatsExcessiveCollisions;
+ u_int32_t stat_Dot3StatsLateCollisions;
+ u_int32_t stat_EtherStatsCollisions;
+ u_int32_t stat_EtherStatsFragments;
+ u_int32_t stat_EtherStatsJabbers;
+ u_int32_t stat_EtherStatsUndersizePkts;
+ u_int32_t stat_EtherStatsOverrsizePkts;
+ u_int32_t stat_EtherStatsPktsRx64Octets;
+ u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets;
+ u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets;
+ u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets;
+ u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
+ u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
+ u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
+ u_int32_t stat_EtherStatsPktsTx64Octets;
+ u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets;
+ u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets;
+ u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets;
+ u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
+ u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
+ u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
+ u_int32_t stat_XonPauseFramesReceived;
+ u_int32_t stat_XoffPauseFramesReceived;
+ u_int32_t stat_OutXonSent;
+ u_int32_t stat_OutXoffSent;
+ u_int32_t stat_FlowControlDone;
+ u_int32_t stat_MacControlFramesReceived;
+ u_int32_t stat_XoffStateEntered;
+ u_int32_t stat_IfInFramesL2FilterDiscards;
+ u_int32_t stat_IfInRuleCheckerDiscards;
+ u_int32_t stat_IfInFTQDiscards;
+ u_int32_t stat_IfInMBUFDiscards;
+ u_int32_t stat_IfInRuleCheckerP4Hit;
+ u_int32_t stat_CatchupInRuleCheckerDiscards;
+ u_int32_t stat_CatchupInFTQDiscards;
+ u_int32_t stat_CatchupInMBUFDiscards;
+ u_int32_t stat_CatchupInRuleCheckerP4Hit;
+
+ /* Mbuf allocation failure counter. */
+ u_int32_t mbuf_alloc_failed;
+
+ /* TX DMA mapping failure counter. */
+ u_int32_t tx_dma_map_failures;
+
+#ifdef BNX_DEBUG
+ /* Track the number of enqueued mbufs. */
+ int tx_mbuf_alloc;
+ int rx_mbuf_alloc;
+
+ /* Track the distribution buffer segments. */
+ u_int32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1];
+
+ /* Track how many and what type of interrupts are generated. */
+ u_int32_t interrupts_generated;
+ u_int32_t interrupts_handled;
+ u_int32_t rx_interrupts;
+ u_int32_t tx_interrupts;
+
+ u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */
+ u_int32_t rx_empty_count; /* Number of times the RX chain was empty. */
+ u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */
+ u_int32_t tx_full_count; /* Number of times the TX chain was full. */
+ u_int32_t mbuf_sim_alloc_failed;/* Mbuf simulated allocation failure counter. */
+ u_int32_t l2fhdr_status_errors;
+ u_int32_t unexpected_attentions;
+ u_int32_t lost_status_block_updates;
+#endif
+};
+
+struct bnx_firmware_header {
+ int bnx_COM_FwReleaseMajor;
+ int bnx_COM_FwReleaseMinor;
+ int bnx_COM_FwReleaseFix;
+ u_int32_t bnx_COM_FwStartAddr;
+ u_int32_t bnx_COM_FwTextAddr;
+ int bnx_COM_FwTextLen;
+ u_int32_t bnx_COM_FwDataAddr;
+ int bnx_COM_FwDataLen;
+ u_int32_t bnx_COM_FwRodataAddr;
+ int bnx_COM_FwRodataLen;
+ u_int32_t bnx_COM_FwBssAddr;
+ int bnx_COM_FwBssLen;
+ u_int32_t bnx_COM_FwSbssAddr;
+ int bnx_COM_FwSbssLen;
+
+ int bnx_RXP_FwReleaseMajor;
+ int bnx_RXP_FwReleaseMinor;
+ int bnx_RXP_FwReleaseFix;
+ u_int32_t bnx_RXP_FwStartAddr;
+ u_int32_t bnx_RXP_FwTextAddr;
+ int bnx_RXP_FwTextLen;
+ u_int32_t bnx_RXP_FwDataAddr;
+ int bnx_RXP_FwDataLen;
+ u_int32_t bnx_RXP_FwRodataAddr;
+ int bnx_RXP_FwRodataLen;
+ u_int32_t bnx_RXP_FwBssAddr;
+ int bnx_RXP_FwBssLen;
+ u_int32_t bnx_RXP_FwSbssAddr;
+ int bnx_RXP_FwSbssLen;
+
+ int bnx_TPAT_FwReleaseMajor;
+ int bnx_TPAT_FwReleaseMinor;
+ int bnx_TPAT_FwReleaseFix;
+ u_int32_t bnx_TPAT_FwStartAddr;
+ u_int32_t bnx_TPAT_FwTextAddr;
+ int bnx_TPAT_FwTextLen;
+ u_int32_t bnx_TPAT_FwDataAddr;
+ int bnx_TPAT_FwDataLen;
+ u_int32_t bnx_TPAT_FwRodataAddr;
+ int bnx_TPAT_FwRodataLen;
+ u_int32_t bnx_TPAT_FwBssAddr;
+ int bnx_TPAT_FwBssLen;
+ u_int32_t bnx_TPAT_FwSbssAddr;
+ int bnx_TPAT_FwSbssLen;
+
+ int bnx_TXP_FwReleaseMajor;
+ int bnx_TXP_FwReleaseMinor;
+ int bnx_TXP_FwReleaseFix;
+ u_int32_t bnx_TXP_FwStartAddr;
+ u_int32_t bnx_TXP_FwTextAddr;
+ int bnx_TXP_FwTextLen;
+ u_int32_t bnx_TXP_FwDataAddr;
+ int bnx_TXP_FwDataLen;
+ u_int32_t bnx_TXP_FwRodataAddr;
+ int bnx_TXP_FwRodataLen;
+ u_int32_t bnx_TXP_FwBssAddr;
+ int bnx_TXP_FwBssLen;
+ u_int32_t bnx_TXP_FwSbssAddr;
+ int bnx_TXP_FwSbssLen;
+
+ /* Followed by blocks of data, each sized according to
+ * the (rather obvious) block length stated above.
+ *
+ * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata,
+ * bnx_COM_FwBss, bnx_COM_FwSbss,
+ *
+ * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata,
+ * bnx_RXP_FwBss, bnx_RXP_FwSbss,
+ *
+ * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata,
+ * bnx_TPAT_FwBss, bnx_TPAT_FwSbss,
+ *
+ * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata,
+ * bnx_TXP_FwBss, bnx_TXP_FwSbss,
+ */
+};
+
+#endif /* _DEV_PCI_IF_BNXVAR_H_ */
+/* $NetBSD */
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jean-Yves Migeon <j...@netbsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $
+ */
+
+#ifndef _DEV_PCI_IF_BNXVAR_H_
+#define _DEV_PCI_IF_BNXVAR_H_
+
+#ifdef _KERNEL_OPT
+#include "bpfilter.h"
+#include "opt_inet.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/sysctl.h>
+//#include <sys/workqueue.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_ether.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_inarp.h>
+#endif
+
+#include <net/if_vlanvar.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+#include <dev/mii/brgphyreg.h>
+
+/*
+ * PCI registers defined in the PCI 2.2 spec.
+ */
+#define BNX_PCI_BAR0 0x10
+#define BNX_PCI_PCIX_CMD 0x40
+
+/****************************************************************************/
+/* Convenience definitions. */
+/****************************************************************************/
+#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
+#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
+#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
+#define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset)
+#define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val)
+#define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val)
+#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
+#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
+#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
+#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
+
+/****************************************************************************/
+/* BNX Device State Data Structure */
+/****************************************************************************/
+
+#define BNX_STATUS_BLK_SZ sizeof(struct status_block)
+#define BNX_STATS_BLK_SZ sizeof(struct statistics_block)
+#define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
+#define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
+
+struct bnx_pkt {
+ TAILQ_ENTRY(bnx_pkt) pkt_entry;
+ bus_dmamap_t pkt_dmamap;
+ struct mbuf *pkt_mbuf;
+ u_int16_t pkt_end_desc;
+};
+
+TAILQ_HEAD(bnx_pkt_list, bnx_pkt);
+
+struct bnx_softc
+{
+ device_t bnx_dev;
+ struct ethercom bnx_ec;
+ struct pci_attach_args bnx_pa;
+
+ struct ifmedia bnx_ifmedia; /* TBI media info */
+
+ bus_space_tag_t bnx_btag; /* Device bus tag */
+ bus_space_handle_t bnx_bhandle; /* Device bus handle */
+ bus_size_t bnx_size;
+
+ void *bnx_intrhand; /* Interrupt handler */
+
+ /* ASIC Chip ID. */
+ u_int32_t bnx_chipid;
+
+ /* General controller flags. */
+ u_int32_t bnx_flags;
+
+ /* PHY specific flags. */
+ u_int32_t bnx_phy_flags;
+
+ /* Values that need to be shared with the PHY driver. */
+ u_int32_t bnx_shared_hw_cfg;
+ u_int32_t bnx_port_hw_cfg;
+
+ u_int16_t bus_speed_mhz; /* PCI bus speed */
+ struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */
+ u_int32_t bnx_flash_size; /* Flash NVRAM size */
+ u_int32_t bnx_shmem_base; /* Shared Memory base address */
+ char * bnx_name; /* Name string */
+
+ /* Tracks the version of bootcode firmware. */
+ u_int32_t bnx_fw_ver;
+
+ /* Tracks the state of the firmware. 0 = Running while any */
+ /* other value indicates that the firmware is not responding. */
+ u_int16_t bnx_fw_timed_out;
+
+ /* An incrementing sequence used to coordinate messages passed */
+ /* from the driver to the firmware. */
+ u_int16_t bnx_fw_wr_seq;
+
+ /* An incrementing sequence used to let the firmware know that */
+ /* the driver is still operating. Without the pulse, management */
+ /* firmware such as IPMI or UMP will operate in OS absent state. */
+ u_int16_t bnx_fw_drv_pulse_wr_seq;
+
+ /* Ethernet MAC address. */
+ u_char eaddr[6];
+
+ /* These setting are used by the host coalescing (HC) block to */
+ /* to control how often the status block, statistics block and */
+ /* interrupts are generated. */
+ u_int16_t bnx_tx_quick_cons_trip_int;
+ u_int16_t bnx_tx_quick_cons_trip;
+ u_int16_t bnx_rx_quick_cons_trip_int;
+ u_int16_t bnx_rx_quick_cons_trip;
+ u_int16_t bnx_comp_prod_trip_int;
+ u_int16_t bnx_comp_prod_trip;
+ u_int16_t bnx_tx_ticks_int;
+ u_int16_t bnx_tx_ticks;
+ u_int16_t bnx_rx_ticks_int;
+ u_int16_t bnx_rx_ticks;
+ u_int16_t bnx_com_ticks_int;
+ u_int16_t bnx_com_ticks;
+ u_int16_t bnx_cmd_ticks_int;
+ u_int16_t bnx_cmd_ticks;
+ u_int32_t bnx_stats_ticks;
+
+ /* The address of the integrated PHY on the MII bus. */
+ int bnx_phy_addr;
+
+ /* The device handle for the MII bus child device. */
+ struct mii_data bnx_mii;
+
+ /* Driver maintained TX chain pointers and byte counter. */
+ u_int16_t rx_prod;
+ u_int16_t rx_cons;
+ u_int32_t rx_prod_bseq; /* Counts the bytes used. */
+ u_int16_t tx_prod;
+ u_int16_t tx_cons;
+ u_int32_t tx_prod_bseq; /* Counts the bytes used. */
+
+ struct callout bnx_timeout;
+
+ /* Frame size and mbuf allocation size for RX frames. */
+ u_int32_t max_frame_size;
+ int mbuf_alloc_size;
+
+ /* Receive mode settings (i.e promiscuous, multicast, etc.). */
+ u_int32_t rx_mode;
+
+ /* Bus tag for the bnx controller. */
+ bus_dma_tag_t bnx_dmatag;
+
+ /* H/W maintained TX buffer descriptor chain structure. */
+ bus_dma_segment_t tx_bd_chain_seg[TX_PAGES];
+ int tx_bd_chain_rseg[TX_PAGES];
+ bus_dmamap_t tx_bd_chain_map[TX_PAGES];
+ struct tx_bd *tx_bd_chain[TX_PAGES];
+ bus_addr_t tx_bd_chain_paddr[TX_PAGES];
+
+ /* H/W maintained RX buffer descriptor chain structure. */
+ bus_dma_segment_t rx_bd_chain_seg[RX_PAGES];
+ int rx_bd_chain_rseg[RX_PAGES];
+ bus_dmamap_t rx_bd_chain_map[RX_PAGES];
+ struct rx_bd *rx_bd_chain[RX_PAGES];
+ bus_addr_t rx_bd_chain_paddr[RX_PAGES];
+
+ /* H/W maintained status block. */
+ bus_dma_segment_t status_seg;
+ int status_rseg;
+ bus_dmamap_t status_map;
+ struct status_block *status_block; /* virtual address */
+ bus_addr_t status_block_paddr; /* Physical address */
+
+ /* H/W maintained context block */
+ int ctx_pages;
+ bus_dma_segment_t ctx_segs[4];
+ int ctx_rsegs[4];
+ bus_dmamap_t ctx_map[4];
+ void *ctx_block[4];
+
+ /* Driver maintained status block values. */
+ u_int16_t last_status_idx;
+ u_int16_t hw_rx_cons;
+ u_int16_t hw_tx_cons;
+
+ /* H/W maintained statistics block. */
+ bus_dma_segment_t stats_seg;
+ int stats_rseg;
+ bus_dmamap_t stats_map;
+ struct statistics_block *stats_block; /* Virtual address */
+ bus_addr_t stats_block_paddr; /* Physical address */
+
+ /* Bus tag for RX/TX mbufs. */
+ bus_dma_segment_t rx_mbuf_seg;
+ int rx_mbuf_rseg;
+ bus_dma_segment_t tx_mbuf_seg;
+ int tx_mbuf_rseg;
+
+ /* S/W maintained mbuf TX chain structure. */
+ kmutex_t tx_pkt_mtx;
+ u_int tx_pkt_count;
+ struct bnx_pkt_list tx_free_pkts;
+ struct bnx_pkt_list tx_used_pkts;
+
+ /* S/W maintained mbuf RX chain structure. */
+ bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
+ struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
+
+ /* Track the number of rx_bd and tx_bd's in use. */
+ u_int16_t free_rx_bd;
+ u_int16_t max_rx_bd;
+ u_int16_t used_tx_bd;
+ u_int16_t max_tx_bd;
+
+ /* Provides access to hardware statistics through sysctl. */
+ u_int64_t stat_IfHCInOctets;
+ u_int64_t stat_IfHCInBadOctets;
+ u_int64_t stat_IfHCOutOctets;
+ u_int64_t stat_IfHCOutBadOctets;
+ u_int64_t stat_IfHCInUcastPkts;
+ u_int64_t stat_IfHCInMulticastPkts;
+ u_int64_t stat_IfHCInBroadcastPkts;
+ u_int64_t stat_IfHCOutUcastPkts;
+ u_int64_t stat_IfHCOutMulticastPkts;
+ u_int64_t stat_IfHCOutBroadcastPkts;
+
+ u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
+ u_int32_t stat_Dot3StatsCarrierSenseErrors;
+ u_int32_t stat_Dot3StatsFCSErrors;
+ u_int32_t stat_Dot3StatsAlignmentErrors;
+ u_int32_t stat_Dot3StatsSingleCollisionFrames;
+ u_int32_t stat_Dot3StatsMultipleCollisionFrames;
+ u_int32_t stat_Dot3StatsDeferredTransmissions;
+ u_int32_t stat_Dot3StatsExcessiveCollisions;
+ u_int32_t stat_Dot3StatsLateCollisions;
+ u_int32_t stat_EtherStatsCollisions;
+ u_int32_t stat_EtherStatsFragments;
+ u_int32_t stat_EtherStatsJabbers;
+ u_int32_t stat_EtherStatsUndersizePkts;
+ u_int32_t stat_EtherStatsOverrsizePkts;
+ u_int32_t stat_EtherStatsPktsRx64Octets;
+ u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets;
+ u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets;
+ u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets;
+ u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
+ u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
+ u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
+ u_int32_t stat_EtherStatsPktsTx64Octets;
+ u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets;
+ u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets;
+ u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets;
+ u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
+ u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
+ u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
+ u_int32_t stat_XonPauseFramesReceived;
+ u_int32_t stat_XoffPauseFramesReceived;
+ u_int32_t stat_OutXonSent;
+ u_int32_t stat_OutXoffSent;
+ u_int32_t stat_FlowControlDone;
+ u_int32_t stat_MacControlFramesReceived;
+ u_int32_t stat_XoffStateEntered;
+ u_int32_t stat_IfInFramesL2FilterDiscards;
+ u_int32_t stat_IfInRuleCheckerDiscards;
+ u_int32_t stat_IfInFTQDiscards;
+ u_int32_t stat_IfInMBUFDiscards;
+ u_int32_t stat_IfInRuleCheckerP4Hit;
+ u_int32_t stat_CatchupInRuleCheckerDiscards;
+ u_int32_t stat_CatchupInFTQDiscards;
+ u_int32_t stat_CatchupInMBUFDiscards;
+ u_int32_t stat_CatchupInRuleCheckerP4Hit;
+
+ /* Mbuf allocation failure counter. */
+ u_int32_t mbuf_alloc_failed;
+
+ /* TX DMA mapping failure counter. */
+ u_int32_t tx_dma_map_failures;
+
+#ifdef BNX_DEBUG
+ /* Track the number of enqueued mbufs. */
+ int tx_mbuf_alloc;
+ int rx_mbuf_alloc;
+
+ /* Track the distribution buffer segments. */
+ u_int32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1];
+
+ /* Track how many and what type of interrupts are generated. */
+ u_int32_t interrupts_generated;
+ u_int32_t interrupts_handled;
+ u_int32_t rx_interrupts;
+ u_int32_t tx_interrupts;
+
+ u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */
+ u_int32_t rx_empty_count; /* Number of times the RX chain was empty. */
+ u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */
+ u_int32_t tx_full_count; /* Number of times the TX chain was full. */
+ u_int32_t mbuf_sim_alloc_failed;/* Mbuf simulated allocation failure counter. */
+ u_int32_t l2fhdr_status_errors;
+ u_int32_t unexpected_attentions;
+ u_int32_t lost_status_block_updates;
+#endif
+};
+
+struct bnx_firmware_header {
+ int bnx_COM_FwReleaseMajor;
+ int bnx_COM_FwReleaseMinor;
+ int bnx_COM_FwReleaseFix;
+ u_int32_t bnx_COM_FwStartAddr;
+ u_int32_t bnx_COM_FwTextAddr;
+ int bnx_COM_FwTextLen;
+ u_int32_t bnx_COM_FwDataAddr;
+ int bnx_COM_FwDataLen;
+ u_int32_t bnx_COM_FwRodataAddr;
+ int bnx_COM_FwRodataLen;
+ u_int32_t bnx_COM_FwBssAddr;
+ int bnx_COM_FwBssLen;
+ u_int32_t bnx_COM_FwSbssAddr;
+ int bnx_COM_FwSbssLen;
+
+ int bnx_RXP_FwReleaseMajor;
+ int bnx_RXP_FwReleaseMinor;
+ int bnx_RXP_FwReleaseFix;
+ u_int32_t bnx_RXP_FwStartAddr;
+ u_int32_t bnx_RXP_FwTextAddr;
+ int bnx_RXP_FwTextLen;
+ u_int32_t bnx_RXP_FwDataAddr;
+ int bnx_RXP_FwDataLen;
+ u_int32_t bnx_RXP_FwRodataAddr;
+ int bnx_RXP_FwRodataLen;
+ u_int32_t bnx_RXP_FwBssAddr;
+ int bnx_RXP_FwBssLen;
+ u_int32_t bnx_RXP_FwSbssAddr;
+ int bnx_RXP_FwSbssLen;
+
+ int bnx_TPAT_FwReleaseMajor;
+ int bnx_TPAT_FwReleaseMinor;
+ int bnx_TPAT_FwReleaseFix;
+ u_int32_t bnx_TPAT_FwStartAddr;
+ u_int32_t bnx_TPAT_FwTextAddr;
+ int bnx_TPAT_FwTextLen;
+ u_int32_t bnx_TPAT_FwDataAddr;
+ int bnx_TPAT_FwDataLen;
+ u_int32_t bnx_TPAT_FwRodataAddr;
+ int bnx_TPAT_FwRodataLen;
+ u_int32_t bnx_TPAT_FwBssAddr;
+ int bnx_TPAT_FwBssLen;
+ u_int32_t bnx_TPAT_FwSbssAddr;
+ int bnx_TPAT_FwSbssLen;
+
+ int bnx_TXP_FwReleaseMajor;
+ int bnx_TXP_FwReleaseMinor;
+ int bnx_TXP_FwReleaseFix;
+ u_int32_t bnx_TXP_FwStartAddr;
+ u_int32_t bnx_TXP_FwTextAddr;
+ int bnx_TXP_FwTextLen;
+ u_int32_t bnx_TXP_FwDataAddr;
+ int bnx_TXP_FwDataLen;
+ u_int32_t bnx_TXP_FwRodataAddr;
+ int bnx_TXP_FwRodataLen;
+ u_int32_t bnx_TXP_FwBssAddr;
+ int bnx_TXP_FwBssLen;
+ u_int32_t bnx_TXP_FwSbssAddr;
+ int bnx_TXP_FwSbssLen;
+
+ /* Followed by blocks of data, each sized according to
+ * the (rather obvious) block length stated above.
+ *
+ * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata,
+ * bnx_COM_FwBss, bnx_COM_FwSbss,
+ *
+ * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata,
+ * bnx_RXP_FwBss, bnx_RXP_FwSbss,
+ *
+ * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata,
+ * bnx_TPAT_FwBss, bnx_TPAT_FwSbss,
+ *
+ * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata,
+ * bnx_TXP_FwBss, bnx_TXP_FwSbss,
+ */
+};
+
+#endif /* _DEV_PCI_IF_BNXVAR_H_ */
+/* $NetBSD */
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jean-Yves Migeon <j...@netbsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $
+ */
+
+#ifndef _DEV_PCI_IF_BNXVAR_H_
+#define _DEV_PCI_IF_BNXVAR_H_
+
+#ifdef _KERNEL_OPT
+#include "bpfilter.h"
+#include "opt_inet.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/sysctl.h>
+//#include <sys/workqueue.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_ether.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_inarp.h>
+#endif
+
+#include <net/if_vlanvar.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+#include <dev/mii/brgphyreg.h>
+
+/*
+ * PCI registers defined in the PCI 2.2 spec.
+ */
+#define BNX_PCI_BAR0 0x10
+#define BNX_PCI_PCIX_CMD 0x40
+
+/****************************************************************************/
+/* Convenience definitions. */
+/****************************************************************************/
+#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
+#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
+#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
+#define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset)
+#define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val)
+#define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val)
+#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
+#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
+#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
+#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
+
+/****************************************************************************/
+/* BNX Device State Data Structure */
+/****************************************************************************/
+
+#define BNX_STATUS_BLK_SZ sizeof(struct status_block)
+#define BNX_STATS_BLK_SZ sizeof(struct statistics_block)
+#define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
+#define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
+
+struct bnx_pkt {
+ TAILQ_ENTRY(bnx_pkt) pkt_entry;
+ bus_dmamap_t pkt_dmamap;
+ struct mbuf *pkt_mbuf;
+ u_int16_t pkt_end_desc;
+};
+
+TAILQ_HEAD(bnx_pkt_list, bnx_pkt);
+
+struct bnx_softc
+{
+ device_t bnx_dev;
+ struct ethercom bnx_ec;
+ struct pci_attach_args bnx_pa;
+
+ struct ifmedia bnx_ifmedia; /* TBI media info */
+
+ bus_space_tag_t bnx_btag; /* Device bus tag */
+ bus_space_handle_t bnx_bhandle; /* Device bus handle */
+ bus_size_t bnx_size;
+
+ void *bnx_intrhand; /* Interrupt handler */
+
+ /* ASIC Chip ID. */
+ u_int32_t bnx_chipid;
+
+ /* General controller flags. */
+ u_int32_t bnx_flags;
+
+ /* PHY specific flags. */
+ u_int32_t bnx_phy_flags;
+
+ /* Values that need to be shared with the PHY driver. */
+ u_int32_t bnx_shared_hw_cfg;
+ u_int32_t bnx_port_hw_cfg;
+
+ u_int16_t bus_speed_mhz; /* PCI bus speed */
+ struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */
+ u_int32_t bnx_flash_size; /* Flash NVRAM size */
+ u_int32_t bnx_shmem_base; /* Shared Memory base address */
+ char * bnx_name; /* Name string */
+
+ /* Tracks the version of bootcode firmware. */
+ u_int32_t bnx_fw_ver;
+
+ /* Tracks the state of the firmware. 0 = Running while any */
+ /* other value indicates that the firmware is not responding. */
+ u_int16_t bnx_fw_timed_out;
+
+ /* An incrementing sequence used to coordinate messages passed */
+ /* from the driver to the firmware. */
+ u_int16_t bnx_fw_wr_seq;
+
+ /* An incrementing sequence used to let the firmware know that */
+ /* the driver is still operating. Without the pulse, management */
+ /* firmware such as IPMI or UMP will operate in OS absent state. */
+ u_int16_t bnx_fw_drv_pulse_wr_seq;
+
+ /* Ethernet MAC address. */
+ u_char eaddr[6];
+
+ /* These setting are used by the host coalescing (HC) block to */
+ /* to control how often the status block, statistics block and */
+ /* interrupts are generated. */
+ u_int16_t bnx_tx_quick_cons_trip_int;
+ u_int16_t bnx_tx_quick_cons_trip;
+ u_int16_t bnx_rx_quick_cons_trip_int;
+ u_int16_t bnx_rx_quick_cons_trip;
+ u_int16_t bnx_comp_prod_trip_int;
+ u_int16_t bnx_comp_prod_trip;
+ u_int16_t bnx_tx_ticks_int;
+ u_int16_t bnx_tx_ticks;
+ u_int16_t bnx_rx_ticks_int;
+ u_int16_t bnx_rx_ticks;
+ u_int16_t bnx_com_ticks_int;
+ u_int16_t bnx_com_ticks;
+ u_int16_t bnx_cmd_ticks_int;
+ u_int16_t bnx_cmd_ticks;
+ u_int32_t bnx_stats_ticks;
+
+ /* The address of the integrated PHY on the MII bus. */
+ int bnx_phy_addr;
+
+ /* The device handle for the MII bus child device. */
+ struct mii_data bnx_mii;
+
+ /* Driver maintained TX chain pointers and byte counter. */
+ u_int16_t rx_prod;
+ u_int16_t rx_cons;
+ u_int32_t rx_prod_bseq; /* Counts the bytes used. */
+ u_int16_t tx_prod;
+ u_int16_t tx_cons;
+ u_int32_t tx_prod_bseq; /* Counts the bytes used. */
+
+ struct callout bnx_timeout;
+
+ /* Frame size and mbuf allocation size for RX frames. */
+ u_int32_t max_frame_size;
+ int mbuf_alloc_size;
+
+ /* Receive mode settings (i.e promiscuous, multicast, etc.). */
+ u_int32_t rx_mode;
+
+ /* Bus tag for the bnx controller. */
+ bus_dma_tag_t bnx_dmatag;
+
+ /* H/W maintained TX buffer descriptor chain structure. */
+ bus_dma_segment_t tx_bd_chain_seg[TX_PAGES];
+ int tx_bd_chain_rseg[TX_PAGES];
+ bus_dmamap_t tx_bd_chain_map[TX_PAGES];
+ struct tx_bd *tx_bd_chain[TX_PAGES];
+ bus_addr_t tx_bd_chain_paddr[TX_PAGES];
+
+ /* H/W maintained RX buffer descriptor chain structure. */
+ bus_dma_segment_t rx_bd_chain_seg[RX_PAGES];
+ int rx_bd_chain_rseg[RX_PAGES];
+ bus_dmamap_t rx_bd_chain_map[RX_PAGES];
+ struct rx_bd *rx_bd_chain[RX_PAGES];
+ bus_addr_t rx_bd_chain_paddr[RX_PAGES];
+
+ /* H/W maintained status block. */
+ bus_dma_segment_t status_seg;
+ int status_rseg;
+ bus_dmamap_t status_map;
+ struct status_block *status_block; /* virtual address */
+ bus_addr_t status_block_paddr; /* Physical address */
+
+ /* H/W maintained context block */
+ int ctx_pages;
+ bus_dma_segment_t ctx_segs[4];
+ int ctx_rsegs[4];
+ bus_dmamap_t ctx_map[4];
+ void *ctx_block[4];
+
+ /* Driver maintained status block values. */
+ u_int16_t last_status_idx;
+ u_int16_t hw_rx_cons;
+ u_int16_t hw_tx_cons;
+
+ /* H/W maintained statistics block. */
+ bus_dma_segment_t stats_seg;
+ int stats_rseg;
+ bus_dmamap_t stats_map;
+ struct statistics_block *stats_block; /* Virtual address */
+ bus_addr_t stats_block_paddr; /* Physical address */
+
+ /* Bus tag for RX/TX mbufs. */
+ bus_dma_segment_t rx_mbuf_seg;
+ int rx_mbuf_rseg;
+ bus_dma_segment_t tx_mbuf_seg;
+ int tx_mbuf_rseg;
+
+ /* S/W maintained mbuf TX chain structure. */
+ kmutex_t tx_pkt_mtx;
+ u_int tx_pkt_count;
+ struct bnx_pkt_list tx_free_pkts;
+ struct bnx_pkt_list tx_used_pkts;
+
+ /* S/W maintained mbuf RX chain structure. */
+ bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
+ struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
+
+ /* Track the number of rx_bd and tx_bd's in use. */
+ u_int16_t free_rx_bd;
+ u_int16_t max_rx_bd;
+ u_int16_t used_tx_bd;
+ u_int16_t max_tx_bd;
+
+ /* Provides access to hardware statistics through sysctl. */
+ u_int64_t stat_IfHCInOctets;
+ u_int64_t stat_IfHCInBadOctets;
+ u_int64_t stat_IfHCOutOctets;
+ u_int64_t stat_IfHCOutBadOctets;
+ u_int64_t stat_IfHCInUcastPkts;
+ u_int64_t stat_IfHCInMulticastPkts;
+ u_int64_t stat_IfHCInBroadcastPkts;
+ u_int64_t stat_IfHCOutUcastPkts;
+ u_int64_t stat_IfHCOutMulticastPkts;
+ u_int64_t stat_IfHCOutBroadcastPkts;
+
+ u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
+ u_int32_t stat_Dot3StatsCarrierSenseErrors;
+ u_int32_t stat_Dot3StatsFCSErrors;
+ u_int32_t stat_Dot3StatsAlignmentErrors;
+ u_int32_t stat_Dot3StatsSingleCollisionFrames;
+ u_int32_t stat_Dot3StatsMultipleCollisionFrames;
+ u_int32_t stat_Dot3StatsDeferredTransmissions;
+ u_int32_t stat_Dot3StatsExcessiveCollisions;
+ u_int32_t stat_Dot3StatsLateCollisions;
+ u_int32_t stat_EtherStatsCollisions;
+ u_int32_t stat_EtherStatsFragments;
+ u_int32_t stat_EtherStatsJabbers;
+ u_int32_t stat_EtherStatsUndersizePkts;
+ u_int32_t stat_EtherStatsOverrsizePkts;
+ u_int32_t stat_EtherStatsPktsRx64Octets;
+ u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets;
+ u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets;
+ u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets;
+ u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
+ u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
+ u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
+ u_int32_t stat_EtherStatsPktsTx64Octets;
+ u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets;
+ u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets;
+ u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets;
+ u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
+ u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
+ u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
+ u_int32_t stat_XonPauseFramesReceived;
+ u_int32_t stat_XoffPauseFramesReceived;
+ u_int32_t stat_OutXonSent;
+ u_int32_t stat_OutXoffSent;
+ u_int32_t stat_FlowControlDone;
+ u_int32_t stat_MacControlFramesReceived;
+ u_int32_t stat_XoffStateEntered;
+ u_int32_t stat_IfInFramesL2FilterDiscards;
+ u_int32_t stat_IfInRuleCheckerDiscards;
+ u_int32_t stat_IfInFTQDiscards;
+ u_int32_t stat_IfInMBUFDiscards;
+ u_int32_t stat_IfInRuleCheckerP4Hit;
+ u_int32_t stat_CatchupInRuleCheckerDiscards;
+ u_int32_t stat_CatchupInFTQDiscards;
+ u_int32_t stat_CatchupInMBUFDiscards;
+ u_int32_t stat_CatchupInRuleCheckerP4Hit;
+
+ /* Mbuf allocation failure counter. */
+ u_int32_t mbuf_alloc_failed;
+
+ /* TX DMA mapping failure counter. */
+ u_int32_t tx_dma_map_failures;
+
+#ifdef BNX_DEBUG
+ /* Track the number of enqueued mbufs. */
+ int tx_mbuf_alloc;
+ int rx_mbuf_alloc;
+
+ /* Track the distribution buffer segments. */
+ u_int32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1];
+
+ /* Track how many and what type of interrupts are generated. */
+ u_int32_t interrupts_generated;
+ u_int32_t interrupts_handled;
+ u_int32_t rx_interrupts;
+ u_int32_t tx_interrupts;
+
+ u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */
+ u_int32_t rx_empty_count; /* Number of times the RX chain was empty. */
+ u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */
+ u_int32_t tx_full_count; /* Number of times the TX chain was full. */
+ u_int32_t mbuf_sim_alloc_failed;/* Mbuf simulated allocation failure counter. */
+ u_int32_t l2fhdr_status_errors;
+ u_int32_t unexpected_attentions;
+ u_int32_t lost_status_block_updates;
+#endif
+};
+
+struct bnx_firmware_header {
+ int bnx_COM_FwReleaseMajor;
+ int bnx_COM_FwReleaseMinor;
+ int bnx_COM_FwReleaseFix;
+ u_int32_t bnx_COM_FwStartAddr;
+ u_int32_t bnx_COM_FwTextAddr;
+ int bnx_COM_FwTextLen;
+ u_int32_t bnx_COM_FwDataAddr;
+ int bnx_COM_FwDataLen;
+ u_int32_t bnx_COM_FwRodataAddr;
+ int bnx_COM_FwRodataLen;
+ u_int32_t bnx_COM_FwBssAddr;
+ int bnx_COM_FwBssLen;
+ u_int32_t bnx_COM_FwSbssAddr;
+ int bnx_COM_FwSbssLen;
+
+ int bnx_RXP_FwReleaseMajor;
+ int bnx_RXP_FwReleaseMinor;
+ int bnx_RXP_FwReleaseFix;
+ u_int32_t bnx_RXP_FwStartAddr;
+ u_int32_t bnx_RXP_FwTextAddr;
+ int bnx_RXP_FwTextLen;
+ u_int32_t bnx_RXP_FwDataAddr;
+ int bnx_RXP_FwDataLen;
+ u_int32_t bnx_RXP_FwRodataAddr;
+ int bnx_RXP_FwRodataLen;
+ u_int32_t bnx_RXP_FwBssAddr;
+ int bnx_RXP_FwBssLen;
+ u_int32_t bnx_RXP_FwSbssAddr;
+ int bnx_RXP_FwSbssLen;
+
+ int bnx_TPAT_FwReleaseMajor;
+ int bnx_TPAT_FwReleaseMinor;
+ int bnx_TPAT_FwReleaseFix;
+ u_int32_t bnx_TPAT_FwStartAddr;
+ u_int32_t bnx_TPAT_FwTextAddr;
+ int bnx_TPAT_FwTextLen;
+ u_int32_t bnx_TPAT_FwDataAddr;
+ int bnx_TPAT_FwDataLen;
+ u_int32_t bnx_TPAT_FwRodataAddr;
+ int bnx_TPAT_FwRodataLen;
+ u_int32_t bnx_TPAT_FwBssAddr;
+ int bnx_TPAT_FwBssLen;
+ u_int32_t bnx_TPAT_FwSbssAddr;
+ int bnx_TPAT_FwSbssLen;
+
+ int bnx_TXP_FwReleaseMajor;
+ int bnx_TXP_FwReleaseMinor;
+ int bnx_TXP_FwReleaseFix;
+ u_int32_t bnx_TXP_FwStartAddr;
+ u_int32_t bnx_TXP_FwTextAddr;
+ int bnx_TXP_FwTextLen;
+ u_int32_t bnx_TXP_FwDataAddr;
+ int bnx_TXP_FwDataLen;
+ u_int32_t bnx_TXP_FwRodataAddr;
+ int bnx_TXP_FwRodataLen;
+ u_int32_t bnx_TXP_FwBssAddr;
+ int bnx_TXP_FwBssLen;
+ u_int32_t bnx_TXP_FwSbssAddr;
+ int bnx_TXP_FwSbssLen;
+
+ /* Followed by blocks of data, each sized according to
+ * the (rather obvious) block length stated above.
+ *
+ * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata,
+ * bnx_COM_FwBss, bnx_COM_FwSbss,
+ *
+ * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata,
+ * bnx_RXP_FwBss, bnx_RXP_FwSbss,
+ *
+ * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata,
+ * bnx_TPAT_FwBss, bnx_TPAT_FwSbss,
+ *
+ * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata,
+ * bnx_TXP_FwBss, bnx_TXP_FwSbss,
+ */
+};
+
+#endif /* _DEV_PCI_IF_BNXVAR_H_ */
