Module Name: src
Committed By: msaitoh
Date: Tue Nov 17 18:26:50 UTC 2015
Modified Files:
src/sys/dev/pci: pci_subr.c pcireg.h
Log Message:
- ARI's function group is not bit 32-24 but 22-20.
- Add the Structure Length field in AF capability register.
- Add Enhanced Allocation extended capability ID (ECN: Enhanced Allocation (EA)
for Memory and I/O Resources).
- Add LN System CLS (ECN: Lightweight Notification (LN) Protocol).
- Add ST Upper and Lower bit definitions (ECN: TLP Processiong Hints).
- Add the Global Invalidate bit in the ATS capability register and the PRG
Response PASID Required bit in the Page Request status register (ECN: PASID
Translation)
- Decode ASPM support bit more (ECN: ASPM Optionally)
- Use __BITS()
To generate a diff of this commit:
cvs rdiff -u -r1.144 -r1.145 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.110 -r1.111 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.144 src/sys/dev/pci/pci_subr.c:1.145
--- src/sys/dev/pci/pci_subr.c:1.144 Tue Nov 17 17:51:42 2015
+++ src/sys/dev/pci/pci_subr.c Tue Nov 17 18:26:50 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.144 2015/11/17 17:51:42 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.145 2015/11/17 18:26:50 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.144 2015/11/17 17:51:42 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.145 2015/11/17 18:26:50 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -1584,15 +1584,18 @@ pci_conf_print_pcie_cap(const pcireg_t *
printf(" Active State PM Support: ");
val = (reg & PCIE_LCAP_ASPM) >> 10;
switch (val) {
+ case 0x0:
+ printf("No ASPM support\n");
+ break;
case 0x1:
- printf("L0s Entry supported\n");
+ printf("L0s supported\n");
+ break;
+ case 0x2:
+ printf("L1 supported\n");
break;
case 0x3:
printf("L0s and L1 supported\n");
break;
- default:
- printf("Reserved value\n");
- break;
}
printf(" L0 Exit Latency: ");
pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12);
@@ -1792,6 +1795,21 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC);
printf(" TPH Completer Supported: %u\n",
(unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12);
+ printf(" LN System CLS: ");
+ switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) {
+ case 0x0:
+ printf("Not supported or not in effect\n");
+ break;
+ case 0x1:
+ printf("64byte cachelines in effect\n");
+ break;
+ case 0x2:
+ printf("128byte cachelines in effect\n");
+ break;
+ case 0x3:
+ printf("Reserved\n");
+ break;
+ }
printf(" OBFF Supported: ");
switch ((reg & PCIE_DCAP2_OBFF) >> 18) {
case 0x0:
@@ -1907,13 +1925,14 @@ pci_conf_print_msix_cap(const pcireg_t *
onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);
reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];
printf(" Table offset register: 0x%08x\n", reg);
- printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK);
- printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK);
+ printf(" Table offset: %08x\n",
+ (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK));
+ printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK));
reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)];
printf(" Pending bit array register: 0x%08x\n", reg);
printf(" Pending bit array offset: %08x\n",
- reg & PCI_MSIX_PBAOFFSET_MASK);
- printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK);
+ (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK));
+ printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK));
}
static void
@@ -1951,6 +1970,8 @@ pci_conf_print_pciaf_cap(const pcireg_t
reg = regs[o2i(capoff + PCI_AFCAPR)];
printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff);
+ printf(" AF Structure Length: 0x%02x\n",
+ (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH));
onoff("Transaction Pending", reg, PCI_AF_TP_CAP);
onoff("Function Level Reset", reg, PCI_AF_FLR_CAP);
reg = regs[o2i(capoff + PCI_AFCSR)];
@@ -1989,7 +2010,8 @@ static struct {
{ PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap },
{ PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
{ PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap },
- { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap }
+ { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap},
+ { PCI_CAP_EA, "Enhanced Allocation", NULL }
};
static int
@@ -2674,6 +2696,7 @@ pci_conf_print_ats_cap(const pcireg_t *r
num = 32;
printf(" Invalidate Queue Depth: %u\n", num);
onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ);
+ onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL);
printf(" Control register: 0x%04x\n", ctl);
printf(" Smallest Translation Unit: %u\n",
@@ -2889,6 +2912,7 @@ pci_conf_print_page_req_cap(const pcireg
onoff("Unexpected Page Request Group Index", reg,
PCI_PAGE_REQ_STA_UPRGI);
onoff("Stopped", reg, PCI_PAGE_REQ_STA_S);
+ onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR);
reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)];
printf(" Outstanding Page Request Capacity: %u\n", reg);
@@ -2897,7 +2921,7 @@ pci_conf_print_page_req_cap(const pcireg
}
/* XXX pci_conf_print_amd_cap */
-/* XXX pci_conf_print_resize_bar_cap */
+/* XXX pci_conf_print_resiz_bar_cap */
/* XXX pci_conf_print_dpa_cap */
static const char *
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.110 src/sys/dev/pci/pcireg.h:1.111
--- src/sys/dev/pci/pcireg.h:1.110 Tue Nov 17 17:51:42 2015
+++ src/sys/dev/pci/pcireg.h Tue Nov 17 18:26:50 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.110 2015/11/17 17:51:42 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.111 2015/11/17 18:26:50 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -539,6 +539,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_CAP_MSIX 0x11
#define PCI_CAP_SATA 0x12
#define PCI_CAP_PCIAF 0x13
+#define PCI_CAP_EA 0x14 /* Enhanced Allocation (EA) */
/*
* Capability ID: 0x01
@@ -1006,6 +1007,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */
#define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */
#define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */
+#define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */
#define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/
#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
@@ -1059,14 +1061,14 @@ typedef u_int8_t pci_revision_t;
* 2nd DWORD is the Table Offset
*/
#define PCI_MSIX_TBLOFFSET 0x04
-#define PCI_MSIX_TBLOFFSET_MASK 0xfffffff8
-#define PCI_MSIX_TBLBIR_MASK 0x00000007
+#define PCI_MSIX_TBLOFFSET_MASK __BITS(31, 3)
+#define PCI_MSIX_TBLBIR_MASK __BITS(2, 0)
/*
* 3rd DWORD is the Pending Bitmap Array Offset
*/
#define PCI_MSIX_PBAOFFSET 0x08
-#define PCI_MSIX_PBAOFFSET_MASK 0xfffffff8
-#define PCI_MSIX_PBABIR_MASK 0x00000007
+#define PCI_MSIX_PBAOFFSET_MASK __BITS(31, 3)
+#define PCI_MSIX_PBABIR_MASK __BITS(2, 0)
#define PCI_MSIX_TABLE_ENTRY_SIZE 16
#define PCI_MSIX_TABLE_ENTRY_ADDR_LO 0x0
@@ -1080,6 +1082,8 @@ struct pci_msix_table_entry {
uint32_t pci_msix_vector_control;
};
#define PCI_MSIX_VECTCTL_MASK __BIT(0)
+#define PCI_MSIX_VECTCTL_STLO __BITS(23, 16)
+#define PCI_MSIX_VECTCTL_STUP __BITS(31, 24)
/* Max number of MSI-X vectors. See PCI-SIG specification. */
#define PCI_MSIX_MAX_VECTORS 2048
@@ -1103,6 +1107,7 @@ struct pci_msix_table_entry {
*/
#define PCI_AFCAPR 0x00 /* Capabilities */
#define PCI_AFCAPR_MASK __BITS(31, 24)
+#define PCI_AF_LENGTH __BITS(23, 16) /* Structure Length */
#define PCI_AF_TP_CAP __BIT(24) /* Transaction Pending */
#define PCI_AF_FLR_CAP __BIT(25) /* Function Level Reset */
#define PCI_AFCSR 0x04 /* Control & Status register */
@@ -1646,7 +1651,7 @@ struct pci_rom {
#define PCI_ARI_CTL 0x04 /* Control Register */
#define PCI_ARI_CTL_M __BIT(16) /* MFVC Function Groups Ena. */
#define PCI_ARI_CTL_A __BIT(17) /* ACS Function Groups Ena. */
-#define PCI_ARI_CTL_FUNCGRP __BITS(31, 24) /* Function Group */
+#define PCI_ARI_CTL_FUNCGRP __BITS(22, 20) /* Function Group */
/*
* Extended capability ID: 0x000f
@@ -1655,6 +1660,7 @@ struct pci_rom {
#define PCI_ATS_CAP 0x04 /* Capability Register */
#define PCI_ATS_CAP_INVQDEPTH __BITS(4, 0) /* Invalidate Queue Depth */
#define PCI_ATS_CAP_PALIGNREQ __BIT(5) /* Page Aligned Request */
+#define PCI_ATS_CAP_GLOBALINVL __BIT(6) /* Global Invalidate Support */
#define PCI_ATS_CTL 0x04 /* Control Register */
#define PCI_ATS_CTL_STU __BITS(20, 16) /* Smallest Translation Unit */
#define PCI_ATS_CTL_EN __BIT(31) /* Enable */
@@ -1739,6 +1745,7 @@ struct pci_rom {
#define PCI_PAGE_REQ_STA_RF __BIT(0+16) /* Response Failure */
#define PCI_PAGE_REQ_STA_UPRGI __BIT(1+16) /* Unexpected Page Req Grp Idx */
#define PCI_PAGE_REQ_STA_S __BIT(8+16) /* Stopped */
+#define PCI_PAGE_REQ_STA_PASIDR __BIT(15+16) /* PRG Response PASID Required */
#define PCI_PAGE_REQ_OUTSTCAPA 0x08 /* Outstanding Page Request Capacity */
#define PCI_PAGE_REQ_OUTSTALLOC 0x0c /* Outstanding Page Request Allocation */
