Module Name: src
Committed By: marty
Date: Thu Nov 26 21:27:31 UTC 2015
Modified Files:
src/sys/arch/evbarm/odroid: odroid_machdep.c odroid_start.S platform.h
Log Message:
Revert my previous change -- it breaks other odroid devices
To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/evbarm/odroid/odroid_machdep.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbarm/odroid/odroid_start.S
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbarm/odroid/platform.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/odroid/odroid_machdep.c
diff -u src/sys/arch/evbarm/odroid/odroid_machdep.c:1.40 src/sys/arch/evbarm/odroid/odroid_machdep.c:1.41
--- src/sys/arch/evbarm/odroid/odroid_machdep.c:1.40 Wed Nov 25 04:04:13 2015
+++ src/sys/arch/evbarm/odroid/odroid_machdep.c Thu Nov 26 21:27:31 2015
@@ -1,4 +1,8 @@
-/* $NetBSD: odroid_machdep.c,v 1.40 2015/11/25 04:04:13 marty Exp $ */
+<<<<<<< odroid_machdep.c
+/* $NetBSD: odroid_machdep.c,v 1.41 2015/11/26 21:27:31 marty Exp $ */
+=======
+/* $NetBSD: odroid_machdep.c,v 1.41 2015/11/26 21:27:31 marty Exp $ */
+>>>>>>> 1.7
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +35,11 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.40 2015/11/25 04:04:13 marty Exp $");
+<<<<<<< odroid_machdep.c
+__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.41 2015/11/26 21:27:31 marty Exp $");
+=======
+__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.41 2015/11/26 21:27:31 marty Exp $");
+>>>>>>> 1.7
#include "opt_evbarm_boardtype.h"
#include "opt_exynos.h"
@@ -128,6 +136,10 @@ extern const struct sscom_uart_info exyn
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB | HUPCL)) | CS8) /* 8N1 */
#endif /* CONMODE */
+// __CTASSERT(EXYNOS_CORE_PBASE + EXYNOS_UART0_OFFSET <= CONADDR);
+// __CTASSERT(CONADDR <= EXYNOS_CORE_PBASE + EXYNOS_UART4_OFFSET);
+// __CTASSERT(CONADDR % EXYNOS_BLOCK_SIZE == 0);
+//static const bus_addr_t conaddr = CONADDR;
static const int conspeed = CONSPEED;
static const int conmode = CONMODE;
#endif /*defined(KGDB) || defined(SSCOM*CONSOLE) */
@@ -148,7 +160,7 @@ uintptr_t uboot_args[4] = { 0 };
* argument and boot configure storage
*/
BootConfig bootconfig; /* for pmap's sake */
-char bootargs[MAX_BOOT_STRING]; /* copied string from uboot */
+char bootargs[MAX_BOOT_STRING] = ""; /* copied string from uboot */
char *boot_args = NULL; /* MI bootargs */
char *boot_file = NULL; /* MI bootfile */
uint8_t uboot_enaddr[ETHER_ADDR_LEN] = {};
@@ -177,9 +189,6 @@ static void exynos_usb_powercycle_lan973
static void exynos_extract_mac_adress(void);
void odroid_device_register(device_t self, void *aux);
void odroid_device_register_post_config(device_t self, void *aux);
-#ifdef MULTIPROCESSOR
-extern void exynos_cpu_hatch(struct cpu_info *ci);
-#endif
/*
@@ -237,21 +246,12 @@ static const struct pmap_devmap e5_devma
#ifdef PMAP_NEED_ALLOC_POOLPAGE
static struct boot_physmem bp_highgig = {
- .bp_start = EXYNOS5_SDRAM_PBASE / NBPG,
.bp_pages = (KERNEL_VM_BASE - KERNEL_BASE) / NBPG,
- .bp_freelist = VM_FREELIST_DEFAULT,
+ .bp_freelist = VM_FREELIST_ISADMA,
.bp_flags = 0,
};
#endif
-#ifdef MULTIPROCESSOR
-void
-exynos_cpu_hatch(struct cpu_info *ci)
-{
- /* MJF: WRITE ME */
-}
-#endif
-
/*
* u_int initarm(...)
*
@@ -260,7 +260,6 @@ exynos_cpu_hatch(struct cpu_info *ci)
* - init the physical console
* - setting up page tables for the kernel
*/
-extern void xputc(int);
u_int
initarm(void *arg)
@@ -270,7 +269,6 @@ initarm(void *arg)
const psize_t ram_reserve = 0x200000;
psize_t ram_size;
-#if 0
/* allocate/map our basic memory mapping */
switch (EXYNOS_PRODUCT_FAMILY(exynos_soc_id)) {
#if defined(EXYNOS4)
@@ -290,24 +288,12 @@ initarm(void *arg)
panic("Unknown product family %llx",
EXYNOS_PRODUCT_FAMILY(exynos_soc_id));
}
-#else
- devmap = e5_devmap;
- rambase = EXYNOS5_SDRAM_PBASE;
-#endif
- xputc('<');
pmap_devmap_register(devmap);
- xputc('>');
-#if 0
/* bootstrap soc. uart_address is determined in odroid_start */
paddr_t uart_address = armreg_tpidruro_read();
exynos_bootstrap(EXYNOS_CORE_VBASE, EXYNOS_IOPHYSTOVIRT(uart_address));
-#else
- xputc('[');
- exynos_bootstrap(EXYNOS_CORE_VBASE,
- EXYNOS_CORE_VBASE + EXYNOS5_UART2_OFFSET);
- xputc(']');
-#endif
+
/* set up CPU / MMU / TLB functions */
if (set_cpufuncs())
panic("cpu not recognized!");
@@ -323,6 +309,7 @@ initarm(void *arg)
printf("\nuboot arg = %#"PRIxPTR", %#"PRIxPTR", %#"PRIxPTR", %#"PRIxPTR"\n",
uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]);
printf("Exynos SoC ID %08x\n", exynos_soc_id);
+
printf("initarm: cbar=%#x\n", armreg_cbar_read());
#endif
@@ -437,19 +424,21 @@ consinit(void)
consinit_called = true;
#if NSSCOM > 0
- bus_space_tag_t bst = &exynos_bs_tag;
bus_addr_t iobase = armreg_tpidruro_read();
+<<<<<<< odroid_machdep.c
+ bus_space_handle_t bsh = EXYNOS_IOPHYSTOVIRT(iobase);
u_int i;
-
/*
* No need to guess at the UART frequency since we can calculate it.
*/
- bus_space_handle_t bsh = EXYNOS_IOPHYSTOVIRT(iobase);
- uint32_t br0 = bus_space_read_4(bst, bsh, SSCOM_UBRDIV);
- uint32_t br1 = bus_space_read_4(bst, bsh, SSCOM_UFRACVAL);
- uint32_t freq = conspeed * (16 * (br0 + 1) + br1);
+ uint32_t freq = conspeed
+ * (16 * (bus_space_read_4(bst, bsh, SSCOM_UBRDIV) + 1)
+ + bus_space_read_4(bst, bsh, SSCOM_UFRACVAL));
freq = (freq + conspeed / 2) / 1000;
freq *= 1000;
+=======
+ size_t i;
+>>>>>>> 1.7
/* go trough all entries */
for (i = 0; i < num_exynos_uarts_entries; i++) {
@@ -457,16 +446,20 @@ consinit(void)
if (exynos_uarts[i].iobase + EXYNOS_CORE_PBASE == iobase)
break;
}
+<<<<<<< odroid_machdep.c
KASSERT(i < num_exynos_uarts_entries);
-
+ printf("%s: attaching console @ %#"PRIxPTR" (%u HZ, %u bps)\n",
+ __func__, iobase, freq, conspeed);
if (sscom_cnattach(bst, exynos_core_bsh, &exynos_uarts[i],
conspeed, freq, conmode))
+=======
+ KASSERT(i < __arraycount(exynos_uarts));
+
+ if (sscom_cnattach(&exynos_bs_tag, exynos_core_bsh,
+ &exynos_uarts[i], conspeed, EXYNOS_UART_FREQ,
+ conmode))
+>>>>>>> 1.7
panic("Serial console can not be initialized");
- printf("%s: attached console @ %#"PRIxPTR" (%u HZ, %u bps)\n",
- __func__, iobase, freq, conspeed);
-#ifdef VERBOSE_INIT_ARM
- printf("Console initialized\n");
-#endif
#else
#error only serial console is supported
#if NUKBD > 0
Index: src/sys/arch/evbarm/odroid/odroid_start.S
diff -u src/sys/arch/evbarm/odroid/odroid_start.S:1.8 src/sys/arch/evbarm/odroid/odroid_start.S:1.9
--- src/sys/arch/evbarm/odroid/odroid_start.S:1.8 Wed Nov 25 04:04:13 2015
+++ src/sys/arch/evbarm/odroid/odroid_start.S Thu Nov 26 21:27:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: odroid_start.S,v 1.8 2015/11/25 04:04:13 marty Exp $ */
+/* $NetBSD: odroid_start.S,v 1.9 2015/11/26 21:27:31 marty Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,7 +46,7 @@
#include <evbarm/odroid/platform.h>
-RCSID("$NetBSD: odroid_start.S,v 1.8 2015/11/25 04:04:13 marty Exp $")
+RCSID("$NetBSD: odroid_start.S,v 1.9 2015/11/26 21:27:31 marty Exp $")
#if defined(VERBOSE_INIT_ARM)
@@ -90,9 +90,9 @@ _C_LABEL(odroid_start):
cpsid if, #PSR_SVC32_MODE
/*
- * Save any arguments passed to us. If .start is not at
- * 0x80000000 but .text is, we can't directly use the address that
- * the linker gave us. Convert the virtual address to the
+ * Save any arguments passed to us. But since .start is not at
+ * 0x80000000 * but .text is, we can't directly use the address that
+ * the linker gave us directly. Convert the virtual address to the
* physical address by using KERNEL_BASE_VOFFSET.
*/
movw r4, #:lower16:uboot_args
@@ -112,9 +112,7 @@ _C_LABEL(odroid_start):
movw r4, #:lower16:exynos_soc_id
movt r4, #:upper16:exynos_soc_id
-#if KERNEL_BASE_VOFFSET != 0
sub r4, r4, #KERNEL_BASE_VOFFSET
-#endif
str r0, [r4] // save soc_id
mov r5, r0 // save soc_id
@@ -154,7 +152,7 @@ _C_LABEL(odroid_start):
*/
bl cortex_init
- XPUTC(#'@')
+ XPUTC(#'C')
/*
* Set up a preliminary mapping in the MMU to allow us to run
@@ -188,7 +186,6 @@ _C_LABEL(odroid_start):
XPUTC2(#'Z')
#if defined(MULTIPROCESSOR)
- /* MJF: HA HA (There's no there here) */
#endif /* MULTIPROCESSOR */
XPUTC2(#13) /* CR */
@@ -211,23 +208,23 @@ _C_LABEL(num_exynos_uarts_entries):
.global _C_LABEL(exynos_uarts)
_C_LABEL(exynos_uarts):
.Lsscom_exynos4_table:
- .word 0
+ .word 0
.word EXYNOS4_UART0_OFFSET
- .word 1
+ .word 1
.word EXYNOS4_UART1_OFFSET
- .word 2
+ .word 2
.word EXYNOS4_UART2_OFFSET
- .word 3
+ .word 3
.word EXYNOS4_UART3_OFFSET
.Lsscom_exynos5_table:
- .word 0
+ .word 0
.word EXYNOS5_UART0_OFFSET
- .word 1
+ .word 1
.word EXYNOS5_UART1_OFFSET
- .word 2
+ .word 2
.word EXYNOS5_UART2_OFFSET
- .word 3
+ .word 3
.word EXYNOS5_UART3_OFFSET
@@ -271,7 +268,7 @@ xputc:
bx lr
#endif
-#include <arm/cortex/cortex_init.S>
+#include <arm/cortex/a9_mpsubr.S>
#if EXYNOS_CORE_SIZE < EXYNOS4_CORE_SIZE
#error EXYNOS_CORE_SIZE smaller than EXYNOS4_CORE_SIZE
@@ -298,6 +295,7 @@ xputc:
EXYNOS_CORE_SIZE / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+ /* Map EXYNOS CORE (so console will work) */
MMU_INIT(EXYNOS_CORE_PBASE, EXYNOS_CORE_PBASE,
EXYNOS_CORE_SIZE / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
Index: src/sys/arch/evbarm/odroid/platform.h
diff -u src/sys/arch/evbarm/odroid/platform.h:1.4 src/sys/arch/evbarm/odroid/platform.h:1.5
--- src/sys/arch/evbarm/odroid/platform.h:1.4 Wed Nov 25 04:04:13 2015
+++ src/sys/arch/evbarm/odroid/platform.h Thu Nov 26 21:27:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: platform.h,v 1.4 2015/11/25 04:04:13 marty Exp $ */
+/* $NetBSD: platform.h,v 1.5 2015/11/26 21:27:31 marty Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,20 +32,34 @@
#ifndef _ARM_ODROID_PLATFORM_H
#define _ARM_ODROID_PLATFORM_H
+#include "opt_exynos.h"
+
/*
* Kernel VM space 16Mb behind KERNEL_BASE upto 0xeff00000
*/
#define KERNEL_VM_BASE 0xc0000000
-#define KERNEL_VM_SIZE 0x24000000
+#define KERNEL_VM_SIZE (EXYNOS_CORE_VBASE - KERNEL_VM_BASE)
/*
* IO space
*/
-/* MJF: This should be 0xF0000000 --- why doesn't that work? */
-/* With this set to 0x10000000 we boot to the point where
- * uvm_init is called and die during it.
+#define EXYNOS_CORE_VBASE 0xf0000000
+
+/*
+ * Serial consoles
*/
-#define EXYNOS_CORE_VBASE 0x10000000
+#define CONADDR_VA ((CONADDR - EXYNOS_CORE_PBASE) + EXYNOS_CORE_VBASE)
+
+#ifdef SSCOM2CONSOLE
+#define SSCON_CHANNEL 0
+#define CONADDR (EXYNOS_CORE_PBASE + EXYNOS5_UART2_OFFSET)
+#endif
+#if 0
+#ifdef SSCOM1CONSOLE
+#define SSCON_CHANNEL 1
+#define CONADDR (EXYNOS_CORE_PBASE + EXYNOS_UART1_OFFSET)
+#endif
+#endif
#endif /* _ARM_ODROID_PLATFORM_H */
