Module Name: src
Committed By: skrll
Date: Thu Mar 3 17:01:31 UTC 2016
Modified Files:
src/sys/arch/arm/arm32: cpu.c
src/sys/arch/arm/include: armreg.h vfpreg.h
src/sys/arch/arm/vfp: vfp_init.c
Log Message:
Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.
My RPI3 works with FB console - the uart needs some help with its clocks.
To generate a diff of this commit:
cvs rdiff -u -r1.112 -r1.113 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.109 -r1.110 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/include/vfpreg.h
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/vfp/vfp_init.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.112 src/sys/arch/arm/arm32/cpu.c:1.113
--- src/sys/arch/arm/arm32/cpu.c:1.112 Sat Jan 23 21:39:17 2016
+++ src/sys/arch/arm/arm32/cpu.c Thu Mar 3 17:01:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.112 2016/01/23 21:39:17 christos Exp $ */
+/* $NetBSD: cpu.c,v 1.113 2016/03/03 17:01:31 skrll Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.112 2016/01/23 21:39:17 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.113 2016/03/03 17:01:31 skrll Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
@@ -513,6 +513,14 @@ const struct cpuidtab cpuids[] = {
pN_steppings, "7A" },
{ CPU_ID_CORTEXA17R1, CPU_CLASS_CORTEX, "Cortex-A17 r1",
pN_steppings, "7A" },
+ { CPU_ID_CORTEXA53R0, CPU_CLASS_CORTEX, "Cortex-A53 r0",
+ pN_steppings, "8A" },
+ { CPU_ID_CORTEXA57R0, CPU_CLASS_CORTEX, "Cortex-A57 r0",
+ pN_steppings, "8A" },
+ { CPU_ID_CORTEXA57R1, CPU_CLASS_CORTEX, "Cortex-A57 r1",
+ pN_steppings, "8A" },
+ { CPU_ID_CORTEXA72R0, CPU_CLASS_CORTEX, "Cortex-A72 r0",
+ pN_steppings, "8A" },
{ CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x",
generic_steppings },
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.109 src/sys/arch/arm/include/armreg.h:1.110
--- src/sys/arch/arm/include/armreg.h:1.109 Thu Oct 15 07:14:56 2015
+++ src/sys/arch/arm/include/armreg.h Thu Mar 3 17:01:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.109 2015/10/15 07:14:56 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.110 2016/03/03 17:01:31 skrll Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -226,12 +226,20 @@
#define CPU_ID_CORTEXA15R2 0x412fc0f0
#define CPU_ID_CORTEXA15R3 0x413fc0f0
#define CPU_ID_CORTEXA17R1 0x411fc0e0
-#define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000)
+#define CPU_ID_CORTEXA53R0 0x410fd030
+#define CPU_ID_CORTEXA57R0 0x410fd070
+#define CPU_ID_CORTEXA57R1 0x411fd070
+#define CPU_ID_CORTEXA72R0 0x410fd080
+
+#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000)
#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070)
#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
#define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0)
+#define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030)
+#define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070)
+#define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080)
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
Index: src/sys/arch/arm/include/vfpreg.h
diff -u src/sys/arch/arm/include/vfpreg.h:1.14 src/sys/arch/arm/include/vfpreg.h:1.15
--- src/sys/arch/arm/include/vfpreg.h:1.14 Mon Feb 9 07:55:52 2015
+++ src/sys/arch/arm/include/vfpreg.h Thu Mar 3 17:01:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: vfpreg.h,v 1.14 2015/02/09 07:55:52 slp Exp $ */
+/* $NetBSD: vfpreg.h,v 1.15 2016/03/03 17:01:31 skrll Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -65,6 +65,7 @@
#define FPU_VFP_CORTEXA9 0x41033090
#define FPU_VFP_CORTEXA15 0x410330f0
#define FPU_VFP_CORTEXA15_QEMU 0x410430f0
+#define FPU_VFP_CORTEXA53 0x41034030
#define FPU_VFP_MV88SV58XX 0x56022090
#define VFP_FPEXC_EX 0x80000000 /* EXception status bit */
Index: src/sys/arch/arm/vfp/vfp_init.c
diff -u src/sys/arch/arm/vfp/vfp_init.c:1.49 src/sys/arch/arm/vfp/vfp_init.c:1.50
--- src/sys/arch/arm/vfp/vfp_init.c:1.49 Thu Nov 12 10:49:35 2015
+++ src/sys/arch/arm/vfp/vfp_init.c Thu Mar 3 17:01:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: vfp_init.c,v 1.49 2015/11/12 10:49:35 jmcneill Exp $ */
+/* $NetBSD: vfp_init.c,v 1.50 2016/03/03 17:01:31 skrll Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -95,6 +95,7 @@ load_vfpregs(const struct vfpreg *fregs)
case FPU_VFP_CORTEXA9:
case FPU_VFP_CORTEXA15:
case FPU_VFP_CORTEXA15_QEMU:
+ case FPU_VFP_CORTEXA53:
#endif
load_vfpregs_hi(fregs->vfp_regs);
#ifdef CPU_ARM11
@@ -117,6 +118,7 @@ save_vfpregs(struct vfpreg *fregs)
case FPU_VFP_CORTEXA9:
case FPU_VFP_CORTEXA15:
case FPU_VFP_CORTEXA15_QEMU:
+ case FPU_VFP_CORTEXA53:
#endif
save_vfpregs_hi(fregs->vfp_regs);
#ifdef CPU_ARM11
@@ -317,6 +319,7 @@ vfp_attach(struct cpu_info *ci)
case FPU_VFP_CORTEXA9:
case FPU_VFP_CORTEXA15:
case FPU_VFP_CORTEXA15_QEMU:
+ case FPU_VFP_CORTEXA53:
if (armreg_cpacr_read() & CPACR_V7_ASEDIS) {
model = "VFP 4.0+";
} else {
