Module Name: src
Committed By: scole
Date: Fri Aug 5 17:04:16 UTC 2016
Modified Files:
src/sys/arch/ia64/include: vmparam.h
Log Message:
PR port-ia64/51261
Import more variables from FreeBSD that will be needed later
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/ia64/include/vmparam.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/ia64/include/vmparam.h
diff -u src/sys/arch/ia64/include/vmparam.h:1.7 src/sys/arch/ia64/include/vmparam.h:1.8
--- src/sys/arch/ia64/include/vmparam.h:1.7 Sun Nov 14 13:33:22 2010
+++ src/sys/arch/ia64/include/vmparam.h Fri Aug 5 17:04:16 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: vmparam.h,v 1.7 2010/11/14 13:33:22 uebayasi Exp $ */
+/* $NetBSD: vmparam.h,v 1.8 2016/08/05 17:04:16 scole Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -63,7 +63,7 @@
#define SGROWSIZ (128UL*1024) /* amount to grow stack */
#endif
-
+#define IA64_VM_MINKERN_REGION 4
/*
* PTEs for mapping user space into the kernel for phyio operations.
@@ -82,6 +82,53 @@
#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6))
#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
+/*
+ * The Itanium architecture defines that all implementations support at
+ * least 51 virtual address bits (i.e. IMPL_VA_MSB=50). The unimplemented
+ * bits are sign-extended from VA{IMPL_VA_MSB}. As such, there's a gap in
+ * the virtual address range, which extends at most from 0x0004000000000000
+ * to 0x1ffbffffffffffff. We define the top half of a region in terms of
+ * this worst-case gap.
+ */
+#define IA64_REGION_GAP_START 0x0004000000000000
+#define IA64_REGION_GAP_EXTEND 0x1ffc000000000000
+
+/*
+ * Parameters for Pre-Boot Virtual Memory (PBVM).
+ * The kernel, its modules and metadata are loaded in the PBVM by the loader.
+ * The PBVM consists of pages for which the mapping is maintained in a page
+ * table. The page table is at least 1 EFI page large (i.e. 4KB), but can be
+ * larger to accommodate more PBVM. The maximum page table size is 1MB. With
+ * 8 bytes per page table entry, this means that the PBVM has at least 512
+ * pages and at most 128K pages.
+ * The GNU toolchain (in particular GNU ld) does not support an alignment
+ * larger than 64K. This means that we cannot guarantee page alignment for
+ * a page size that's larger than 64K. We do want to have text and data in
+ * different pages, which means that the maximum usable page size is 64KB.
+ * Consequently:
+ * The maximum total PBVM size is 8GB -- enough for a DVD image. A page table
+ * of a single EFI page (4KB) allows for 32MB of PBVM.
+ *
+ * The kernel is given the PA and size of the page table that provides the
+ * mapping of the PBVM. The page table itself is assumed to be mapped at a
+ * known virtual address and using a single translation wired into the CPU.
+ * As such, the page table is assumed to be a power of 2 and naturally aligned.
+ * The kernel also assumes that a good portion of the kernel text is mapped
+ * and wired into the CPU, but does not assume that the mapping covers the
+ * whole of PBVM.
+ */
+#define IA64_PBVM_RR IA64_VM_MINKERN_REGION
+#define IA64_PBVM_BASE \
+ (IA64_RR_BASE(IA64_PBVM_RR) + IA64_REGION_GAP_EXTEND)
+
+#define IA64_PBVM_PGTBL_MAXSZ 1048576
+#define IA64_PBVM_PGTBL \
+ (IA64_RR_BASE(IA64_PBVM_RR + 1) - IA64_PBVM_PGTBL_MAXSZ)
+
+#define IA64_PBVM_PAGE_SHIFT 16 /* 64KB */
+#define IA64_PBVM_PAGE_SIZE (1 << IA64_PBVM_PAGE_SHIFT)
+#define IA64_PBVM_PAGE_MASK (IA64_PBVM_PAGE_SIZE - 1)
+
#define IA64_ID_PAGE_SHIFT 28 /* 256M */
#define IA64_ID_PAGE_SIZE (1 << IA64_ID_PAGE_SHIFT)
#define IA64_ID_PAGE_MASK (IA64_ID_PAGE_SIZE-1)
