Module Name:    src
Committed By:   skrll
Date:           Sun Aug  7 07:13:57 UTC 2016

Modified Files:
        src/sys/arch/mips/mips: mipsX_subr.S

Log Message:
Fix two bugs for tlb_invalidate_addr for (PGSHIFT & 1) == 0

- t0/t1 weren't being updated when both lo0/lo1 become invalid
- the global bit (G) needs to be preserved if the entry becomes invalid

The MIPSNN optimisation is disabled for now as it needs to be updated
appropriately


To generate a diff of this commit:
cvs rdiff -u -r1.82 -r1.83 src/sys/arch/mips/mips/mipsX_subr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.82 src/sys/arch/mips/mips/mipsX_subr.S:1.83
--- src/sys/arch/mips/mips/mipsX_subr.S:1.82	Sun Aug  7 06:15:49 2016
+++ src/sys/arch/mips/mips/mipsX_subr.S	Sun Aug  7 07:13:57 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: mipsX_subr.S,v 1.82 2016/08/07 06:15:49 skrll Exp $	*/
+/*	$NetBSD: mipsX_subr.S,v 1.83 2016/08/07 07:13:57 skrll Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -2307,18 +2307,21 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr
 	and	a2, t0				# a2=valid entryLo0 afterwards
 	and	a3, t1				# a3=valid entryLo1 afterwards
 	or	v0, a2, a3			# will one be valid?
-#ifdef MIPSNN
+#ifdef MIPSNNX
+#error Global bit is lost here when V==0 and it needs to be preserved
 	movz	t0, zero, a2			# zero lo0 if V would not be set
 	movz	t1, zero, a3			# zero lo1 if V would not be set
 	movn	t2, a0, v0			# yes, keep VA the same
 #else
-	beqz	v0, 1f				# no valid entry
-	 _SLL	a2, a2, PG_V_LSHIFT		# move V to MSB
+	_SLL	a2, a2, PG_V_LSHIFT		# move V to MSB
 	_SRA	a2, a2, PG_V_RSHIFT		# fill with MSB
+	or	a2, MIPS3_PG_G			# mask needs to preserve G
 	and	t0, t0, a2			# zero lo0 if V would not be set
 	_SLL	a3, a3, PG_V_LSHIFT		# move V to MSB
 	_SRA	a3, a3, PG_V_RSHIFT		# fill with MSB
-	and	t1, t1, a3			# zero lo1 if V would not be set
+	or	a3, MIPS3_PG_G			# mask needs to preserve G
+	beqz	v0, 1f				# no valid entry
+	 and	t1, t1, a3			# zero lo1 if V would not be set
 	move	t2, a0				# we need entryHi to be valid
 1:
 #endif /* MIPSNN */

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