Module Name: xsrc
Committed By: mrg
Date: Tue Aug 16 07:38:15 UTC 2016
Modified Files:
xsrc/external/mit/xf86-video-ati/dist/src: radeon_driver.c
xsrc/external/mit/xf86-video-ati/include: config.h
Added Files:
xsrc/external/mit/xf86-video-ati/xorg-server-copy: README fi1236.c
fi1236.h msp3430.c msp3430.h tda9885.c tda9885.h uda1380.c
uda1380.h
Log Message:
port to xorg-server 1.18.
XXX: fil1236, msp3430, tda9885 and uda1380 drivers are copied from
XXX: our xorg-server 1.10.6 and needed for linking.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 \
xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c
cvs rdiff -u -r1.14 -r1.15 xsrc/external/mit/xf86-video-ati/include/config.h
cvs rdiff -u -r0 -r1.1 \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/README \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.c \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.h \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.c \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.h \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.c \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.h \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.c \
xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c:1.13 xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c:1.14
--- xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c:1.13 Tue Aug 16 01:27:46 2016
+++ xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c Tue Aug 16 07:38:15 2016
@@ -6440,7 +6440,11 @@ static Bool RADEONCloseScreen(CLOSE_SCRE
if (info->dri && info->dri->pDamage) {
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
+#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,15,0,0,0)
+ DamageUnregister(info->dri->pDamage);
+#else
DamageUnregister(&pPix->drawable, info->dri->pDamage);
+#endif
DamageDestroy(info->dri->pDamage);
info->dri->pDamage = NULL;
}
Index: xsrc/external/mit/xf86-video-ati/include/config.h
diff -u xsrc/external/mit/xf86-video-ati/include/config.h:1.14 xsrc/external/mit/xf86-video-ati/include/config.h:1.15
--- xsrc/external/mit/xf86-video-ati/include/config.h:1.14 Sun Sep 23 20:06:51 2012
+++ xsrc/external/mit/xf86-video-ati/include/config.h Tue Aug 16 07:38:15 2016
@@ -118,8 +118,10 @@
/* Define to use byteswap macros from <sys/endian.h> */
#define USE_SYS_ENDIAN_H 1
+#if 0
/* Build support for XAA */
#define USE_XAA 1
+#endif
/* Version number of package */
#define VERSION "6.14.6"
Added files:
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/README
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/README:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/README Tue Aug 16 07:38:15 2016
@@ -0,0 +1,7 @@
+$NetBSD: README,v 1.1 2016/08/16 07:38:15 mrg Exp $
+
+These are copied from xorg-server 1.10.6 in the NetBSD xsrc tree,
+and are apparently necessary for xf86-video-ati pre-KMS-only to
+build, which is necessary for older NetBSD ports.
+
+--mrg 2016-08-15
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.c
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.c:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.c Tue Aug 16 07:38:15 2016
@@ -0,0 +1,605 @@
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#include "xf86.h"
+#include "xf86i2c.h"
+#include "fi1236.h"
+#include "tda9885.h"
+#include "i2c_def.h"
+
+#define NUM_TUNERS 8
+
+const FI1236_parameters tuner_parms[NUM_TUNERS] =
+{
+ /* 0 - FI1236 */
+ { 733 ,884 ,12820 ,2516 ,7220 ,0xA2 ,0x94, 0x34, 0x8e },
+ /* !!!based on documentation - it should be:
+ {733 ,16*55.25 ,16*801.25 ,16*160 ,16*454 ,0xA0 ,0x90, 0x30, 0x8e},*/
+
+ /* 1 - FI1216 */
+ { 623 ,16*48.75 ,16*855.25 ,16*170 ,16*450 ,0xA0 ,0x90, 0x30, 0x8e },
+ /* 2 - TEMIC FN5AL */
+ { 623 ,16*45.75 ,16*855.25 ,16*169 ,16*454 ,0xA0 ,0x90, 0x30, 0x8e },
+ /* 3 - MT2032.. */
+ { 733 ,768 ,13760 , 0 , 0 , 0 , 0, 0, 0 },
+ /* 4 - FI1246 */
+ { 623 ,16*45.75 ,16*855.25 ,16*170 ,16*450 ,0xA0 ,0x90, 0x30, 0x8e },
+ /* 5 - FI1256 */
+ { 623 ,16*49.75 ,16*863.25 ,16*170 ,16*450 ,0xA0 ,0x90, 0x30, 0x8e },
+ /* 6 - FI1236W */
+ /*{ 733 ,884 ,12820 ,2516 ,7220 ,0x1 ,0x2, 0x4, 0x8e },*/
+ { 732, 16*55.25, 16*801.25, 16*160, 16*442, 0x1, 0x2, 0x4, 0x8e },
+ /* 7 - FM1216ME */
+ { 623 ,16*48.25 ,16*863.25 ,16*158.00 ,16*442.00 ,0x1 ,0x2, 0x4, 0x8e }
+};
+
+
+FI1236Ptr Detect_FI1236(I2CBusPtr b, I2CSlaveAddr addr)
+{
+ FI1236Ptr f;
+ I2CByte a;
+
+ f = calloc(1,sizeof(FI1236Rec));
+ if(f == NULL) return NULL;
+ f->d.DevName = strdup("FI12xx Tuner");
+ f->d.SlaveAddr = addr;
+ f->d.pI2CBus = b;
+ f->d.NextDev = NULL;
+ f->d.StartTimeout = b->StartTimeout;
+ f->d.BitTimeout = b->BitTimeout;
+ f->d.AcknTimeout = b->AcknTimeout;
+ f->d.ByteTimeout = b->ByteTimeout;
+ f->type=TUNER_TYPE_FI1236;
+ f->afc_timer_installed=FALSE;
+ f->last_afc_hint=TUNER_OFF;
+ f->video_if=45.7812;
+
+ if(!I2C_WriteRead(&(f->d), NULL, 0, &a, 1))
+ {
+ free(f);
+ return NULL;
+ }
+ FI1236_set_tuner_type(f, TUNER_TYPE_FI1236);
+ if(!I2CDevInit(&(f->d)))
+ {
+ free(f);
+ return NULL;
+ }
+ return f;
+}
+
+static void MT2032_dump_parameters(FI1236Ptr f, MT2032_parameters *m)
+{
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: input f_rf=%g f_if1=%g f_if2=%g f_ref=%g f_ifbw=%g f_step=%g\n",
+ m->f_rf, m->f_if1, m->f_if2, m->f_ref, m->f_ifbw, m->f_step);
+
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: computed f_lo1=%g f_lo2=%g LO1I=%d LO2I=%d SEL=%d STEP=%d NUM=%d\n",
+ m->f_lo1, m->f_lo2, m->LO1I, m->LO2I, m->SEL, m->STEP, m->NUM);
+}
+
+
+static void MT2032_getid(FI1236Ptr f)
+{
+CARD8 out[4];
+CARD8 in;
+
+in=0x11;
+I2C_WriteRead(&(f->d), (I2CByte *)&in, 1, out, 4);
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: Company code 0x%02x%02x, part code 0x%02x, revision code 0x%02x\n",
+ out[0], out[1], out[2], out[3]);
+
+}
+
+/* might be buggy */
+#if 0
+static void MT2032_shutdown(FI1236Ptr f)
+{
+CARD8 data[10];
+
+data[0]=0x00; /* start with register 0x00 */
+data[1]=0x1A;
+data[2]=0x44;
+data[3]=0x20;
+
+I2C_WriteRead(&(f->d), (I2CByte *)data, 4, NULL, 0);
+
+data[0]=0x05; /* now start with register 0x05 */
+data[1]=0xD7;
+data[2]=0x14;
+data[3]=0x05;
+I2C_WriteRead(&(f->d), (I2CByte *)data, 4, NULL, 0);
+
+data[0]=0x0B; /* now start with register 0x05 */
+data[1]=0x8F;
+data[2]=0x07;
+data[3]=0x43;
+I2C_WriteRead(&(f->d), (I2CByte *)data, 4, NULL, 0);
+
+usleep(15000);
+}
+#endif
+
+static void MT2032_dump_status(FI1236Ptr f);
+
+static void MT2032_init(FI1236Ptr f)
+{
+CARD8 data[10];
+CARD8 value;
+CARD8 xogc = 0x00;
+
+MT2032_getid(f);
+
+data[0]=0x02; /* start with register 0x02 */
+data[1]=0xFF;
+data[2]=0x0F;
+data[3]=0x1F;
+
+I2C_WriteRead(&(f->d), (I2CByte *)data, 4, NULL, 0);
+
+data[0]=0x06; /* now start with register 0x06 */
+data[1]=0xE4;
+data[2]=0x8F;
+data[3]=0xC3;
+data[4]=0x4E;
+data[5]=0xEC;
+I2C_WriteRead(&(f->d), (I2CByte *)data, 6, NULL, 0);
+
+data[0]=0x0d; /* now start with register 0x0d */
+data[1]=0x32;
+I2C_WriteRead(&(f->d), (I2CByte *)data, 2, NULL, 0);
+
+while(1) {
+ usleep(15000); /* wait 15 milliseconds */
+
+ data[0]=0x0e; /* register number 7, status */
+ value=0xFF;
+ if(!I2C_WriteRead(&(f->d), (I2CByte *)data, 1, &value, 1))
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: failed to read XOK\n");
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: XOK=%d\n", value & 0x01);
+ if(value & 1) break;
+
+ data[0]=0x07;
+ if(!I2C_WriteRead(&(f->d), (I2CByte *)data, 1, &value, 1))
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: failed to read XOGC\n");
+
+ xogc=value & 0x7;
+ if(xogc==4){
+ break; /* XOGC has reached 4.. stop */
+ }
+ xogc--;
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: try XOGC=%d\n", xogc);
+ usleep(15000);
+ data[0]=0x07; /* register number 7, control byte 2 */
+ data[1]=0x08 | xogc;
+ I2C_WriteRead(&(f->d), (I2CByte *)data, 2, NULL, 0);
+ }
+f->xogc=xogc;
+/* wait before continuing */
+usleep(15000); /* wait 50 milliseconds */
+MT2032_dump_status(f);
+}
+
+static int MT2032_no_spur_in_band(MT2032_parameters *m)
+{
+int n_max, n1, n2;
+double f_test;
+n_max=5;
+n1=1;
+while(1){
+ n2=-n1;
+ f_test=n1*(m->f_lo1-m->f_lo2);
+ while(1){
+ n2--;
+ f_test=f_test-m->f_lo2;
+ xf86DrvMsg(0, X_INFO, "testing f_test=%g n1=%d n2=%d f_lo1=%g f_lo2=%g f_if2=%g\n", f_test, n1, n2, m->f_lo1, m->f_lo2, m->f_if2);
+ xf86DrvMsg(0, X_INFO, "d_f=%g f_ifbw=%g\n",fabs(fabs(f_test)-m->f_if2), m->f_ifbw);
+ if((fabs(fabs(f_test)-m->f_if2)*2.0)<=m->f_ifbw)return 0;
+ if(n2<=-n_max)break;
+ /* this line in the manual is bogus. I say it is faster
+ and more correct to go over all harmonics.. */
+ #if 0
+ if(f_test<(m->f_lo2-m->f_if2-m->f_ifbw))break;
+ #endif
+ }
+ n1++;
+ if(n1>=n_max)return 1;
+ }
+
+}
+
+static void MT2032_calculate_register_settings(MT2032_parameters *m, double f_rf, double f_if1, double f_if2, double f_ref, double f_ifbw, double f_step)
+{
+int n;
+m->f_rf=f_rf;
+m->f_if1=f_if1;
+m->f_if2=f_if2;
+m->f_ref=f_ref;
+m->f_ifbw=f_ifbw;
+m->f_step=f_step;
+
+m->f_lo1=f_rf+f_if1;
+m->LO1I=lrint(m->f_lo1/f_ref);
+m->f_lo1=f_ref*m->LO1I;
+
+m->f_lo2=m->f_lo1-f_rf-f_if2;
+
+/* check for spurs */
+n=1;
+while(n<3){
+ if(MT2032_no_spur_in_band(m))break;
+ if(m->f_lo1<(f_rf+f_if1)){
+ m->LO1I+=n;
+ } else {
+ m->LO1I-=n;
+ }
+ m->f_lo1=m->LO1I*f_ref;
+ m->f_lo2=m->f_lo1-f_rf-f_if2;
+ n++;
+ }
+/* xf86DrvMsg(0, X_INFO, "MT2032: n=%d\n", n); */
+/* select VCO */
+
+/* m->f_lo1>1100.0 */
+if(m->f_lo1<1370.0)m->SEL=4;
+ else
+if(m->f_lo1<1530.0)m->SEL=3;
+ else
+if(m->f_lo1<1720.0)m->SEL=2;
+ else
+if(m->f_lo1<1890.0)m->SEL=1;
+ else /* m->f_lo1 < 1958.0 */
+ m->SEL=0;
+
+/* calculate the rest of the registers */
+m->LO2I=floor(m->f_lo2/f_ref);
+m->STEP=floor(3780.0*f_step/f_ref);
+m->NUM=floor(3780.0*(m->f_lo2/f_ref-m->LO2I));
+m->NUM=m->STEP*lrint((1.0*m->NUM)/(1.0*m->STEP));
+}
+
+static int MT2032_wait_for_lock(FI1236Ptr f)
+{
+int n;
+CARD8 data[10];
+CARD8 value;
+
+n=12;
+while(1){
+ data[0]=0x0e; /* register number 7, status */
+ I2C_WriteRead(&(f->d), (I2CByte *)data, 1, &value, 1);
+/* xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: LO1LK=%d LO2LK=%d\n", (value & 0x04)>>2, (value & 0x02)>>1); */
+ if((value & 6)==6) break;
+ usleep(1500);
+ n--;
+ if(n<0)break;
+ }
+if(n<0){
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: failed to set frequency\n");
+ return 0;
+ }
+return 1;
+}
+
+static void MT2032_implement_settings(FI1236Ptr f, MT2032_parameters *m)
+{
+CARD8 data[10];
+CARD8 value;
+
+data[0]=0x00; /* start with register 0x00 */
+data[1]=(m->LO1I>>3)-1;
+data[2]=(m->SEL<<4)|(m->LO1I & 0x7);
+data[3]=0x86;
+I2C_WriteRead(&(f->d), (I2CByte *)data, 4, NULL, 0);
+
+data[0]=0x05; /* start with register 0x05 */
+data[1]=((m->LO2I & 0x7)<<5)|((m->LO2I>>3)-1);
+if(m->f_rf<400.0)data[2]=0xe4;
+ else data[2]=0xf4;
+I2C_WriteRead(&(f->d), (I2CByte *)data, 3, NULL, 0);
+
+data[0]=0x07; /* register number 7, control byte 2 */
+I2C_WriteRead(&(f->d), (I2CByte *)data, 1, &value, 1);
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: using XOGC=%d\n", (value & 0x07));
+data[1]=8 | (value & 0x7);
+I2C_WriteRead(&(f->d), (I2CByte *)data, 2, NULL, 0);
+
+data[0]=0x0b; /* start with register 0x0b */
+data[1]=m->NUM & 0xff;
+data[2]=(1<<7)|((m->NUM >> 8) & 0x0f);
+I2C_WriteRead(&(f->d), (I2CByte *)data, 3, NULL, 0);
+
+MT2032_wait_for_lock(f);
+}
+
+static void MT2032_optimize_VCO(FI1236Ptr f, MT2032_parameters *m)
+{
+CARD8 data[10];
+CARD8 value;
+CARD8 TAD1;
+
+data[0]=0x0f; /* register number 7, status */
+I2C_WriteRead(&(f->d), (I2CByte *)data, 1, &value, 1);
+TAD1=value & 0x07;
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: TAD1=%d SEL=%d\n", TAD1, m->SEL);
+if(TAD1 < 2)return;
+if(TAD1==2){
+ if(m->SEL==0)return;
+ m->SEL--;
+ } else {
+ if(m->SEL>=4)return;
+ m->SEL++;
+ }
+data[0]=0x01; /* start with register 1 */
+data[1]=(m->SEL<<4)|(m->LO1I & 0x7);
+I2C_WriteRead(&(f->d), (I2CByte *)data, 2, NULL, 0);
+
+}
+
+static int FI1236_get_afc_hint(FI1236Ptr f)
+{
+ CARD8 out;
+ CARD8 AFC;
+
+ if ((f->type == TUNER_TYPE_FM1216ME) || (f->type == TUNER_TYPE_FI1236W))
+ {
+ TDA9885Ptr t = (TDA9885Ptr)f->afc_source;
+ if (t == NULL)
+ return TUNER_OFF;
+
+ tda9885_getstatus(t);
+ tda9885_dumpstatus(t);
+ AFC = t->afc_status & 0x0f;
+
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC: FI1236_get_afc_hint: %i\n", AFC);
+ if (AFC == 0) return TUNER_TUNED;
+ else if (AFC <= 0x07)return TUNER_JUST_BELOW;
+ else if (AFC < 0x0f )return TUNER_JUST_ABOVE;
+ else if (AFC == 0x0f)return TUNER_TUNED;
+ }
+ else
+ {
+ I2C_WriteRead(&(f->d), NULL, 0, &out, 1);
+ AFC=out & 0x7;
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC: FI1236_get_afc_hint: %i\n", AFC);
+ if(AFC==2)return TUNER_TUNED;
+ if(AFC==3)return TUNER_JUST_BELOW;
+ if(AFC==1)return TUNER_JUST_ABOVE;
+ return TUNER_OFF;
+ }
+ return TUNER_OFF;
+}
+
+static int MT2032_get_afc_hint(FI1236Ptr f)
+{
+CARD8 in;
+CARD8 out[2];
+CARD8 AFC;
+in=0x0e;
+I2C_WriteRead(&(f->d), (I2CByte *)&in, 1, out, 2);
+AFC=(out[0]>>4) & 0x7;
+#if 0
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC=%d TAD1=%d TAD2=%d\n", AFC, out[1] & 0x7, (out[1]>>4)& 0x07);
+#endif
+if(AFC==2)return TUNER_TUNED;
+if(AFC==3)return TUNER_JUST_BELOW;
+if(AFC==1)return TUNER_JUST_ABOVE;
+return TUNER_OFF;
+}
+
+/* this function is for external use only */
+int TUNER_get_afc_hint(FI1236Ptr f)
+{
+if(f->afc_timer_installed)return TUNER_STILL_TUNING;
+return f->last_afc_hint;
+}
+
+static void MT2032_dump_status(FI1236Ptr f)
+{
+CARD8 in;
+CARD8 out[2];
+CARD8 AFC;
+CARD8 LDONrb;
+CARD8 LO1LK, LO2LK, XOK;
+CARD8 TAD2, TAD1;
+
+in=0x0e;
+I2C_WriteRead(&(f->d), (I2CByte *)&in, 1, out, 2);
+XOK=out[0] & 1;
+LO1LK=(out[0]>>2) &1;
+LO2LK=(out[0]>>1) &1;
+LDONrb=(out[0]>>3) &1;
+
+AFC=(out[0]>>4) & 0x7;
+
+TAD1=(out[1] & 0x7);
+TAD2=(out[1]>>4) & 0x7;
+
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: status: XOK=%d LO1LK=%d LO2LK=%d LDONrb=%d AFC=%d TAD1=%d TAD2=%d\n",
+ XOK, LO1LK, LO2LK, LDONrb, AFC, TAD1, TAD2);
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: status: OSCILLATOR:%s PLL1:%s PLL2:%s\n",
+ XOK ? "ok":"off", LO1LK ? "locked" : "off" , LO2LK ? "locked" : "off");
+
+}
+
+static void MT2032_tune(FI1236Ptr f, double freq, double step)
+{
+MT2032_parameters m;
+CARD8 data[10];
+int i;
+/* NTSC IF is 44mhz.. but 733/16=45.8125 and all TDAXXXX docs mention
+ 45.75, 39, 58.75 and 30. */
+#if 0
+MT2032_calculate_register_settings(&m, freq, 1090.0, 45.125, 5.25, 6.0, step);
+MT2032_calculate_register_settings(&m, freq, 1090.0, 45.74, 5.25, 6.0, step);
+#endif
+MT2032_calculate_register_settings(&m, freq, 1090.0, f->video_if, 5.25, 3.0, step);
+MT2032_dump_parameters(f, &m);
+MT2032_implement_settings(f, &m);
+/* MT2032_dump_parameters(f, &m); */
+for(i=0;i<3;i++){
+ MT2032_optimize_VCO(f, &m);
+ if(MT2032_wait_for_lock(f)){
+ data[0]=0x02; /* LO Gain control register 0x02 */
+ data[1]=0x20;
+ I2C_WriteRead(&(f->d), (I2CByte *)data, 2, NULL, 0);
+ return;
+ }
+ data[0]=0x07;
+ data[1]=0x88|f->xogc;
+ I2C_WriteRead(&(f->d), (I2CByte *)data, 2, NULL, 0);
+ usleep(15000);
+ data[1]=0x08|f->xogc;
+ I2C_WriteRead(&(f->d), (I2CByte *)data, 2, NULL, 0);
+ }
+xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "MT2032: failed to set frequency\n");
+}
+
+void FI1236_set_tuner_type(FI1236Ptr f, int type)
+{
+f->type=type;
+if(type>=NUM_TUNERS)type = NUM_TUNERS-1;
+if(type<0)type = 0;
+memcpy(&(f->parm), &(tuner_parms[type]), sizeof(FI1236_parameters));
+f->original_frequency=f->parm.min_freq;
+f->afc_delta=0;
+if(type==TUNER_TYPE_MT2032){
+ MT2032_init(f);
+ return;
+ }
+}
+
+
+static CARD32 AFC_TimerCallback(OsTimerPtr timer, CARD32 time, pointer data){
+FI1236Ptr f=(FI1236Ptr)data;
+if(FI1236_AFC(f))return 150;
+ else {
+ f->afc_timer_installed=FALSE;
+ f->afc_count=0;
+ return 0;
+ }
+}
+
+void FI1236_tune(FI1236Ptr f, CARD32 frequency)
+{
+ CARD16 divider;
+ CARD8 data;
+
+ if(frequency < f->parm.min_freq) frequency = f->parm.min_freq;
+ if(frequency > f->parm.max_freq) frequency = f->parm.max_freq;
+
+ divider = (f->parm.fcar+(CARD16)frequency) & 0x7fff;
+ f->tuner_data.div1 = (CARD8)((divider>>8)&0x7f);
+ f->tuner_data.div2 = (CARD8)(divider & 0xff);
+ f->tuner_data.control = f->parm.control;
+
+ if(frequency < f->parm.threshold1)
+ {
+ f->tuner_data.band = f->parm.band_low;
+ }
+ else if (frequency < f->parm.threshold2)
+ {
+ f->tuner_data.band = f->parm.band_mid;
+ }
+ else
+ {
+ f->tuner_data.band = f->parm.band_high;
+ }
+
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "Setting tuner band to %d\n", f->tuner_data.band);
+
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "Setting tuner frequency to %d\n", (int)frequency);
+
+ if ((f->type == TUNER_TYPE_FM1216ME) || (f->type == TUNER_TYPE_FI1236W))
+ {
+ f->tuner_data.aux = 0x20;
+ I2C_WriteRead(&(f->d), (I2CByte *)&(f->tuner_data), 5, NULL, 0);
+ I2C_WriteRead(&(f->d), NULL, 0, &data, 1);
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "Tuner status %x\n", data);
+
+ }
+ else
+ I2C_WriteRead(&(f->d), (I2CByte *)&(f->tuner_data), 4, NULL, 0);
+}
+
+void TUNER_set_frequency(FI1236Ptr f, CARD32 frequency)
+{
+ if(frequency < f->parm.min_freq) frequency = f->parm.min_freq;
+ if(frequency > f->parm.max_freq) frequency = f->parm.max_freq;
+
+ f->afc_delta=0;
+ f->original_frequency=frequency;
+
+ if(f->type==TUNER_TYPE_MT2032)
+ {
+ MT2032_tune(f, (1.0*frequency)/16.0, 0.0625);
+ } else
+ {
+ FI1236_tune(f, frequency);
+ }
+
+ if(!f->afc_timer_installed)
+ {
+ f->afc_timer_installed=TRUE;
+/* RegisterBlockAndWakeupHandlers(FI1236_BlockHandler, AFCWakeup, f); */
+ TimerSet(NULL, 0, 300, AFC_TimerCallback, f);
+ }
+
+}
+
+
+int FI1236_AFC(FI1236Ptr f)
+{
+ #if 0
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC: f=%p f->count=%d f->original_frequency=%d f->afc_delta=%d\n", f, f->afc_count, f->original_frequency, f->afc_delta);
+ #endif
+ f->afc_count++;
+ if(f->type==TUNER_TYPE_MT2032)
+ {
+ f->last_afc_hint=MT2032_get_afc_hint(f);
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC: afc_hint=%d\n", f->last_afc_hint);
+ if(f->last_afc_hint==TUNER_TUNED)return 0;
+ if(f->afc_count>3)f->last_afc_hint=TUNER_OFF;
+ if(f->last_afc_hint==TUNER_OFF)
+ {
+ f->afc_delta=0;
+ } else
+ f->afc_delta+=f->last_afc_hint;
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC: Setting tuner frequency to %g\n", (0.5*(2*f->original_frequency+f->afc_delta))/16.0);
+ MT2032_tune(f, (1.0*f->original_frequency+0.5*f->afc_delta)/16.0, 0.03125);
+ if(f->last_afc_hint==TUNER_OFF)return 0;
+ return 1; /* call me again */
+ } else
+ {
+ f->last_afc_hint=FI1236_get_afc_hint(f);
+ if(f->last_afc_hint==TUNER_TUNED)
+ {
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC: TUNER_TUNNED\n");
+ return 0;
+ }
+ if(f->afc_count>3)f->last_afc_hint=TUNER_OFF;
+ if(f->last_afc_hint==TUNER_OFF)
+ {
+ f->afc_delta=0;
+ } else
+ f->afc_delta+=f->last_afc_hint;
+ xf86DrvMsg(f->d.pI2CBus->scrnIndex, X_INFO, "AFC: Setting tuner frequency to %g\n", (0.5*(2*f->original_frequency+f->afc_delta))/16.0);
+ FI1236_tune(f, f->original_frequency+f->afc_delta);
+ if(f->last_afc_hint==TUNER_OFF)return 0;
+ return 1; /* call me again */
+ }
+ return 0; /* done */
+}
+
+void fi1236_dump_status(FI1236Ptr f)
+{
+if(f->type==TUNER_TYPE_MT2032){
+ MT2032_dump_status(f);
+ }
+}
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.h
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.h:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/fi1236.h Tue Aug 16 07:38:15 2016
@@ -0,0 +1,111 @@
+#ifndef __FI1236_H__
+#define __FI1236_H__
+
+#include "xf86i2c.h"
+
+/* why someone has defined NUM someplace else is beyoung me.. */
+#undef NUM
+
+typedef struct {
+ CARD32 fcar; /* 16 * fcar_Mhz */
+ CARD32 min_freq; /* 16 * min_freq_Mhz */
+ CARD32 max_freq; /* 16 * max_freq_Mhz */
+
+ CARD32 threshold1; /* 16 * Value_Mhz */
+ CARD32 threshold2; /* 16 * Value_Mhz */
+
+ CARD8 band_low;
+ CARD8 band_mid;
+ CARD8 band_high;
+ CARD8 control;
+ } FI1236_parameters;
+
+
+typedef struct {
+ /* what we want */
+ /* all frequencies are in Mhz */
+ double f_rf; /* frequency to tune to */
+ double f_if1; /* first intermediate frequency */
+ double f_if2; /* second intermediate frequency */
+ double f_ref; /* reference frequency */
+ double f_ifbw; /* bandwidth */
+ double f_step; /* step */
+
+ /* what we compute */
+ double f_lo1;
+ double f_lo2;
+ int LO1I;
+ int LO2I;
+ int SEL;
+ int STEP;
+ int NUM;
+ } MT2032_parameters;
+
+typedef struct {
+ I2CDevRec d;
+ int type;
+
+ void* afc_source; /* The AFC source may be another chip like TDA988x */
+
+ int afc_delta;
+ CARD32 original_frequency;
+ Bool afc_timer_installed;
+ int afc_count;
+ int last_afc_hint;
+
+ double video_if;
+ FI1236_parameters parm;
+ int xogc; /* for MT2032 */
+
+ struct {
+ CARD8 div1;
+ CARD8 div2;
+ CARD8 control;
+ CARD8 band;
+ CARD8 aux; /* this is for MK3 tuners */
+ } tuner_data;
+ } FI1236Rec, *FI1236Ptr;
+
+#define TUNER_TYPE_FI1236 0
+#define TUNER_TYPE_FI1216 1
+#define TUNER_TYPE_TEMIC_FN5AL 2
+#define TUNER_TYPE_MT2032 3
+#define TUNER_TYPE_FI1246 4
+#define TUNER_TYPE_FI1256 5
+#define TUNER_TYPE_FI1236W 6
+#define TUNER_TYPE_FM1216ME 7
+
+#define FI1236_ADDR(a) ((a)->d.SlaveAddr)
+
+#define FI1236_ADDR_1 0xC6
+#define FI1236_ADDR_2 0xC0
+
+#define TUNER_TUNED 0
+#define TUNER_JUST_BELOW 1
+#define TUNER_JUST_ABOVE -1
+#define TUNER_OFF 4
+#define TUNER_STILL_TUNING 5
+
+
+void FI1236_tune(FI1236Ptr f, CARD32 frequency);
+
+#define FI1236SymbolsList \
+ "Detect_FI1236", \
+ "FI1236_set_tuner_type", \
+ "TUNER_set_frequency"
+
+#define xf86_Detect_FI1236 Detect_FI1236
+extern _X_EXPORT FI1236Ptr Detect_FI1236(I2CBusPtr b, I2CSlaveAddr addr);
+#define xf86_FI1236_set_tuner_type FI1236_set_tuner_type
+extern _X_EXPORT void FI1236_set_tuner_type(FI1236Ptr f, int type);
+#define xf86_TUNER_set_frequency TUNER_set_frequency
+extern _X_EXPORT void TUNER_set_frequency(FI1236Ptr f, CARD32 frequency);
+
+#define xf86_FI1236_AFC FI1236_AFC
+extern _X_EXPORT int FI1236_AFC(FI1236Ptr f);
+#define xf86_TUNER_get_afc_hint TUNER_get_afc_hint
+extern _X_EXPORT int TUNER_get_afc_hint(FI1236Ptr f);
+#define xf86_fi1236_dump_status fi1236_dump_status
+extern _X_EXPORT void fi1236_dump_status(FI1236Ptr f);
+
+#endif
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.c
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.c:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.c Tue Aug 16 07:38:15 2016
@@ -0,0 +1,726 @@
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <string.h>
+#include <unistd.h>
+
+#include "xf86.h"
+#include "xf86i2c.h"
+#include "msp3430.h"
+#include "i2c_def.h"
+
+#define CONTROL 0x00
+#define WR_DEM 0x10
+#define RD_DEM 0x11
+#define WR_DSP 0x12
+#define RD_DSP 0x13
+
+
+void InitMSP34xxG(MSP3430Ptr m);
+void InitMSP34x5D(MSP3430Ptr m);
+void CheckModeMSP34x5D(MSP3430Ptr m);
+char *MSP_getProductName (CARD16 product_id);
+void mpause(int milliseconds);
+
+#define __MSPDEBUG__ 0
+
+#if __MSPDEBUG__ > 3
+
+void MSPBeep(MSP3430Ptr m, CARD8 freq);
+#define __MSPBEEP MSPBeep(m,0x14);
+
+#else
+
+#define __MSPBEEP
+#endif
+
+static void SetMSP3430Control(MSP3430Ptr m, CARD8 RegAddress, CARD8 RegValueHigh, CARD8 RegValueLow)
+{
+ I2CByte data[3];
+
+ data[0]=RegAddress;
+ data[1]=RegValueHigh;
+ data[2]=RegValueLow;
+
+ I2C_WriteRead(&(m->d),data,3,NULL,0);
+}
+
+static void SetMSP3430Data(MSP3430Ptr m, CARD8 RegAddress, CARD8 RegSubAddressHigh, CARD8 RegSubAddressLow,
+ CARD8 RegValueHigh, CARD8 RegValueLow)
+{
+ I2CByte data[5];
+#ifdef MSP_DEBUG
+ if(!m->registers_present[RegSubAddressLow]){
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_ERROR, "Attempt to access non-existent register in MSP34xxX: 0x%02x 0x%02x 0x%02x <- 0x%02x 0x%02x\n",
+ RegAddress, RegSubAddressHigh, RegSubAddressLow, RegValueHigh, RegValueLow);
+ }
+#endif
+
+ data[0] = RegAddress;
+ data[1] = RegSubAddressHigh;
+ data[2] = RegSubAddressLow;
+ data[3] = RegValueHigh;
+ data[4] = RegValueLow;
+
+ I2C_WriteRead(&(m->d),data,5,NULL,0);
+}
+
+static void GetMSP3430Data(MSP3430Ptr m, CARD8 RegAddress, CARD8 RegSubAddressHigh, CARD8 RegSubAddressLow,
+ CARD8 *RegValueHigh, CARD8 *RegValueLow)
+{
+ I2CByte send[3];
+ I2CByte receive[2];
+
+ send[0] = RegAddress;
+ send[1] = RegSubAddressHigh;
+ send[2] = RegSubAddressLow;
+
+ I2C_WriteRead(&(m->d), send, 3, receive, 2);
+
+ *RegValueHigh = receive[0];
+ *RegValueLow = receive[1];
+}
+
+#if __MSPDEBUG__ > 2
+static void MSP3430DumpStatus(MSP3430Ptr m)
+{
+CARD8 status_hi, status_lo;
+CARD8 subaddr, data[2];
+
+GetMSP3430Data(m, RD_DEM, 0x02, 0x00, &status_hi, &status_lo);
+xf86DrvMsg(m->d.pI2CBus->scrnIndex, X_INFO, "MSP34xx: SAP(8)=%d mono/NICAM(7)=%d stereo=%d %s O_1=%d O_0=%d 2nd car=%d 1st car=%d\n",
+ status_hi & 1, (status_lo>>7) & 1, (status_lo>>6)&1,
+ (status_lo>>5)? ( (status_hi>>1)&1? "bad NICAM reception" : "NICAM" ) :
+ ((status_hi>>1)&1 ? "bogus" : "ANALOG FM/AM") ,
+ (status_lo>>4)&1, (status_lo>>3)&1,!( (status_lo>>2)&1), !((status_lo>>1)&1));
+
+GetMSP3430Data(m, RD_DEM, 0x00, 0x7E, &status_hi, &status_lo);
+xf86DrvMsg(m->d.pI2CBus->scrnIndex, X_INFO, "MSP34xx: standard result=0x%02x%02x\n",
+ status_hi, status_lo);
+subaddr=0x0;
+I2C_WriteRead(&(m->d), &subaddr, 1, data, 2);
+xf86DrvMsg(m->d.pI2CBus->scrnIndex, X_INFO, "MSP34xx: control=0x%02x%02x\n",
+ data[1], data[0]);
+}
+#endif
+
+/* wrapper */
+void InitMSP3430(MSP3430Ptr m)
+{
+ #if __MSPDEBUG__ > 1
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_INFO,"InitMSP3430(m->connector=%d, m->standard=%d, m->chip_family=%d)\n",
+ m->connector, m->standard, m->chip_family);
+ #endif
+ switch (m->chip_family) {
+ case MSPFAMILY_34x0G:
+ InitMSP34xxG(m);
+ break;
+ case MSPFAMILY_34x5G:
+ InitMSP34xxG(m);
+ break;
+ case MSPFAMILY_34x5D:
+ InitMSP34x5D(m);
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------
+| common functions for all MSP34xx chips
+|----------------------------------------------------------------*/
+
+MSP3430Ptr DetectMSP3430(I2CBusPtr b, I2CSlaveAddr addr)
+{
+ MSP3430Ptr m;
+ I2CByte a;
+ CARD8 hardware_version, major_revision, product_code, rom_version;
+ Bool supported;
+
+ m = calloc(1,sizeof(MSP3430Rec));
+ if(m == NULL)return NULL;
+ m->d.DevName = strdup("MSP34xx");
+ m->d.SlaveAddr = addr;
+ m->d.pI2CBus = b;
+ m->d.NextDev = NULL;
+ m->d.StartTimeout = b->StartTimeout;
+ m->d.BitTimeout = b->BitTimeout;
+ m->d.AcknTimeout = b->AcknTimeout;
+ m->d.ByteTimeout = b->ByteTimeout;
+
+ if(!I2C_WriteRead(&(m->d), NULL, 0, &a, 1))
+ {
+ free(m->d.DevName);
+ free(m);
+ return NULL;
+ }
+
+
+ m->standard=MSP3430_NTSC;
+ m->connector=MSP3430_CONNECTOR_1;
+ m->mode=MSPMODE_STEREO_A; /*stereo or chanel A if avail. */
+ m->c_format=MSPFORMAT_UNKNOWN;
+ m->c_standard=MSPSTANDARD_UNKNOWN;
+ m->c_matrix=m->c_fmmatrix=m->c_source=0;
+ m->volume=0;
+ m->recheck=FALSE;
+
+ GetMSP3430Data(m, RD_DSP, 0x00, 0x1E, &hardware_version, &major_revision);
+ GetMSP3430Data(m, RD_DSP, 0x00, 0x1F, &product_code, &rom_version);
+ m->hardware_version=hardware_version;
+ m->major_revision=major_revision;
+ m->product_code=product_code;
+ m->rom_version=rom_version;
+
+ m->chip_id=((major_revision << 8) | product_code);
+
+ supported=FALSE;
+ switch (major_revision) {
+ case 4: /* 34xxD */
+ switch (product_code) {
+ case 0x05: /* 3405D */
+ case 0x0A: /* 3410D */
+ case 0x0F: /* 3415D */
+ m->chip_family=MSPFAMILY_34x5D;
+ m->recheck=TRUE;
+ supported=TRUE;
+ break;
+ default:
+ m->chip_family=MSPFAMILY_34x0D;
+ }
+ break;
+ case 7: /* 34xxG */
+ switch(product_code){
+ case 0x00:
+ case 0x0A:
+ case 0x1E:
+ case 0x28:
+ case 0x32:
+ m->chip_family=MSPFAMILY_34x0G;
+ supported=TRUE;
+ break;
+ case 0x0f:
+ case 0x19:
+ case 0x2d:
+ case 0x37:
+ case 0x41:
+ m->chip_family=MSPFAMILY_34x5G;
+ supported=TRUE;
+ #ifdef MSP_DEBUG
+ memset(m->registers_present, 0, 256);
+ #define A(num) m->registers_present[(num)]=1;
+ #define B(num1, num2) memset(&(m->registers_present[num1]), 1, num2-num1);
+ A(0x20)
+ A(0x30)
+ A(0x40)
+ A(0x00)
+ B(0x01, 0x08)
+ B(0x0B, 0x0E)
+ A(0x10)
+ B(0x12,0x14)
+ A(0x16)
+ A(0x29)
+ #undef B
+ #undef A
+ #endif
+ break;
+ default:
+ m->chip_family=MSPFAMILY_UNKNOWN;
+ }
+ break;
+ default:
+ m->chip_family=MSPFAMILY_UNKNOWN;
+ }
+
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex, X_INFO, "Found %s%s, rom version 0x%02x, chip_id=0x%04x\n",
+ MSP_getProductName(m->chip_id), supported?"":" (unsupported)", rom_version, m->chip_id);
+
+ if (!supported) {
+ free(m->d.DevName);
+ free(m);
+ return NULL;
+ }
+ if(!I2CDevInit(&(m->d)))
+ {
+ free(m->d.DevName);
+ free(m);
+ return NULL;
+ }
+
+ return m;
+}
+
+void ResetMSP3430(MSP3430Ptr m)
+{
+ /* Reset the MSP3430 */
+ SetMSP3430Control(m, 0x00, 0x80, 0x00);
+ /* Set it back to normal operation */
+ SetMSP3430Control(m, 0x00, 0x00, 0x00);
+
+ m->c_format=MSPFORMAT_UNKNOWN;
+ m->c_standard=MSPSTANDARD_UNKNOWN;
+ m->c_matrix=m->c_fmmatrix=m->c_source=0;
+ m->volume=0;
+}
+
+void MSP3430SetVolume (MSP3430Ptr m, CARD8 value)
+{
+ CARD8 result;
+#if 0
+ CARD8 old_volume;
+ GetMSP3430Data(m, RD_DSP, 0x00, 0x00, &old_volume, &result);
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex, X_INFO, "MSP3430 result 0x%02x\n", result);
+#endif
+ /* save an extra Get call */
+ result=0;
+
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x00, value, result);
+
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x07, value, 0);
+ m->volume=value;
+
+#if __MSPDEBUG__ > 2
+ MSP3430DumpStatus(m);
+ __MSPBEEP
+ GetMSP3430Data(m, RD_DSP, 0x00, 0x00, &old_volume, &result);
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex, X_INFO, "MSP3430 volume 0x%02x\n",value);
+#endif
+}
+
+
+void MSP3430SetSAP (MSP3430Ptr m, int mode)
+{
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex, X_INFO, "Put actual code to change SAP here\n");
+
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x08, mode & 0xff, 0x20);
+}
+
+
+#if 0
+void MSP3430SetSource(MSP3430Ptr m, CARD8 value)
+{
+ /* Write to DSP, register 0x0008, (loudspeaker channel source/matrix) */
+ /* This sets the source to the TV tuner, for stereo operation */
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x08, value, 0x20);
+}
+#endif
+
+
+char *MSP_getProductName (CARD16 product_id)
+{
+ switch (product_id) {
+ case 0x0400: return "MSP3400D";
+ case 0x040a: return "MSP3410D";
+ case 0x0405: return "MSP3405D";
+ case 0x040f: return "MSP3415D";
+ case 0x0700: return "MSP3400G";
+ case 0x070a: return "MSP3410G";
+ case 0x071e: return "MSP3430G";
+ case 0x0728: return "MSP3440G";
+ case 0x0732: return "MSP3450G";
+ case 0x070f: return "MSP3415G";
+ case 0x0719: return "MSP3425G";
+ case 0x072d: return "MSP3445G";
+ case 0x0737: return "MSP3455G";
+ case 0x0741: return "MSP3465G";
+ }
+ return "MSP - unknown type";
+}
+
+#if __MSPDEBUG__ > 2
+/*puts beep in MSP output
+ freq = 0x01 - 16Hz ... 0x40 - 1kHz ... 0xff - 4kHz
+*/
+void MSPBeep(MSP3430Ptr m, CARD8 freq) {
+ SetMSP3430Data (m, WR_DSP, 0x00, freq, 0x7f, 0x40);
+ mpause(100);
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x14, 0x00, 0x00);
+}
+#endif
+
+void mpause(int milliseconds) {
+ int i,m;
+ m=milliseconds/20;
+ for (i=0;i<m;i++) usleep(20000);
+}
+
+/*-----------------------------------------------------------------
+| specific functions for all MSP34xxG chips
+|----------------------------------------------------------------*/
+
+void InitMSP34xxG(MSP3430Ptr m)
+{
+
+ #if __MSPDEBUG__ > 1
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_INFO,"InitMSP34xxG(m->connector=%d, m->standard=%d, m->chip_family=%d)\n",
+ m->connector, m->standard, m->chip_family);
+ #endif
+ /* Reset MSP3430 */
+ SetMSP3430Control(m, 0x00, 0x80, 0x00);
+ /* Set it back to normal operation */
+ SetMSP3430Control(m, 0x00, 0x00, 0x00);
+
+ /*set MODUS register */
+ /* bits: 0 - automatic sound detection */
+ /* 1 - enable STATUS change */
+ /* 12 - detect 6.5 Mhz carrier as D/K1, D/K2 or D/K NICAM (does not seem to work ) */
+ /* 13 - detect 4.5 Mhz carrier as BTSC */
+ if ( (m->standard & 0xff) == MSP3430_PAL )
+ {
+ SetMSP3430Data(m, WR_DEM, 0x00, 0x30, 0x30, 0x03|0x08); /* make O_ pins tristate */
+ /* PAL standard */
+ SetMSP3430Data(m, WR_DEM, 0x00, 0x20, 0x00, 0x01); /* possibly wrong */
+ } else {
+ SetMSP3430Data(m, WR_DEM, 0x00, 0x30, 0x20, 0x03|0x08);
+ /* standard selection is M-BTSC-Stereo */
+ SetMSP3430Data(m, WR_DEM, 0x00, 0x20, 0x00, 0x20);
+ }
+
+ switch(m->connector){
+ case MSP3430_CONNECTOR_1:
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x08, 0x03, 0x20);
+ break;
+ case MSP3430_CONNECTOR_2:
+ /* this has not been checked yet.. could be bogus */
+ /* SCART Input Prescale: 0 dB gain */
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x0d, 0x19, 0x00);
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x08, 0x02, 0x20);
+ break;
+ case MSP3430_CONNECTOR_3:
+ default:
+ /* SCART Input Prescale: 0 dB gain */
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x0d, 0x19, 0x00);
+
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x08, 0x02, 0x20);
+ break;
+ }
+
+ switch(m->standard){
+ case MSP3430_PAL:
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x0e, 0x24, 0x03);
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x10, 0x00, 0x5a);
+ SetMSP3430Data(m, WR_DEM, 0x00, 0x20, 0x00, 0x03);
+ /* Set volume to FAST_MUTE. */
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x00, 0xFF, 0x00);
+ break;
+ case MSP3430_PAL_DK1:
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x0e, 0x24, 0x03);
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x10, 0x00, 0x5a);
+ SetMSP3430Data(m, WR_DEM, 0x00, 0x20, 0x00, 0x04);
+ /* Set volume to FAST_MUTE. */
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x00, 0xFF, 0x00);
+ break;
+ case MSP3430_SECAM: /* is this right ? */
+ case MSP3430_NTSC:
+ /* Write to DSP, register 0x000E, (prescale FM/FM matrix) */
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x0e, 0x24, 0x03);
+
+ /* Set volume to FAST_MUTE. */
+ SetMSP3430Data(m, WR_DSP, 0x00, 0x00, 0xFF, 0x00);
+ break;
+ }
+
+}
+
+/*-----------------------------------------------------------------
+| specific functions for all MSP34x5D chips
+|----------------------------------------------------------------*/
+
+void InitMSP34x5D(MSP3430Ptr m)
+{
+int count;
+CARD8 high,low;
+CARD16 result,standard;
+CARD16 peak;
+
+
+if (m->c_format==MSPFORMAT_UNKNOWN) ResetMSP3430(m);
+else {
+ /*mute volume*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x00, 0x00, 0x00);
+}
+
+
+
+ switch(m->connector){
+ case MSP3430_CONNECTOR_2:
+ case MSP3430_CONNECTOR_3:
+ if (m->c_format!=MSPFORMAT_SCART) {
+ /* SCART Input Prescale: 0 dB gain */
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0d, 0x19, 0x00);
+ /* this has not been checked yet.. could be bogus */
+ m->c_format=MSPFORMAT_SCART; /*stereo*/
+ }
+ break;
+ case MSP3430_CONNECTOR_1:
+ default:
+
+ switch ( m->standard & 0x00ff ) {
+ case MSP3430_PAL:
+ switch( m->standard ) {
+ case MSP3430_PAL_DK1:
+ standard=MSPSTANDARD_FM_DK1;
+ break;
+/* case MSP3430_PAL_DK2:
+ standard=MSPSTANDARD_FM_DK2;
+ break;
+ case MSP3430_PAL_BG:
+ may be FM stereo (Germany) or FM NICAM (Scandinavia,spain)
+ standard=MSPSTANDARD_AUTO;
+ break;
+*/
+ default:
+ standard=MSPSTANDARD_AUTO;
+ }
+ break;
+ case MSP3430_SECAM:
+ standard=MSPSTANDARD_AUTO;
+ case MSP3430_NTSC:
+ /* Only MSP34x5 supported format - Korean NTSC-M*/
+ standard=MSPSTANDARD_FM_M;
+ default:
+ standard=MSPSTANDARD_AUTO;
+ }
+
+ /*no NICAM support in MSP3410D - force to autodetect*/
+ if ((m->chip_id==0x405) && (standard>=MSPSTANDARD_NICAM_BG))
+ standard=MSPSTANDARD_AUTO;
+
+ if (m->c_standard != standard) {
+
+ SetMSP3430Data (m, WR_DEM, 0x00, 0x20, standard>>8, standard & 0xFF);
+ if (standard==MSPSTANDARD_AUTO) {
+ count = 50; /* time shouldn't exceed 1s, just in case */
+ do {
+ usleep(20000);
+ GetMSP3430Data (m, RD_DEM, 0x00, 0x7e, &high, &low);
+ result = ( high << 8 ) | low;
+ --count;
+ } while( result > 0x07ff && count > 0 );
+
+ if ((result > MSPSTANDARD_AUTO))
+ standard=result;
+ else standard=MSPSTANDARD_UNKNOWN;
+#if __MSPDEBUG__ > 1
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_INFO,"Detected audio standard: %d\n",result);
+#endif
+ /* result = MSPSTANDARD_NICAM_L can be one of:
+ SECAM_L - MSPSTANDARD_NICAM_L
+ D/K1 - MSPSTANDARD_FM_DK1
+ D/K2 - MSPSTANDARD_FM_DK2
+ D/K-NICAM - MSPSTANDARD_NICAM_DK*/
+ if( standard == MSPSTANDARD_NICAM_L ) {
+ if ((m->standard & 0x00ff)==MSP3430_PAL) {
+ /* force PAL D/K */
+ standard=MSPSTANDARD_FM_DK1;
+ SetMSP3430Data (m, WR_DEM, 0x00, 0x20, standard>>8, standard & 0xFF);
+#if __MSPDEBUG__ > 1
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_INFO, "Detected 6.5MHz carrier - forced to D/K1 !!!\n" );
+#endif
+ }
+ }
+ }
+ m->c_standard=standard;
+ } /*end - standard changed*/
+ else {
+ if (standard<MSPSTANDARD_NICAM_BG) {
+ /* get old value of ident. mode register*/
+ GetMSP3430Data (m, RD_DSP, 0x00, 0x15, &high, &low);
+ /* reset Ident-Filter */
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x14, 0x00, 0x3F);
+ /* put back old value to ident. mode register*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x14, 0x00, low);
+ }
+ }
+
+ if (standard<=MSPSTANDARD_AUTO) {
+ m->c_format=MSPFORMAT_1xFM;
+ }
+ else if (standard<MSPSTANDARD_NICAM_BG) {
+ /* set FM prescale */
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0e, 0x30, 0);
+ /* set FM deemphasis*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0f, ((standard==MSPSTANDARD_FM_M)?0:1), 0);
+
+ /* check if FM2 carrier is present */
+ /*turn off FM DC Notch*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x17, 0x00, 0x3f);
+ /*matrix source for Quasi-Peak Detector - stereo: ch2->L ch1->R*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0c, 0x00, 0x20);
+
+ mpause(250);
+ GetMSP3430Data (m, RD_DSP, 0x00, 0x1A, &high, &low);
+ peak = (high << 8) | low;
+#if __MSPDEBUG__ > 1
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_INFO,"Second carrier Quasi-Peak detection: %d\n",peak);
+#endif
+ /*turn on FM DC Notch*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x17, 0x00, 0x00);
+
+ if (peak<5) {
+ /* if second carrier not detected - only mono from first carrier*/
+ m->c_format=MSPFORMAT_1xFM;
+ }
+ else {
+ m->c_format=MSPFORMAT_2xFM;
+ /*start of FM identification process - FM_WAIT
+ wait at least 0.5s - used 1s - gives beter resolution*/
+ mpause(1000);
+ }
+ }
+ else {
+ if (standard==MSPSTANDARD_NICAM_L) {
+ m->c_format=MSPFORMAT_NICAM_AM;
+ /* set AM prescale */
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0e, 0x7C, 0);
+ }
+ else {
+ m->c_format=MSPFORMAT_NICAM_FM;
+ /* set FM prescale */
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0e, 0x30, 0);
+ }
+ /* set FM deemphasis*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0f, 0x00, 0);
+ /* set NICAM prescale to 0dB */
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x10, 0x20, 0);
+ }
+
+ break;
+ } /*end - case conector*/
+
+ CheckModeMSP34x5D(m);
+
+ /* Set volume to FAST_MUTE. */
+ /*SetMSP3430Data(m, WR_DSP, 0x00, 0x00, 0xFF, 0x00);*/
+ /*set volume*/
+ MSP3430SetVolume(m,m->volume);
+
+ __MSPBEEP
+
+
+} /* EnableMSP34x5D ()... */
+
+
+
+
+void CheckModeMSP34x5D(MSP3430Ptr m) {
+ const char stereo_on=25;
+ const char stereo_off=20;
+ const char dual_on=-stereo_on;
+ const char dual_off=-stereo_off;
+ char detect;
+ CARD8 matrix, fmmatrix, source, high, low;
+
+ fmmatrix=0; /*no matrix*/
+ source=0; /*FM*/
+ switch (m->c_format) {
+ case MSPFORMAT_NICAM_FM:
+ case MSPFORMAT_NICAM_AM:
+ case MSPFORMAT_SCART:
+ source=( (m->c_format == MSPFORMAT_SCART)?2:1 );
+ switch (m->mode) {
+ case MSPMODE_MONO:
+ matrix=0x30; /*MONO*/
+ break;
+ case MSPMODE_A:
+ matrix=0x00; /*A*/
+ break;
+ case MSPMODE_B:
+ matrix=0x10; /*B*/
+ break;
+ default:
+ matrix=0x20; /*STEREO*/
+ break;
+ }
+ break;
+ default:
+ case MSPFORMAT_1xFM:
+ matrix=0x00; /*A*/
+ break;
+ case MSPFORMAT_2xFM:
+ switch (m->mode) {
+ case MSPMODE_MONO:
+ matrix=0x30; /*MONO*/
+ break;
+ case MSPMODE_STEREO:
+ matrix=0x20; /*STEREO*/
+ fmmatrix=((m->c_standard==MSPSTANDARD_FM_M)?2:1);
+ break;
+ case MSPMODE_AB:
+ matrix=0x20; /*STEREO*/
+ break;
+ case MSPMODE_A:
+ matrix=0x00; /*A*/
+ break;
+ case MSPMODE_B:
+ matrix=0x10; /*B*/
+ break;
+ default:
+ /*FM_IDENT_CHECK*/
+ GetMSP3430Data (m, RD_DSP, 0x00, 0x18, &high, &low);
+ detect=(char)high;
+#if __MSPDEBUG__ > 1
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_INFO,"Stereo Detection Register: %d\n",detect);
+#endif
+ if (detect>=((m->c_mode==MSPMODE_STEREO)?stereo_off:stereo_on)) {
+ m->c_mode=MSPMODE_STEREO;
+ matrix=0x20; /*STEREO*/
+ fmmatrix=((m->c_standard==MSPSTANDARD_FM_M)?2:1);
+ }
+ else if (detect<=((m->c_mode==MSPMODE_AB)?dual_off:dual_on)) {
+ m->c_mode=MSPMODE_AB;
+ switch (m->mode) {
+ case MSPMODE_STEREO_AB: matrix=0x20; break;
+ case MSPMODE_STEREO_B: matrix=0x10; break;
+ default:
+ case MSPMODE_A: matrix=0x00; break;
+ }
+ }
+ else {
+ m->c_mode=MSPMODE_MONO;
+ matrix=0x30; /*MONO*/
+ }
+ break;
+ } /* end - case mode*/
+ break;
+ }
+
+ if (m->c_fmmatrix != fmmatrix) {
+ GetMSP3430Data (m, RD_DSP, 0x00, 0x0e, &high, &low);
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x0e, high, fmmatrix);
+ m->c_fmmatrix = fmmatrix;
+ }
+
+ if ((m->c_matrix != matrix) || (m->c_source != source)) {
+ /*set chanel source and matrix for loudspeaker*/
+ SetMSP3430Data (m, WR_DSP, 0x00, 0x08, source, matrix);
+
+ m->c_matrix = matrix;
+ m->c_source = source;
+ }
+
+ if ( ((m->c_format) & 0xF0) == MSPFORMAT_NICAM)
+ SetMSP3430Data (m, WR_DEM, 0x00, 0x21, 0, 1);
+
+#if __MSPDEBUG__ > 0
+ char *msg;
+ switch (matrix) {
+ case 0x30: /*MONO*/
+ msg="MONO";
+ break;
+ case 0x00: /*LEFT*/
+ msg="MONO/CHANNEL_1";
+ break;
+ case 0x10: /*RIGHT*/
+ msg="MONO/CHANNEL_2";
+ break;
+ case 0x20: /*LEFT*/
+ msg="STEREO";
+ break;
+ default:
+ msg="unknown";
+ break;
+ }
+ xf86DrvMsg(m->d.pI2CBus->scrnIndex,X_INFO,"Audio mode set to: %s\n",msg);
+#endif
+}
+
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.h
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.h:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/msp3430.h Tue Aug 16 07:38:15 2016
@@ -0,0 +1,113 @@
+#ifndef __MSP3430_H__
+#define __MSP3430_H__
+
+#include "xf86i2c.h"
+
+typedef struct {
+ I2CDevRec d;
+
+ int standard;
+ int connector;
+ int mode;
+
+ CARD8 hardware_version, major_revision, product_code, rom_version;
+#ifdef MSP_DEBUG
+ CARD8 registers_present[256];
+#endif
+
+ CARD16 chip_id;
+ CARD8 chip_family;
+ Bool recheck; /*reinitialization needed after channel change */
+ CARD8 c_format; /*current state of audio format */
+ CARD16 c_standard; /*current state of standard register */
+ CARD8 c_source; /*current state of source register */
+ CARD8 c_matrix; /*current state of matrix register */
+ CARD8 c_fmmatrix; /*current state of fmmatrix register */
+ int c_mode; /* current state of mode for autoswitchimg */
+ CARD8 volume;
+ } MSP3430Rec, * MSP3430Ptr;
+
+
+#define MSP3430_ADDR_1 0x80
+#define MSP3430_ADDR_2 0x84
+#define MSP3430_ADDR_3 0x88
+
+#define MSP3430_PAL 1
+#define MSP3430_NTSC 2
+#define MSP3430_PAL_DK1 (0x100 | MSP3430_PAL)
+#define MSP3430_SECAM 3
+
+#define MSP3430_CONNECTOR_1 1 /* tuner on AIW cards */
+#define MSP3430_CONNECTOR_2 2 /* SVideo on AIW cards */
+#define MSP3430_CONNECTOR_3 3 /* composite on AIW cards */
+
+#define MSP3430_ADDR(a) ((a)->d.SlaveAddr)
+
+#define MSP3430_FAST_MUTE 0xFF
+/* a handy volume transform function, -1000..1000 -> 0x01..0x7F */
+#define MSP3430_VOLUME(value) (0x01+(0x7F-0x01)*log(value+1001)/log(2001))
+
+/*----------------------------------------------------------*/
+
+/* MSP chip families */
+#define MSPFAMILY_UNKNOWN 0
+#define MSPFAMILY_34x0D 1
+#define MSPFAMILY_34x5D 2
+#define MSPFAMILY_34x0G 3
+#define MSPFAMILY_34x5G 4
+
+/* values for MSP standard */
+#define MSPSTANDARD_UNKNOWN 0x00
+#define MSPSTANDARD_AUTO 0x01
+#define MSPSTANDARD_FM_M 0x02
+#define MSPSTANDARD_FM_BG 0x03
+#define MSPSTANDARD_FM_DK1 0x04
+#define MSPSTANDARD_FM_DK2 0x04
+#define MSPSTANDARD_NICAM_BG 0x08
+#define MSPSTANDARD_NICAM_L 0x09
+#define MSPSTANDARD_NICAM_I 0x0A
+#define MSPSTANDARD_NICAM_DK 0x0B
+
+/* values for MSP format */
+#define MSPFORMAT_UNKNOWN 0x00
+#define MSPFORMAT_FM 0x10
+#define MSPFORMAT_1xFM 0x00|MSPFORMAT_FM
+#define MSPFORMAT_2xFM 0x01|MSPFORMAT_FM
+#define MSPFORMAT_NICAM 0x20
+#define MSPFORMAT_NICAM_FM 0x00|MSPFORMAT_NICAM
+#define MSPFORMAT_NICAM_AM 0x01|MSPFORMAT_NICAM
+#define MSPFORMAT_SCART 0x30
+
+/* values for MSP mode */
+#define MSPMODE_UNKNOWN 0
+/* automatic modes */
+#define MSPMODE_STEREO_AB 1
+#define MSPMODE_STEREO_A 2
+#define MSPMODE_STEREO_B 3
+/* forced modes */
+#define MSPMODE_MONO 4
+#define MSPMODE_STEREO 5
+#define MSPMODE_AB 6
+#define MSPMODE_A 7
+#define MSPMODE_B 8
+/*----------------------------------------------------------*/
+
+#define xf86_InitMSP3430 InitMSP3430
+extern _X_EXPORT void InitMSP3430(MSP3430Ptr m);
+#define xf86_DetectMSP3430 DetectMSP3430
+extern _X_EXPORT MSP3430Ptr DetectMSP3430(I2CBusPtr b, I2CSlaveAddr addr);
+#define xf86_ResetMSP3430 ResetMSP3430
+extern _X_EXPORT void ResetMSP3430(MSP3430Ptr m);
+#define xf86_MSP3430SetVolume MSP3430SetVolume
+extern _X_EXPORT void MSP3430SetVolume (MSP3430Ptr m, CARD8 value);
+#define xf86_MSP3430SetSAP MSP3430SetSAP
+extern _X_EXPORT void MSP3430SetSAP (MSP3430Ptr m, int mode);
+
+#define MSP3430SymbolsList \
+ "InitMSP3430", \
+ "DetectMSP3430", \
+ "ResetMSP3430", \
+ "MSP3430SetVolume", \
+ "MSP3430SetSAP"
+
+#endif
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.c
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.c:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.c Tue Aug 16 07:38:15 2016
@@ -0,0 +1,104 @@
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include "xf86.h"
+#include "xf86i2c.h"
+#include "tda9885.h"
+#include "i2c_def.h"
+
+
+TDA9885Ptr Detect_tda9885(I2CBusPtr b, I2CSlaveAddr addr)
+{
+ TDA9885Ptr t;
+ I2CByte a;
+
+ t = calloc(1, sizeof(TDA9885Rec));
+ if(t == NULL) return NULL;
+ switch(addr)
+ {
+ case TDA9885_ADDR_1:
+ case TDA9885_ADDR_2:
+ case TDA9885_ADDR_3:
+ case TDA9885_ADDR_4:
+ t->d.DevName = "TDA9885 Alignment-free IF-PLL";
+ break;
+ default:
+ t->d.DevName = "Generic TDAxxxx";
+ break;
+ }
+ t->d.SlaveAddr = addr;
+ t->d.pI2CBus = b;
+ t->d.NextDev = NULL;
+ t->d.StartTimeout = b->StartTimeout;
+ t->d.BitTimeout = b->BitTimeout;
+ t->d.AcknTimeout = b->AcknTimeout;
+ t->d.ByteTimeout = b->ByteTimeout;
+
+ if(!I2C_WriteRead(&(t->d), NULL, 0, &a, 1))
+ {
+ free(t);
+ return NULL;
+ }
+
+ /* set default parameters */
+ if(!I2CDevInit(&(t->d)))
+ {
+ free(t);
+ return NULL;
+ }
+
+ return t;
+}
+
+Bool tda9885_init(TDA9885Ptr t)
+{
+ t->forced_mute_audio=1;
+ return TRUE;
+}
+
+void tda9885_getstatus(TDA9885Ptr t)
+{
+CARD8 value;
+
+I2C_WriteRead(&(t->d), NULL, 0, &value, 1);
+t->after_reset=value & 1;
+t->afc_status=(value >> 1) & 0xf;
+t->fm_carrier=(value>>5)& 1;
+t->vif_level=(value >>6) & 1;
+t->afc_win=(value >> 7)&1;
+}
+
+void tda9885_setparameters(TDA9885Ptr t)
+{
+CARD8 data[4];
+
+data[0]=0; /* start with subaddress 0 */
+data[1]=(t->sound_trap & 1) |
+ ((t->auto_mute_fm &1)<<1) |
+ ((t->carrier_mode &1)<<2) |
+ ((t->modulation &3)<<3) |
+ ((t->forced_mute_audio &1)<<5) |
+ ((t->port1 & 1)<<6) |
+ ((t->port2 &1)<<7); /* B data */
+data[2]=(t->top_adjustment & 0x1f) |
+ ((t->deemphasis & 0x3)<<5) |
+ ((t->audio_gain & 1) << 7); /* C data */
+data[3]=(t->standard_sound_carrier & 0x3) |
+ ((t->standard_video_if & 0x07)<<2) |
+ ((t->minimum_gain & 0x01)<<5) |
+ ((t->gating & 0x01)<<6) |
+ ((t->vif_agc & 0x01)<<7); /* E data */
+
+I2C_WriteRead(&(t->d), data, 4, NULL, 0);
+
+xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"TDA9885 setparam: B data: %x, C data: %x, E data: %x\n", data[1], data[2], data[3]);
+}
+
+void tda9885_dumpstatus(TDA9885Ptr t)
+{
+xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"TDA9885 status: after_reset=%d afc_status=%d (%3.1f kHz off) fm_carrier=%d vif_level=%d afc_win=%d %s\n",
+ t->after_reset, t->afc_status,
+ (t->afc_status<8)?-12.5-t->afc_status*25.0:-12.5+(16-t->afc_status)*25.0,
+ t->fm_carrier, t->vif_level, t->afc_win, t->afc_win?"VCO in": "VCO out");
+}
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.h
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.h:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/tda9885.h Tue Aug 16 07:38:15 2016
@@ -0,0 +1,59 @@
+#ifndef __TDA9885_H__
+#define __TDA9885_H__
+
+#include "xf86i2c.h"
+
+typedef struct {
+ I2CDevRec d;
+
+ /* write-only parameters */
+ /* B DATA */
+ CARD8 sound_trap;
+ CARD8 auto_mute_fm;
+ CARD8 carrier_mode;
+ CARD8 modulation;
+ CARD8 forced_mute_audio;
+ CARD8 port1;
+ CARD8 port2;
+ /* C DATA */
+ CARD8 top_adjustment;
+ CARD8 deemphasis;
+ CARD8 audio_gain;
+ /* E DATA */
+ CARD8 standard_sound_carrier;
+ CARD8 standard_video_if;
+ CARD8 minimum_gain;
+ CARD8 gating;
+ CARD8 vif_agc;
+ /* read-only values */
+
+ CARD8 after_reset;
+ CARD8 afc_status;
+ CARD8 vif_level;
+ CARD8 afc_win;
+ CARD8 fm_carrier;
+ } TDA9885Rec, *TDA9885Ptr;
+
+#define TDA9885_ADDR_1 0x86
+#define TDA9885_ADDR_2 0x84
+#define TDA9885_ADDR_3 0x96
+#define TDA9885_ADDR_4 0x94
+
+#define xf86_Detect_tda9885 Detect_tda9885
+extern _X_EXPORT TDA9885Ptr Detect_tda9885(I2CBusPtr b, I2CSlaveAddr addr);
+#define xf86_tda9885_init tda9885_init
+extern _X_EXPORT Bool tda9885_init(TDA9885Ptr t);
+#define xf86_tda9885_setparameters tda9885_setparameters
+extern _X_EXPORT void tda9885_setparameters(TDA9885Ptr t);
+#define xf86_tda9885_getstatus tda9885_getstatus
+extern _X_EXPORT void tda9885_getstatus(TDA9885Ptr t);
+#define xf86_tda9885_dumpstatus tda9885_dumpstatus
+extern _X_EXPORT void tda9885_dumpstatus(TDA9885Ptr t);
+
+#define TDA9885SymbolsList \
+ "Detect_tda9885", \
+ "tda9885_init", \
+ "tda9885_setaudio", \
+ "tda9885_mute"
+
+#endif
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.c
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.c:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.c Tue Aug 16 07:38:15 2016
@@ -0,0 +1,183 @@
+/*************************************************************************************
+ * Copyright (C) 2005 Bogdan D. [email protected]
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this
+ * software and associated documentation files (the "Software"), to deal in the Software
+ * without restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the author shall not be used in advertising or
+ * otherwise to promote the sale, use or other dealings in this Software without prior written
+ * authorization from the author.
+ *
+ ************************************************************************************/
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include "xf86.h"
+#include "xf86i2c.h"
+#include "uda1380.h"
+#include "i2c_def.h"
+
+UDA1380Ptr Detect_uda1380(I2CBusPtr b, I2CSlaveAddr addr)
+{
+ UDA1380Ptr t;
+ I2CByte a;
+
+ t = calloc(1, sizeof(UDA1380Rec));
+ if(t == NULL) return NULL;
+ switch(addr)
+ {
+ case UDA1380_ADDR_1:
+ case UDA1380_ADDR_2:
+ t->d.DevName = "UDA1380 Stereo audion coder-decoder";
+ break;
+ default:
+ t->d.DevName = "Generic UDAxxxx";
+ break;
+ }
+ t->d.SlaveAddr = addr;
+ t->d.pI2CBus = b;
+ t->d.NextDev = NULL;
+ t->d.StartTimeout = b->StartTimeout;
+ t->d.BitTimeout = b->BitTimeout;
+ t->d.AcknTimeout = b->AcknTimeout;
+ t->d.ByteTimeout = b->ByteTimeout;
+
+ if(!I2C_WriteRead(&(t->d), NULL, 0, &a, 1))
+ {
+ free(t);
+ return NULL;
+ }
+
+ /* set default parameters */
+ if(!I2CDevInit(&(t->d)))
+ {
+ free(t);
+ return NULL;
+ }
+
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 stereo coder-decoder detected\n");
+
+ return t;
+}
+
+Bool uda1380_init(UDA1380Ptr t)
+{
+ CARD8 data[3];
+ CARD16 tmp;
+ Bool ret;
+
+ /* Power control */
+ data[0] = 0x02;
+ tmp = (1 << 13) | (1 << 10) | ( 1 << 8) | (1 << 7) | (1 << 6) | (1 << 3) | (1 << 1);
+ data[1] = (CARD8)((tmp >> 8) & 0xff);
+ data[2] = (CARD8)(tmp & 0xff);
+ ret = I2C_WriteRead(&(t->d), data, 3, NULL, 0);
+ if (ret == FALSE)
+ {
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 failed to initialize\n");
+ return FALSE;
+ }
+
+ /* Analog mixer (AVC) */
+ data[0] = 0x03;
+ /* the analog mixer is muted initially */
+ data[1] = 0x3f;
+ data[2] = 0x3f;
+ ret = I2C_WriteRead(&(t->d), data, 3, NULL, 0);
+ if (ret == FALSE)
+ {
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 failed to initialize\n");
+ return FALSE;
+ }
+
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 initialized\n");
+
+ return TRUE;
+}
+
+void uda1380_shutdown(UDA1380Ptr t)
+{
+ CARD8 data[3];
+ Bool ret;
+
+ /* Power control */
+ data[0] = 0x02;
+ data[1] = 0;
+ data[2] = 0;
+ ret = I2C_WriteRead(&(t->d), data, 3, NULL, 0);
+ if (ret == FALSE)
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 failed to shutdown\n");
+}
+
+void uda1380_setvolume(UDA1380Ptr t, INT32 value)
+{
+ CARD8 data[3];
+ /*
+ * We have to scale the value ranging from -1000 to 1000 to 0x2c to 0
+ */
+ CARD8 volume = 47 - (CARD8)((value + 1000) * 47 / 2000);
+ Bool ret;
+
+ t->analog_mixer_settings = ((volume << 8) & 0x3f00) | (volume & 0x3f);
+
+ /* Analog mixer (AVC) */
+ data[0] = 0x03;
+ data[1] = volume & 0x3f;
+ data[2] = volume & 0x3f;
+ ret = I2C_WriteRead(&(t->d), data, 3, NULL, 0);
+ if (ret == FALSE)
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 failed to set volume\n");
+}
+
+void uda1380_mute(UDA1380Ptr t, Bool mute)
+{
+ CARD8 data[3];
+ Bool ret;
+
+ if (mute == TRUE)
+ {
+ /* Analog mixer (AVC) */
+ data[0] = 0x03;
+ data[1] = 0xff;
+ data[2] = 0xff;
+ ret = I2C_WriteRead(&(t->d), data, 3, NULL, 0);
+ if (ret == FALSE)
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 failed to mute\n");
+ }
+ else
+ {
+ /* Analog mixer (AVC) */
+ data[0] = 0x03;
+ data[1] = (CARD8)((t->analog_mixer_settings >> 8) & 0x3f);
+ data[2] = (CARD8)(t->analog_mixer_settings & 0x3f);
+ ret = I2C_WriteRead(&(t->d), data, 3, NULL, 0);
+ if (ret == FALSE)
+ xf86DrvMsg(t->d.pI2CBus->scrnIndex,X_INFO,"UDA1380 failed to unmute\n");
+ }
+}
+
+void uda1380_getstatus(UDA1380Ptr t)
+{
+}
+
+void uda1380_setparameters(UDA1380Ptr t)
+{
+}
+
+void uda1380_dumpstatus(UDA1380Ptr t)
+{
+}
Index: xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.h
diff -u /dev/null xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.h:1.1
--- /dev/null Tue Aug 16 07:38:15 2016
+++ xsrc/external/mit/xf86-video-ati/xorg-server-copy/uda1380.h Tue Aug 16 07:38:15 2016
@@ -0,0 +1,74 @@
+/*************************************************************************************
+ * Copyright (C) 2005 Bogdan D. [email protected]
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this
+ * software and associated documentation files (the "Software"), to deal in the Software
+ * without restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the author shall not be used in advertising or
+ * otherwise to promote the sale, use or other dealings in this Software without prior written
+ * authorization from the author.
+ *
+ * Revision 1.3 2005/09/24 21:56:00 bogdand
+ * Changed the license to a X/MIT one
+ *
+ * Revision 1.2 2005/07/01 22:43:11 daniels
+ * Change all misc.h and os.h references to <X11/foo.h>.
+ *
+ *
+ ************************************************************************************/
+
+#ifndef __UDA1380_H__
+#define __UDA1380_H__
+
+#include "xf86i2c.h"
+
+typedef struct {
+ I2CDevRec d;
+
+ CARD16 analog_mixer_settings; /* register 0x03 */
+
+ } UDA1380Rec, *UDA1380Ptr;
+
+#define UDA1380_ADDR_1 0x30
+#define UDA1380_ADDR_2 0x34
+
+#define xf86_Detect_uda1380 Detect_uda1380
+extern _X_EXPORT UDA1380Ptr Detect_uda1380(I2CBusPtr b, I2CSlaveAddr addr);
+#define xf86_uda1380_init uda1380_init
+extern _X_EXPORT Bool uda1380_init(UDA1380Ptr t);
+#define xf86_uda1380_shutdown uda1380_shutdown
+extern _X_EXPORT void uda1380_shutdown(UDA1380Ptr t);
+#define xf86_uda1380_setvolume uda1380_setvolume
+extern _X_EXPORT void uda1380_setvolume(UDA1380Ptr t, INT32);
+#define xf86_uda1380_mute uda1380_mute
+extern _X_EXPORT void uda1380_mute(UDA1380Ptr t, Bool);
+#define xf86_uda1380_setparameters uda1380_setparameters
+extern _X_EXPORT void uda1380_setparameters(UDA1380Ptr t);
+#define xf86_uda1380_getstatus uda1380_getstatus
+extern _X_EXPORT void uda1380_getstatus(UDA1380Ptr t);
+#define xf86_uda1380_dumpstatus uda1380_dumpstatus
+extern _X_EXPORT void uda1380_dumpstatus(UDA1380Ptr t);
+
+#define UDA1380SymbolsList \
+ "Detect_uda1380", \
+ "uda1380_init", \
+ "uda1380_shutdown", \
+ "uda1380_setvolume", \
+ "uda1380_mute", \
+ "uda1380_setparameters", \
+ "uda1380_getstatus", \
+ "uda1380_dumpstatus"
+
+#endif
